Re: [PATCH 1/6] include: env: phytec: overlays: Add extension command
Am 09.07.24 um 15:31 schrieb Daniel Schultz:
Hi Yannic,
On 09.07.24 08:49, Yannic Moog wrote:
Hello Daniel,
On Sun, 2024-07-07 at 23:07 -0700, Daniel Schultz wrote:
Add a new environment routine to apply extensions. Our SOM detection
adds overlays via the extension framework to alter the kernel
device-tree according to the flashed EEPROM image.
Signed-off-by: Daniel Schultz
---
include/env/phytec/overlays.env | 20
1 file changed, 20 insertions(+)
diff --git a/include/env/phytec/overlays.env
b/include/env/phytec/overlays.env
index 78721cde654..50110e731bd 100644
--- a/include/env/phytec/overlays.env
+++ b/include/env/phytec/overlays.env
@@ -23,6 +23,16 @@ mmc_apply_overlays=
fi;
done;
fi;
+#ifdef CONFIG_CMD_EXTENSION
+mmc_apply_extensions=
+ setenv extension_overlay_addr ${fdtoverlay_addr_r};
+ setenv extension_overlay_cmd 'load mmc ${mmcdev}:${mmcpart}
+ ${fdtoverlay_addr_r} ${extension_overlay_name}';
+ extension scan;
+ extension apply all;
+#else
+mmc_apply_extensions=echo "no extension command"
Do you think it makes sense to make this fail? I would think
"apply_extensions" would be
unsuccessful if extensions are not working.
Technically, you don't need our SOM detection overlays. They just make
the boot nicer and you don't have any probe errors or other error
messages. So, in my opinion, it's better not apply them instead of
stopping the entire boot.
My recommendation is to embed all SoM variant related overlays into
u-boot.img's FIT using binman.
This makes the extension command obsolete, and especially the handling
for loading of overlays from different boot sources / storage devices.
Having them available directly in the u-boot binary resolves the issue
of not found overlays.
We do not know how users will proceed after u-boot booted and if the
overlays will be available to the "extension setup". Better to have
everything in place and fixup to the best we know using our SoM data
stored in the EEPROM.
This kind of overlays should be applied regardless of the boot device.
Regards,
Daniel
Yannic
+#endif
net_load_bootenv=${get_cmd} ${bootenv_addr_r} ${bootenv}
net_load_overlay=${get_cmd} ${fdtoverlay_addr_r} ${overlay}
net_apply_overlays=
@@ -36,3 +46,13 @@ net_apply_overlays=
fi;
done;
fi;
+#ifdef CONFIG_CMD_EXTENSION
+net_apply_extensions=
+ setenv extension_overlay_addr ${fdtoverlay_addr_r};
+ setenv extension_overlay_cmd '${get_cmd} ${fdtoverlay_addr_r}
+ ${extension_overlay_name}';
+ extension scan;
+ extension apply all;
+#else
+net_apply_extensions=echo "no extension command"
+#endif
Re: [PATCH 1/4] configs: phycore_am62x_a53: Add more commands
Am 01.07.24 um 08:20 schrieb Daniel Schultz: Add i2c and rtc commands with all dependencies which are required for testing. Additionally, add smc and cache commands to boot Zephyr on the A53. Signed-off-by: Daniel Schultz For this series, Reviewed-by: Wadim Egorov --- configs/phycore_am62x_a53_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 56302383c0f..06b8834e074 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARM_SMCCC=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -63,9 +64,13 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_DFU=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_SMC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y @@ -123,6 +128,8 @@ CONFIG_TI_SCI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV3028=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y
Re: [PATCH 0/9] Generalize PHYTEC Overlay Handling
Am 03.07.24 um 07:41 schrieb Daniel Schultz: The overlays are specified in the bootenv.txt file that is loaded into the environment. Then these overlays get loaded and applied via a script. These scripts for loading and applying devicetree overlays are identical for many phytec boards. Create a common overlays.env that can be included. Add support for devicetree overlays to phycore-imx8mp and include the overlays.env for phycore-imx93. Rename existing environment variables according to bootstd doc. Move MMC boot logic into a common k3_mmc.env file and include the new overlays.env file as well. Benjamin Hahn (5): include: env: phytec: Create env file for loading and applying overlays phycore-imx8mp: Add overlay and bootenv.txt support phycore_imx93: include common overlays.env board: phytec: renaming of variables according to bootstd doc include: env: phytec: renaming of variables according to bootstd doc Daniel Schultz (4): include: env: phytec: Add common mmc boot for K3 SoMs include: env: phytec: k3_mmc: Apply overlays during boot board: phytec: phycore_am62x: Use k3_mmc.env logic board: phytec: phycore_am64x: Use k3_mmc.env logic For this series, Reviewed-by: Wadim Egorov
Re: [PATCH] board: phytec: k3: k3_ddrss_patch: Add ddr phy reg count
Am 02.07.24 um 11:22 schrieb Dominik Haller:
Add and use the correct number of ddr phy registers to update the
corresponding settings.
Fixes: cbf5c99ef317 ("board: phytec: common: Introduce a method to inject DDR
timings deltas")
Signed-off-by: Dominik Haller
Reviewed-by: Wadim Egorov
---
board/phytec/common/k3/k3_ddrss_patch.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/phytec/common/k3/k3_ddrss_patch.c
b/board/phytec/common/k3/k3_ddrss_patch.c
index 39f7be8dc922..5afe5a20c7f3 100644
--- a/board/phytec/common/k3/k3_ddrss_patch.c
+++ b/board/phytec/common/k3/k3_ddrss_patch.c
@@ -12,6 +12,7 @@
#ifdef CONFIG_K3_AM64_DDRSS
#define LPDDR4_INTR_CTL_REG_COUNT (423U)
#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
#endif
static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
@@ -54,7 +55,7 @@ int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss
*ddrss)
return ret;
}
- for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+ for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
for (j = 0; j < ddrss->phy_regs_num; j++)
if (i == ddrss->phy_regs[j].off) {
ret = fdt_setprop_inplace_idx_u32(fdt,
[PATCH] doc: board: phytec: phycore-am6: Describe UART based boot
Describe how to boot via UART.
Signed-off-by: Wadim Egorov
---
For next
---
doc/board/phytec/phycore-am62x.rst | 17 +
doc/board/phytec/phycore-am64x.rst | 19 +++
2 files changed, 36 insertions(+)
diff --git a/doc/board/phytec/phycore-am62x.rst
b/doc/board/phytec/phycore-am62x.rst
index a615d01474e..5f02a9db5f8 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -118,6 +118,23 @@ tiboot3.bin, tispl.bin and u-boot.img are stored on the
uSD card.
fatload mmc 1 ${loadaddr} u-boot.img
mtd write ospi.u-boot ${loadaddr} 0 ${filesize}
+UART based boot
+---
+
+To boot the board via UART, set the switches to UART mode and connect to the
+micro USB port labeled as "Debug UART". After power-on the build artifacts
+needs to be uploaded one by one with a tool like sz.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device. Assuming the host uses /dev/ttyUSB0 as
+the main domain serial port:
+
+.. prompt:: bash $
+
+ stty -F /dev/ttyUSB0 115200
+ sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem tispl.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem u-boot.img > /dev/ttyUSB0 < /dev/ttyUSB0
Boot Modes
--
diff --git a/doc/board/phytec/phycore-am64x.rst
b/doc/board/phytec/phycore-am64x.rst
index 189da179534..e7f8656e1bf 100644
--- a/doc/board/phytec/phycore-am64x.rst
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -119,6 +119,25 @@ tiboot3.bin, tispl.bin and u-boot.img are stored on the
uSD card.
fatload mmc 1 ${loadaddr} u-boot.img
mtd write ospi.u-boot ${loadaddr} 0 ${filesize}
+UART based boot
+---
+
+To boot the board via UART, set the switches to UART mode and connect to the
+micro USB port labeled as "Debug UART". After power-on the build artifacts
+needs to be uploaded one by one with a tool like sz.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device. Assuming the host uses /dev/ttyUSB0 as
+the main domain serial port:
+
+.. prompt:: bash $
+
+ stty -F /dev/ttyUSB0 115200
+ sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ # Resend tiboot3.bin a 2nd time due to ErrataID:i2331
+ sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem tispl.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem u-boot.img > /dev/ttyUSB0 < /dev/ttyUSB0
Boot Modes
--
--
2.34.1
Re: [PATCH 1/6] arm: mach-k3: Add default ATF location for AM62/AM62a
Am 19.06.24 um 22:02 schrieb Andrew Davis: On 6/19/24 1:20 PM, Nishanth Menon wrote: On 17:19-20240619, Dhruva Gole wrote: Hi, On Feb 14, 2024 at 10:30:04 -0600, Andrew Davis wrote: There is a default ATF load address that is used for devices that have ATF running in SRAM. For AM62 and AM62a, ATF runs from DRAM. Instead of having to override the address in every defconfig, make add a default for these ATF in DRAM devices. Signed-off-by: Andrew Davis --- arch/arm/mach-k3/Kconfig | 5 +++-- configs/am62ax_evm_a53_defconfig | 1 - configs/am62x_beagleplay_a53_defconfig | 1 - configs/am62x_evm_a53_defconfig | 1 - configs/phycore_am62x_a53_defconfig | 1 - configs/verdin-am62_a53_defconfig | 1 - 6 files changed, 3 insertions(+), 7 deletions(-) Beagleplay stops booting completely with latest U-boot so I did a little bisect and it seems like reverting this patch helps. I am not sure what other implications there are of reverting this so I don't suggest immediately dropping it, however some hints around what's missing on beagleplay vs other platforms would be helpful. Because other platforms based off the same SoC don't seem to be affected. Grumble... I had to rediscover this in parallel as well - Thanks Dhruva. mkimage -l tispl.bin and comparing with kernel log of reserved mem had me completely confused. a) Memory maps are already notorious to manage on complex heterogenous systems. From beagle perspective, we have no need to go and monkey with DT defined memory map and DT should be the default and modifying Your DT source file is wrong, ATF is at 0x8000_ (or any address one wants to put in K3_ATF_LOAD_ADDR). DT doesn't "define" hardware, it "describes" it. ATF's location is dynamic and configurable, it doesn't belong in DT. You have two options, either go update your DT, then update it again every time ATF moves. *OR* simply turn on OF_SYSTEM_SETUP and let U-Boot add the correct location reserved memory node for you. Then you can also drop out the reserved-node from the DT template file. Only U-Boot knows where ATF is really placed in RAM, so U-Boot must add this info to DT. I think it is a good idea to remove the nodes from the device tree or at least mark them as "templates" and note that they are actually provided by the bootloader to make it less confusing. DT should be explicitly called out with a log (instead of done "transparently") - so instead of CONFIG_K3_OPTEE_LOAD_ADDR default being forced from u-boot, it should be made optional, where when defined, it can overide the dt definition or some variant of that. b) Looks like https://lore.kernel.org/u-boot/20240214163009.983034-4-...@ti.com/ missed beagleplay? and we were in for a surprise there - i dont want This was the only miss, OF_SYSTEM_SETUP didn't get added to the beagleplay config. Bryan just sent the fix for that now. I'll go look for a way to make this common across the whole SoC family so we don't again miss any new boards. Andrew to switch from default dts for beagleplay to something different just because of simplicity for users to know exactly the carveouts and with other s/w starting up on uC, dts is our "canonical truth".
Re: [PATCH 1/3] doc: board: phytec: phycore-am62x: Fix Link to Documentation
Am 12.06.24 um 18:16 schrieb Daniel Schultz: We moved our documentation to another hoster and therefore the URL changed. Point to the latest documentation instead of release versions to not link out-dated documentation. Signed-off-by: Daniel Schultz For all three patches, Reviewed-by: Wadim Egorov --- doc/board/phytec/phycore-am62x.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index bc6d5246694..681ac536125 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -155,4 +155,4 @@ Further Information --- Please see :doc:`../ti/am62x_sk` chapter for further AM62 SoC related documentation -and https://docs.phytec.com/phycore-am62x for vendor documentation. +and https://docs.phytec.com/projects/yocto-phycore-am62x/en/latest/ for vendor documentation.
Re: [U-boot] [PATCH 01/13] arch: arm: dts: k3-am625-phyboard-lyra: Add fixed partitions
Am 11.06.24 um 10:08 schrieb Teresa Remmet:
Hello Wadim,
Am Montag, dem 10.06.2024 um 15:33 +0200 schrieb Wadim Egorov:
From: Nathan Morrisson
Add a fixed partitions node to the AM62x device tree so that it can
be used to fixup the Linux device tree.
for which branch is this series?
This patch is for u-boot/next
Somehow it landed also on our internal list, sorry for that.
Regards,
Teresa
Signed-off-by: Nathan Morrisson
Signed-off-by: Wadim Egorov
---
.../k3-am625-phyboard-lyra-rdk-u-boot.dtsi | 26
+++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 94162282068..7c76acc0d59 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -127,6 +127,32 @@
flash@0 {
bootph-all;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x8>;
+ };
+ partition@8 {
+ label = "ospi.tispl";
+ reg = <0x08 0x20>;
+ };
+ partition@28 {
+ label = "ospi.u-boot";
+ reg = <0x28 0x40>;
+ };
+ partition@68 {
+ label = "ospi.env";
+ reg = <0x68 0x4>;
+ };
+ partition@6c {
+ label = "ospi.env.backup";
+ reg = <0x6c 0x4>;
+ };
+ };
};
};
[PATCH 13/13] board: phytec: phycore-am62x: Use memory nodes in higher boot stages
There is no need to reread the EEPROM multiple times in different stages
to detect the RAM size. We can do this once at an early stage and let
higher stages decode memory nodes using fdtdec.
Make sure to pass fixup memory nodes before passing to u-boot stage.
Signed-off-by: Wadim Egorov
---
board/phytec/phycore_am62x/phycore-am62x.c | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c
b/board/phytec/phycore_am62x/phycore-am62x.c
index 35e1bb96b8d..9f6bc736cbb 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -47,7 +47,12 @@ static u8 phytec_get_am62_ddr_size_default(void)
int dram_init(void)
{
- u8 ram_size = phytec_get_am62_ddr_size_default();
+ u8 ram_size;
+
+ if (!IS_ENABLED(CONFIG_CPU_V7R))
+ return fdtdec_setup_mem_size_base();
+
+ ram_size = phytec_get_am62_ddr_size_default();
/*
* HACK: ddrss driver support 2GB RAM by default
@@ -92,6 +97,9 @@ int dram_init_banksize(void)
{
u8 ram_size;
+ if (!IS_ENABLED(CONFIG_CPU_V7R))
+ return fdtdec_setup_memory_banksize();
+
ram_size = phytec_get_am62_ddr_size_default();
switch (ram_size) {
case EEPROM_RAM_SIZE_1GB:
@@ -174,6 +182,26 @@ int do_board_detect(void)
}
#endif
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int bank;
+ int ret;
+
+ dram_init();
+ dram_init_banksize();
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start[bank] = gd->bd->bi_dram[bank].start;
+ size[bank] = gd->bd->bi_dram[bank].size;
+ }
+
+ ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
CONFIG_NR_DRAM_BANKS);
+}
+#endif
+
#define CTRLMMR_USB0_PHY_CTRL 0x43004008
#define CTRLMMR_USB1_PHY_CTRL 0x43004018
#define CORE_VOLTAGE0x8000
--
2.34.1
[PATCH 12/13] doc: board: phytec: phycore-am6: Use mtd commands
Update Flash to SPI NOR chapter for use with mtd commands.
This is more convenient as we do not have to remember any
offsets in the SPI.
Signed-off-by: Wadim Egorov
---
doc/board/phytec/phycore-am62x.rst | 8
doc/board/phytec/phycore-am64x.rst | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/doc/board/phytec/phycore-am62x.rst
b/doc/board/phytec/phycore-am62x.rst
index f8870657be0..a615d01474e 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -110,13 +110,13 @@ tiboot3.bin, tispl.bin and u-boot.img are stored on the
uSD card.
.. code-block:: bash
- sf probe
+ mtd list
fatload mmc 1 ${loadaddr} tiboot3.bin
- sf update $loadaddr 0x0 $filesize
+ mtd write ospi.tiboot3 ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} tispl.bin
- sf update $loadaddr 0x8 $filesize
+ mtd write ospi.tispl ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} u-boot.img
- sf update $loadaddr 0x28 $filesize
+ mtd write ospi.u-boot ${loadaddr} 0 ${filesize}
Boot Modes
diff --git a/doc/board/phytec/phycore-am64x.rst
b/doc/board/phytec/phycore-am64x.rst
index a27ad01027b..189da179534 100644
--- a/doc/board/phytec/phycore-am64x.rst
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -111,13 +111,13 @@ tiboot3.bin, tispl.bin and u-boot.img are stored on the
uSD card.
.. code-block:: bash
- sf probe
+ mtd list
fatload mmc 1 ${loadaddr} tiboot3.bin
- sf update $loadaddr 0x0 $filesize
+ mtd write ospi.tiboot3 ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} tispl.bin
- sf update $loadaddr 0x8 $filesize
+ mtd write ospi.tispl ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} u-boot.img
- sf update $loadaddr 0x28 $filesize
+ mtd write ospi.u-boot ${loadaddr} 0 ${filesize}
Boot Modes
--
2.34.1
[PATCH 11/13] doc: board: phytec: phycore-am62x: Add USB DFU switch config
Provide boot switch config for USB DFU boot. Signed-off-by: Wadim Egorov --- doc/board/phytec/phycore-am62x.rst | 4 1 file changed, 4 insertions(+) diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index bc6d5246694..f8870657be0 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -151,6 +151,10 @@ Boot switches should be changed with power off. - 11011100 - + * - USB DFU + - 11001010 + - 0010 + Further Information --- -- 2.34.1
[PATCH 10/13] configs: phycore_am6xx: Update MTD & SPI configs
Enable mtd command and remove SPI NOR flashes we do not populate on our SoMs. Signed-off-by: Wadim Egorov --- configs/phycore_am62x_a53_defconfig | 4 ++-- configs/phycore_am62x_r5_defconfig | 1 - configs/phycore_am64x_a53_defconfig | 4 ++-- configs/phycore_am64x_r5_defconfig | 1 - 4 files changed, 4 insertions(+), 6 deletions(-) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 5fe2c9d4422..95a48aa246b 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -63,6 +63,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -106,10 +107,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 0062a4e3569..12ba4c06d1e 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -106,7 +106,6 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y -CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_PINCTRL=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index e94d829fd8f..cf04e145372 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -69,6 +69,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_OF_CONTROL=y @@ -120,10 +121,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83867=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 15a7e7089e7..a0d78241928 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -121,7 +121,6 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y -CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_PHY_TI_DP83867=y -- 2.34.1
[PATCH 09/13] board: phytec: phycore-am62x: Pull in k3_dfu.env
Pull in ti/k3_dfu.env for dfu_alt_info_ram in SPL stage. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62x/phycore_am62x.env | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index ada3a9233be..42db26a5990 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -1,3 +1,5 @@ +#include + fdtaddr=0x8800 loadaddr=0x8200 scriptaddr=0x8000 -- 2.34.1
[PATCH 08/13] configs: phycore_am62x_a53_defconfig: Enable DFU boot
Enable configs required for booting via DFU. Configs taken from the am62x_a53_usbdfu.config config fragment. Signed-off-by: Wadim Egorov --- configs/phycore_am62x_a53_defconfig | 28 1 file changed, 28 insertions(+) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 7476bb4a175..5fe2c9d4422 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -53,18 +54,23 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_DFU=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=1 @@ -73,10 +79,15 @@ CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -121,4 +132,21 @@ CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- 2.34.1
[PATCH 07/13] arm: dts: k3-am625-phyboard-lyra-rdk: Enable usb port in u-boot
Enable usb0 in all boot phases for use with DFU.
Signed-off-by: Wadim Egorov
---
arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 7c76acc0d59..2bc5acbec23 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -168,6 +168,15 @@
bootph-all;
};
+ {
+ bootph-all;
+};
+
+ {
+ dr_mode = "peripheral";
+ bootph-all;
+};
+
_3v3_mmc {
bootph-all;
};
--
2.34.1
[PATCH 04/13] board: phytec: phycore-am62x: Fix CONFIG_SPL_BOARD_INIT
Make sure spl_board_init() gets compiled by enabling missing
CONFIG_SPL_BOARD_INIT and including hardware.h.
Fixes: 085cd6459dae ("board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM")
Signed-off-by: Wadim Egorov
---
board/phytec/phycore_am62x/phycore-am62x.c | 1 +
configs/phycore_am62x_a53_defconfig| 1 +
2 files changed, 2 insertions(+)
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c
b/board/phytec/phycore_am62x/phycore-am62x.c
index 4a76f1343d7..35e1bb96b8d 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -4,6 +4,7 @@
* Author: Wadim Egorov
*/
+#include
#include
#include
#include
diff --git a/configs/phycore_am62x_a53_defconfig
b/configs/phycore_am62x_a53_defconfig
index 44f6e77b626..468c0f373b7 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -42,6 +42,7 @@ CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
--
2.34.1
[PATCH 03/13] board: phytec: common: k3: Copy fixed partitions to OS device tree
Copy fixed-partitions nodes from U-Boot device tree to OS device tree.
Signed-off-by: Wadim Egorov
---
board/phytec/common/k3/board.c | 10 ++
configs/phycore_am62x_a53_defconfig | 1 +
2 files changed, 11 insertions(+)
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index f21e154d4fe..3d7e090ccaa 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
@@ -94,3 +95,12 @@ int board_late_init(void)
return 0;
}
#endif
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ fdt_copy_fixed_partitions(blob);
+
+ return 0;
+}
+#endif
diff --git a/configs/phycore_am62x_a53_defconfig
b/configs/phycore_am62x_a53_defconfig
index 7545bf2ea73..44f6e77b626 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -36,6 +36,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
CONFIG_BOOTSTD_FULL=y
CONFIG_SYS_BOOTM_LEN=0x80
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
--
2.34.1
[PATCH 05/13] configs: phycore_am62x: Update environment location
Update environment location to align with OSPI fixed-partition definitions and provide a redundant environment at a 2nd location. Signed-off-by: Wadim Egorov --- configs/phycore_am62x_a53_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 468c0f373b7..7476bb4a175 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -11,7 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b8 CONFIG_SF_DEFAULT_SPEED=2500 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xD000 +CONFIG_ENV_OFFSET=0x68 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk" CONFIG_SPL_TEXT_BASE=0x8008 @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x8 CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x4 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 +CONFIG_ENV_OFFSET_REDUND=0x6c CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -65,6 +66,7 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y -- 2.34.1
[PATCH 06/13] configs: phycore_am64x: Update environment location
Update environment location to align with OSPI fixed-partition definitions and provide a redundant environment at a 2nd location. Signed-off-by: Wadim Egorov --- configs/phycore_am64x_a53_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 76bb0e53e51..e94d829fd8f 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -13,7 +13,7 @@ CONFIG_TARGET_PHYCORE_AM64X_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048 CONFIG_ENV_SIZE=0x2 -CONFIG_ENV_OFFSET=0xD000 +CONFIG_ENV_OFFSET=0x68 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-phyboard-electra-rdk" @@ -28,6 +28,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a0 CONFIG_SPL_BSS_MAX_SIZE=0x8 CONFIG_SPL_STACK_R=y +CONFIG_ENV_OFFSET_REDUND=0x6c CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -76,6 +77,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y -- 2.34.1
[PATCH 02/13] arch: arm: dts: k3-am642-phyboard-electra: Add fixed partitions
From: Nathan Morrisson
Add a fixed partitions node to the AM64x device tree so that it can
be used to fixup the Linux device tree.
Signed-off-by: Nathan Morrisson
Signed-off-by: Wadim Egorov
---
.../k3-am642-phyboard-electra-rdk-u-boot.dtsi | 26 +++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
index 4677c35e2d9..8f3c3a185ae 100644
--- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
@@ -115,6 +115,32 @@
bootph-all;
flash@0 {
bootph-all;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x8>;
+ };
+ partition@8 {
+ label = "ospi.tispl";
+ reg = <0x08 0x20>;
+ };
+ partition@28 {
+ label = "ospi.u-boot";
+ reg = <0x28 0x40>;
+ };
+ partition@68 {
+ label = "ospi.env";
+ reg = <0x68 0x4>;
+ };
+ partition@6c {
+ label = "ospi.env.backup";
+ reg = <0x6c 0x4>;
+ };
+ };
};
};
--
2.34.1
[PATCH 01/13] arch: arm: dts: k3-am625-phyboard-lyra: Add fixed partitions
From: Nathan Morrisson
Add a fixed partitions node to the AM62x device tree so that it can
be used to fixup the Linux device tree.
Signed-off-by: Nathan Morrisson
Signed-off-by: Wadim Egorov
---
.../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 26 +++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 94162282068..7c76acc0d59 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -127,6 +127,32 @@
flash@0 {
bootph-all;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x8>;
+ };
+ partition@8 {
+ label = "ospi.tispl";
+ reg = <0x08 0x20>;
+ };
+ partition@28 {
+ label = "ospi.u-boot";
+ reg = <0x28 0x40>;
+ };
+ partition@68 {
+ label = "ospi.env";
+ reg = <0x68 0x4>;
+ };
+ partition@6c {
+ label = "ospi.env.backup";
+ reg = <0x6c 0x4>;
+ };
+ };
};
};
--
2.34.1
[PATCH 00/13] *** Various fixes & improvements for phycore-AM6* SoMs ***
This patch set is for u-boot/next. It includes various fixes and improvements for phyCORE-AM62x and phyCORE-AM64x SoMs. Notable is the last patch which prepares for use with future ECC memory fixups. Nathan Morrisson (2): arch: arm: dts: k3-am625-phyboard-lyra: Add fixed partitions arch: arm: dts: k3-am642-phyboard-electra: Add fixed partitions Wadim Egorov (11): board: phytec: common: k3: Copy fixed partitions to OS device tree board: phytec: phycore-am62x: Fix CONFIG_SPL_BOARD_INIT configs: phycore_am62x: Update environment location configs: phycore_am64x: Update environment location arm: dts: k3-am625-phyboard-lyra-rdk: Enable usb port in u-boot configs: phycore_am62x_a53_defconfig: Enable DFU boot board: phytec: phycore-am62x: Pull in k3_dfu.env configs: phycore_am6xx: Update MTD & SPI configs doc: board: phytec: phycore-am62x: Add USB DFU switch config doc: board: phytec: phycore-am6: Use mtd commands board: phytec: phycore-am62x: Use memory nodes in higher boot stages .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 35 + .../k3-am642-phyboard-electra-rdk-u-boot.dtsi | 26 + board/phytec/common/k3/board.c| 10 + board/phytec/phycore_am62x/phycore-am62x.c| 31 ++- board/phytec/phycore_am62x/phycore_am62x.env | 2 + configs/phycore_am62x_a53_defconfig | 38 +-- configs/phycore_am62x_r5_defconfig| 1 - configs/phycore_am64x_a53_defconfig | 8 ++-- configs/phycore_am64x_r5_defconfig| 1 - doc/board/phytec/phycore-am62x.rst| 12 -- doc/board/phytec/phycore-am64x.rst| 8 ++-- 11 files changed, 155 insertions(+), 17 deletions(-) -- 2.34.1
Re: [PATCH v3 7/8] board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled
Hi Santhosh,
thanks for this series!
Am 23.05.24 um 07:04 schrieb Santhosh Kumar K:
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the
device tree and resize the available amount of DDR, if ECC is enabled.
Otherwise, fixup the device tree using the regular
fdt_fixup_memory_banks().
Also call dram_init_banksize() after every call to
fixup_ddr_driver_for_ecc() is made so that gd->bd is populated
correctly.
Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR
controllers present.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
[...]
+++ b/board/ti/common/k3-ddr-init.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+
+#include "k3-ddr-init.h"
+
+int dram_init(void)
+{
+ s32 ret;
+
+ ret = fdtdec_setup_mem_size_base_lowest();
+ if (ret)
+ printf("Error setting up mem size and base. %d\n", ret);
+
+ return ret;
+}
+
+int dram_init_banksize(void)
+{
+ s32 ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ printf("Error setting up memory banksize. %d\n", ret);
+
+ return ret;
+}
I'm wondering if we can generalize more.
What do you say if we keep dram_init() & dram_init_banksize() in the
board code and move fixup_ddr_driver_for_ecc() & fixup_memory_node() to
mach-k3 and make them available for all K3 based boards?
It looks like I will reuse the code for our boards and I assume other
vendors too.
Regards,
Wadim
+
+#if defined(CONFIG_SPL_BUILD)
+
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
+{
+ struct udevice *dev;
+ int ret, ctr = 1;
+
+ dram_init_banksize();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, );
+ if (ret)
+ panic("Cannnot get RAM device for ddr size fixup: %d\n", ret);
+
+ ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
+ if (ret)
+ printf("Error fixing up ddr node for ECC use! %d\n", ret);
+
+ dram_init_banksize();
+
+ ret = uclass_next_device_err();
+
+ while (!ret) {
+ ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
+ if (ret)
+ printf("Error fixing up ddr node %d for ECC use! %d\n",
ctr, ret);
+
+ dram_init_banksize();
+ ret = uclass_next_device_err();
+ ctr++;
+ }
+}
+
+void fixup_memory_node(struct spl_image_info *spl_image)
+{
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int bank;
+ int ret;
+
+ dram_init();
+ dram_init_banksize();
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start[bank] = gd->bd->bi_dram[bank].start;
+ size[bank] = gd->bd->bi_dram[bank].size;
+ }
+
+ ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
+CONFIG_NR_DRAM_BANKS);
+
+ if (ret)
+ printf("Error fixing up memory node! %d\n", ret);
+}
+
+#endif
diff --git a/board/ti/common/k3-ddr-init.h b/board/ti/common/k3-ddr-init.h
new file mode 100644
index ..9d1826815dfd
--- /dev/null
+++ b/board/ti/common/k3-ddr-init.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __K3_DDR_INIT_H
+#define __K3_DDR_INIT_H
+
+int dram_init(void);
+int dram_init_banksize(void);
+
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image);
+void fixup_memory_node(struct spl_image_info *spl_image);
+
+#endif /* __K3_DDR_INIT_H */
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 539eaf47186a..e0cd8529bc2b 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -17,6 +17,7 @@
#include "../common/board_detect.h"
#include "../common/fdt_ops.h"
+#include "../common/k3-ddr-init.h"
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \
board_ti_k3_is("J721EX-PM2-SOM"))
@@ -37,17 +38,6 @@ int board_init(void)
return 0;
}
-int dram_init(void)
-{
-#ifdef CONFIG_PHYS_64BIT
- gd->ram_size = 0x1;
-#else
- gd->ram_size = 0x8000;
-#endif
-
- return 0;
-}
-
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
@@ -59,23 +49,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return gd->ram_top;
}
-int dram_init_banksize(void)
-{
- /* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = 0x8000;
-
Re: [Upstream] [PATCH 5/6] board: phytec: common: k3: Set MAC
Am 22.05.24 um 08:18 schrieb Daniel Schultz:
Read the EEPROM API v3 content and set all available
MAC-Addresses to the environment.
Signed-off-by: Daniel Schultz
---
board/phytec/common/k3/board.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 9cb168c36cb..f21e154d4fe 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -8,6 +8,8 @@
#include
#include
+#include "../am6_som_detection.h"
+
#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
int mmc_get_env_dev(void)
{
@@ -68,6 +70,27 @@ int board_late_init(void)
break;
};
+ if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) {
+ struct phytec_api3_element *block_element;
+ struct phytec_eeprom_data data;
+ int ret;
+
+ ret = phytec_eeprom_data_setup(, 0, EEPROM_ADDR);
+ if (ret || !data.valid)
+ return 0;
Don't you want to return an error or at least print a warning?
Apart from that,
Reviewed-by: Wadim Egorov
+
+ PHYTEC_API3_FOREACH_BLOCK(block_element, ) {
+ switch (block_element->block_type) {
+ case PHYTEC_API3_BLOCK_MAC:
+ phytec_blocks_add_mac_to_env(block_element);
+ break;
+ default:
+ debug("%s: Unknown block type %i\n", __func__,
+ block_element->block_type);
+ }
+ }
+ }
+
return 0;
}
#endif
Re: [Upstream] [PATCH 6/6] configs: phycore_am62x_a53_defconfig: Enable CONFIG_ENV_OVERWRITE
Hi Daniel, Am 22.05.24 um 08:18 schrieb Daniel Schultz: Enable CONFIG_ENV_OVERWRITE to overwrite ethaddr in the environment. This is required because our environment is not located in the boot partition. Signed-off-by: Daniel Schultz --- configs/phycore_am62x_a53_defconfig | 1 + What about the change for the phycore_am64x? 1 file changed, 1 insertion(+) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index fd36edc29dd..286cd89c5a6 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -59,6 +59,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y
Re: [Upstream] [PATCH 0/6] PHYTEC SOM Detection API v3
Am 22.05.24 um 08:18 schrieb Daniel Schultz: This patch series adds support for the EEPROM v3 API. V3 is backwards compatible to V2 and therefore, the V2 image still exists at the beginning. Only the API version changed from 2 to 3. V3 is a block-based memory layout organized as singled-linked list with different types of blocks. This is a more flexible approach and allows us to extend it by more block types in the future. The V3 data starts with a 8-byte large header which defines the block count (u8), V3 subversion (u8) and data payload length (u16). Additionally the header contains a CRC8 checksum a 3 reserved bytes. Each block starts with a 4-byte large header which defined the block type (u8), the absolute address of the next block (u16) and a CRC8 checksum. The content itself is defined via the block type and we currently have 2 different types: 1) MAC: Contains the Ethernet interface number (u8), MAC address (6 x u8) and a CRC8 checksum. For this series, Tested-by: Wadim Egorov
[PATCH v2 2/5] board: phytec: Fix function definitions in AM6x SOM detection
Functions are declared as phytec_am6* and not phytec_am62*.
Update the definitions to match the declarations.
Fixes: 9d152c23279c ("board: phytec: Add SOM detection for AM6x")
Signed-off-by: Wadim Egorov
Tested-by: John Ma
---
board/phytec/common/am6_som_detection.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/board/phytec/common/am6_som_detection.c
b/board/phytec/common/am6_som_detection.c
index 2e9884dab44..7930ab42d1c 100644
--- a/board/phytec/common/am6_som_detection.c
+++ b/board/phytec/common/am6_som_detection.c
@@ -73,7 +73,7 @@ static u8 phytec_check_opt(struct phytec_eeprom_data *data,
u8 option)
* - The size
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data)
{
u8 ddr_id = phytec_check_opt(data, 3);
@@ -89,7 +89,7 @@ u8 __maybe_unused phytec_get_am62_ddr_size(struct
phytec_eeprom_data *data)
* - Otherwise a board depended code for the size.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data)
{
u8 spi = phytec_check_opt(data, 5);
@@ -105,7 +105,7 @@ u8 __maybe_unused phytec_get_am62_spi(struct
phytec_eeprom_data *data)
* - 0x1 if 10/100/1000 MBit Phy is populated.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data)
{
u8 eth = phytec_check_opt(data, 6);
@@ -121,7 +121,7 @@ u8 __maybe_unused phytec_get_am62_eth(struct
phytec_eeprom_data *data)
* - 1 if it is populated.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data)
{
u8 rtc = phytec_check_opt(data, 7);
@@ -131,28 +131,28 @@ u8 __maybe_unused phytec_get_am62_rtc(struct
phytec_eeprom_data *data)
#else
-inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data)
+inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data)
{
return -1;
}
inline u8 __maybe_unused
-phytec_get_am62_ddr_size(struct phytec_eeprom_data *data)
+phytec_get_am6_ddr_size(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
--
2.34.1
[PATCH v2 5/5] board: phytec: am62x: Add support for 1 & 4 GB RAM variants
Use content of EEPROM to detect the actual RAM size and adjust
DDR timings, size and banks accordingly.
Also enable the SoM detection per default in the defconfigs.
Signed-off-by: Wadim Egorov
Tested-by: John Ma
---
v2:
- Add Kconfig option to select RAM size statically
---
board/phytec/common/am6_som_detection.h | 8 +
board/phytec/phycore_am62x/Kconfig| 30 +++
board/phytec/phycore_am62x/phycore-am62x.c| 152 -
board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++
configs/phycore_am62x_a53_defconfig | 4 +
configs/phycore_am62x_r5_defconfig| 4 +
6 files changed, 402 insertions(+), 2 deletions(-)
create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h
diff --git a/board/phytec/common/am6_som_detection.h
b/board/phytec/common/am6_som_detection.h
index 032f9da3aab..c5c6e179da6 100644
--- a/board/phytec/common/am6_som_detection.h
+++ b/board/phytec/common/am6_som_detection.h
@@ -9,11 +9,19 @@
#include "phytec_som_detection.h"
+#define EEPROM_ADDR0x50
#define PHYTEC_AM62X_SOM 71
#define PHYTEC_AM64X_SOM 72
#define PHYTEC_EEPROM_VALUE_X 0x21
#define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC
+enum {
+ EEPROM_RAM_SIZE_512MB = 0,
+ EEPROM_RAM_SIZE_1GB = 1,
+ EEPROM_RAM_SIZE_2GB = 2,
+ EEPROM_RAM_SIZE_4GB = 4
+};
+
int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data);
diff --git a/board/phytec/phycore_am62x/Kconfig
b/board/phytec/phycore_am62x/Kconfig
index 1de8850c6c4..7c179ef0078 100644
--- a/board/phytec/phycore_am62x/Kconfig
+++ b/board/phytec/phycore_am62x/Kconfig
@@ -35,3 +35,33 @@ config SPL_LDSCRIPT
source "board/phytec/common/Kconfig"
endif
+
+config PHYCORE_AM62X_RAM_SIZE_FIX
+bool "Set phyCORE-AM62x RAM size fix instead of detecting"
+default false
+help
+ RAM size is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM size to a fix value
+ instead.
+
+choice
+prompt "phyCORE-AM62x RAM size"
+depends on PHYCORE_AM62X_RAM_SIZE_FIX
+default PHYCORE_AM62X_RAM_SIZE_2GB
+
+config PHYCORE_AM62X_RAM_SIZE_1GB
+bool "1GB RAM"
+help
+ Set RAM size fix to 1GB for phyCORE-AM62x.
+
+config PHYCORE_AM62X_RAM_SIZE_2GB
+bool "2GB RAM"
+help
+ Set RAM size fix to 2GB for phyCORE-AM62x.
+
+config PHYCORE_AM62X_RAM_SIZE_4GB
+bool "4GB RAM"
+help
+ Set RAM size fix to 4GB for phyCORE-AM62x.
+
+endchoice
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c
b/board/phytec/phycore_am62x/phycore-am62x.c
index a082b886bda..4a76f1343d7 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -8,6 +8,13 @@
#include
#include
+#include "phycore-ddr-data.h"
+#include "../common/k3/k3_ddrss_patch.h"
+#include "../common/am6_som_detection.h"
+
+#define AM64_DDRSS_SS_BASE 0x0F30
+#define DDRSS_V2A_CTL_REG 0x0020
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -15,16 +22,157 @@ int board_init(void)
return 0;
}
+static u8 phytec_get_am62_ddr_size_default(void)
+{
+ int ret;
+ struct phytec_eeprom_data data;
+
+ if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB))
+ return EEPROM_RAM_SIZE_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB))
+ return EEPROM_RAM_SIZE_2GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB))
+ return EEPROM_RAM_SIZE_4GB;
+ }
+
+ ret = phytec_eeprom_data_setup(, 0, EEPROM_ADDR);
+ if (!ret && data.valid)
+ return phytec_get_am6_ddr_size();
+
+ /* Default DDR size is 2GB */
+ return EEPROM_RAM_SIZE_2GB;
+}
+
int dram_init(void)
{
- return fdtdec_setup_mem_size_base();
+ u8 ram_size = phytec_get_am62_ddr_size_default();
+
+ /*
+* HACK: ddrss driver support 2GB RAM by default
+* V2A_CTL_REG should be updated to support other RAM size
+*/
+ if (IS_ENABLED(CONFIG_K3_AM64_DDRSS))
+ if (ram_size == EEPROM_RAM_SIZE_4GB)
+ writel(0x0210, AM64_DDRSS_SS_BASE +
DDRSS_V2A_CTL_REG);
+
+ switch (ram_size) {
+ case EEPROM_RAM_SIZE_1GB:
+ gd->ram_size = 0x4000;
+ break;
+ case EEPROM_RAM_SIZE_2GB:
+ gd->ram_size = 0x8000;
+ break;
+ case EE
[PATCH v2 4/5] board: phytec: common: Introduce a method to inject DDR timings deltas
Introduce fdt_apply_ddrss_timings_patch() to allow board code to
override DDR settings in the device tree prior to DDRSS driver probing.
Signed-off-by: Wadim Egorov
Tested-by: John Ma
---
v2:
- Make board/phytec/common/k3 always compile for CONFIG_ARCH_K3
---
board/phytec/common/Makefile| 4 +-
board/phytec/common/k3/Makefile | 1 +
board/phytec/common/k3/k3_ddrss_patch.c | 68 +
board/phytec/common/k3/k3_ddrss_patch.h | 28 ++
board/phytec/phycore_am62x/MAINTAINERS | 1 +
5 files changed, 99 insertions(+), 3 deletions(-)
create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c
create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index c34fc503059..988c5742db5 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -5,10 +5,8 @@
ifdef CONFIG_SPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
-else
-obj-$(CONFIG_ARCH_K3) += k3/
endif
obj-y += phytec_som_detection.o
-obj-$(CONFIG_ARCH_K3) += am6_som_detection.o
+obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile
index bcca1a9f846..40e91a43e99 100644
--- a/board/phytec/common/k3/Makefile
+++ b/board/phytec/common/k3/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += board.o
+obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o
diff --git a/board/phytec/common/k3/k3_ddrss_patch.c
b/board/phytec/common/k3/k3_ddrss_patch.c
new file mode 100644
index 000..39f7be8dc92
--- /dev/null
+++ b/board/phytec/common/k3/k3_ddrss_patch.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov
+ */
+
+#include "k3_ddrss_patch.h"
+
+#include
+#include
+
+#ifdef CONFIG_K3_AM64_DDRSS
+#define LPDDR4_INTR_CTL_REG_COUNT (423U)
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+#endif
+
+static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
+ const char *name, uint32_t idx, u32 val)
+{
+ val = cpu_to_be32(val);
+ return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
+ strlen(name),
+ idx * sizeof(val), ,
+ sizeof(val));
+}
+
+int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss)
+{
+ int i, j;
+ int ret;
+ int mem_offset;
+
+ mem_offset = fdt_path_offset(fdt, "/memorycontroller@f30");
+ if (mem_offset < 0)
+ return -ENODEV;
+
+ for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
+ for (j = 0; j < ddrss->ctl_regs_num; j++)
+ if (i == ddrss->ctl_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,ctl-data", i,
+ ddrss->ctl_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+ for (j = 0; j < ddrss->pi_regs_num; j++)
+ if (i == ddrss->pi_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,pi-data", i,
+ ddrss->pi_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+ for (j = 0; j < ddrss->phy_regs_num; j++)
+ if (i == ddrss->phy_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,phy-data", i,
+ ddrss->phy_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/board/phytec/common/k3/k3_ddrss_patch.h
b/board/phytec/common/k3/k3_ddrss_patch.h
new file mode 100644
index 000..0a47c85116a
--- /dev/null
+++ b/board/phytec/common/k3/k3_ddrss_patch.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov
+ */
+
+#ifndef K3_DDRSS_PATCH
+#define K3_DDRSS_PATCH
+
+#include
+
+struct ddr_reg {
+ u32 off;
+ u32 val;
+};
+
+struct ddrss {
+ struct ddr_reg *ctl_regs;
[PATCH v2 3/5] arm: mach-k3: am625: Call do_board_detect() before DDR probing
Call do_board_detect() hook before the K3 DDRSS driver gets probed. It will allow boards to adjust DDR timings in do_board_detect(). Signed-off-by: Wadim Egorov Tested-by: John Ma --- arch/arm/mach-k3/am62x/am625_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index ed8d24e0433..72a752d38e8 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -213,6 +213,8 @@ void board_init_f(ulong dummy) preloader_console_init(); + do_board_detect(); + /* * Allow establishing an early console as required for example when * doing a UART-based boot. Note that this console may not "survive" -- 2.34.1
[PATCH v2 0/5] *** phyCORE-AM62x: DDR detection / Inject DDR timing deltas ***
Changes in v2: - Reabse to current next - Add Tested-by: John Ma - Add Kconfig option to select RAM size statically - Make board/phytec/common/k3 always compile for CONFIG_ARCH_K3 v1: https://lists.denx.de/pipermail/u-boot/2024-May/553057.html Wadim Egorov (5): board: phytec: Make AM6 SoM detection depend on I2C board: phytec: Fix function definitions in AM6x SOM detection arm: mach-k3: am625: Call do_board_detect() before DDR probing board: phytec: common: Introduce a method to inject DDR timings deltas board: phytec: am62x: Add support for 1 & 4 GB RAM variants arch/arm/mach-k3/am62x/am625_init.c | 2 + board/phytec/common/Kconfig | 2 + board/phytec/common/Makefile | 4 +- board/phytec/common/am6_som_detection.c | 18 +- board/phytec/common/am6_som_detection.h | 8 + board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 ++ board/phytec/common/k3/k3_ddrss_patch.h | 28 +++ board/phytec/phycore_am62x/Kconfig| 30 +++ board/phytec/phycore_am62x/MAINTAINERS| 1 + board/phytec/phycore_am62x/phycore-am62x.c| 152 - board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig| 4 + 14 files changed, 514 insertions(+), 14 deletions(-) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h -- 2.34.1
[PATCH v2 1/5] board: phytec: Make AM6 SoM detection depend on I2C
SoM detection is using I2C driver model functions. Let's depend on I2C. Signed-off-by: Wadim Egorov Tested-by: John Ma --- board/phytec/common/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..56c8290f641 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -16,6 +16,7 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +26,7 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported -- 2.34.1
[PATCH 5/5] board: phytec: am62x: Add support for 1 & 4 GB RAM variants
Use content of EEPROM to detect the actual RAM size and adjust
DDR timings, size and banks accordingly.
Also enable the SoM detection per default in the defconfigs.
Signed-off-by: Wadim Egorov
---
board/phytec/common/am6_som_detection.h | 8 +
board/phytec/phycore_am62x/phycore-am62x.c| 152 -
board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++
configs/phycore_am62x_a53_defconfig | 4 +
configs/phycore_am62x_r5_defconfig| 4 +
5 files changed, 372 insertions(+), 2 deletions(-)
create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h
diff --git a/board/phytec/common/am6_som_detection.h
b/board/phytec/common/am6_som_detection.h
index 032f9da3aab..c5c6e179da6 100644
--- a/board/phytec/common/am6_som_detection.h
+++ b/board/phytec/common/am6_som_detection.h
@@ -9,11 +9,19 @@
#include "phytec_som_detection.h"
+#define EEPROM_ADDR0x50
#define PHYTEC_AM62X_SOM 71
#define PHYTEC_AM64X_SOM 72
#define PHYTEC_EEPROM_VALUE_X 0x21
#define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC
+enum {
+ EEPROM_RAM_SIZE_512MB = 0,
+ EEPROM_RAM_SIZE_1GB = 1,
+ EEPROM_RAM_SIZE_2GB = 2,
+ EEPROM_RAM_SIZE_4GB = 4
+};
+
int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data);
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c
b/board/phytec/phycore_am62x/phycore-am62x.c
index a082b886bda..4a76f1343d7 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -8,6 +8,13 @@
#include
#include
+#include "phycore-ddr-data.h"
+#include "../common/k3/k3_ddrss_patch.h"
+#include "../common/am6_som_detection.h"
+
+#define AM64_DDRSS_SS_BASE 0x0F30
+#define DDRSS_V2A_CTL_REG 0x0020
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -15,16 +22,157 @@ int board_init(void)
return 0;
}
+static u8 phytec_get_am62_ddr_size_default(void)
+{
+ int ret;
+ struct phytec_eeprom_data data;
+
+ if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB))
+ return EEPROM_RAM_SIZE_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB))
+ return EEPROM_RAM_SIZE_2GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB))
+ return EEPROM_RAM_SIZE_4GB;
+ }
+
+ ret = phytec_eeprom_data_setup(, 0, EEPROM_ADDR);
+ if (!ret && data.valid)
+ return phytec_get_am6_ddr_size();
+
+ /* Default DDR size is 2GB */
+ return EEPROM_RAM_SIZE_2GB;
+}
+
int dram_init(void)
{
- return fdtdec_setup_mem_size_base();
+ u8 ram_size = phytec_get_am62_ddr_size_default();
+
+ /*
+* HACK: ddrss driver support 2GB RAM by default
+* V2A_CTL_REG should be updated to support other RAM size
+*/
+ if (IS_ENABLED(CONFIG_K3_AM64_DDRSS))
+ if (ram_size == EEPROM_RAM_SIZE_4GB)
+ writel(0x0210, AM64_DDRSS_SS_BASE +
DDRSS_V2A_CTL_REG);
+
+ switch (ram_size) {
+ case EEPROM_RAM_SIZE_1GB:
+ gd->ram_size = 0x4000;
+ break;
+ case EEPROM_RAM_SIZE_2GB:
+ gd->ram_size = 0x8000;
+ break;
+ case EEPROM_RAM_SIZE_4GB:
+#ifdef CONFIG_PHYS_64BIT
+ gd->ram_size = 0x1;
+#else
+ gd->ram_size = 0x8000;
+#endif
+ break;
+ default:
+ gd->ram_size = 0x8000;
+ }
+
+ return 0;
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x1)
+ return 0x1;
+#endif
+ return gd->ram_top;
}
int dram_init_banksize(void)
{
- return fdtdec_setup_memory_banksize();
+ u8 ram_size;
+
+ ram_size = phytec_get_am62_ddr_size_default();
+ switch (ram_size) {
+ case EEPROM_RAM_SIZE_1GB:
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x4000;
+ gd->ram_size = 0x4000;
+ break;
+
+ case EEPROM_RAM_SIZE_2GB:
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x8000;
+ gd->ram_size = 0x8000;
+ break;
+
+ case EEPROM_RAM_SIZE_4GB:
+ /* Bank 0 declares the memory available in the DDR low region */
+
[PATCH 4/5] board: phytec: common: Introduce a method to inject DDR timings deltas
Introduce fdt_apply_ddrss_timings_patch() to allow board code to
override DDR settings in the device tree prior to DDRSS driver probing.
Signed-off-by: Wadim Egorov
---
board/phytec/common/k3/Makefile | 1 +
board/phytec/common/k3/k3_ddrss_patch.c | 68 +
board/phytec/common/k3/k3_ddrss_patch.h | 28 ++
board/phytec/phycore_am62x/MAINTAINERS | 1 +
4 files changed, 98 insertions(+)
create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c
create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile
index bcca1a9f846..40e91a43e99 100644
--- a/board/phytec/common/k3/Makefile
+++ b/board/phytec/common/k3/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += board.o
+obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o
diff --git a/board/phytec/common/k3/k3_ddrss_patch.c
b/board/phytec/common/k3/k3_ddrss_patch.c
new file mode 100644
index 000..39f7be8dc92
--- /dev/null
+++ b/board/phytec/common/k3/k3_ddrss_patch.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov
+ */
+
+#include "k3_ddrss_patch.h"
+
+#include
+#include
+
+#ifdef CONFIG_K3_AM64_DDRSS
+#define LPDDR4_INTR_CTL_REG_COUNT (423U)
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+#endif
+
+static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
+ const char *name, uint32_t idx, u32 val)
+{
+ val = cpu_to_be32(val);
+ return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
+ strlen(name),
+ idx * sizeof(val), ,
+ sizeof(val));
+}
+
+int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss)
+{
+ int i, j;
+ int ret;
+ int mem_offset;
+
+ mem_offset = fdt_path_offset(fdt, "/memorycontroller@f30");
+ if (mem_offset < 0)
+ return -ENODEV;
+
+ for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
+ for (j = 0; j < ddrss->ctl_regs_num; j++)
+ if (i == ddrss->ctl_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,ctl-data", i,
+ ddrss->ctl_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+ for (j = 0; j < ddrss->pi_regs_num; j++)
+ if (i == ddrss->pi_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,pi-data", i,
+ ddrss->pi_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+ for (j = 0; j < ddrss->phy_regs_num; j++)
+ if (i == ddrss->phy_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,phy-data", i,
+ ddrss->phy_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/board/phytec/common/k3/k3_ddrss_patch.h
b/board/phytec/common/k3/k3_ddrss_patch.h
new file mode 100644
index 000..0a47c85116a
--- /dev/null
+++ b/board/phytec/common/k3/k3_ddrss_patch.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov
+ */
+
+#ifndef K3_DDRSS_PATCH
+#define K3_DDRSS_PATCH
+
+#include
+
+struct ddr_reg {
+ u32 off;
+ u32 val;
+};
+
+struct ddrss {
+ struct ddr_reg *ctl_regs;
+ u32 ctl_regs_num;
+ struct ddr_reg *pi_regs;
+ u32 pi_regs_num;
+ struct ddr_reg *phy_regs;
+ u32 phy_regs_num;
+};
+
+int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss);
+
+#endif /* K3_DDRSS_PATCH */
diff --git a/board/phytec/phycore_am62x/MAINTAINERS
b/board/phytec/phycore_am62x/MAINTAINERS
index 02ac88e58a4..42463ad054e 100644
--- a/board/phytec/phycore_am62x/MAINTAINERS
+++ b/board/phytec/phycore_am62x/MAINTAINERS
@@ -11,3 +11,4 @@ F:configs/phycore_am62x_a53_defconfig
F: configs/phycore_am62x_r5_defconfig
F: include/configs/phycore_am62x.h
F: doc/board/phytec/phycore-am62x.rst
+F: board/phytec/common/k3
--
2.34.1
[PATCH 3/5] arm: mach-k3: am625: Call do_board_detect() before DDR probing
Call do_board_detect() hook before the K3 DDRSS driver gets probed. It will allow boards to adjust DDR timings in do_board_detect(). Signed-off-by: Wadim Egorov --- arch/arm/mach-k3/am625_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 668f9a51ef4..672de1c03de 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -212,6 +212,8 @@ void board_init_f(ulong dummy) preloader_console_init(); + do_board_detect(); + /* * Allow establishing an early console as required for example when * doing a UART-based boot. Note that this console may not "survive" -- 2.34.1
[PATCH 1/5] board: phytec: Make AM6 SoM detection depend on I2C
SoM detection is using I2C driver model functions. Let's depend on I2C. Signed-off-by: Wadim Egorov --- board/phytec/common/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..56c8290f641 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -16,6 +16,7 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +26,7 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported -- 2.34.1
[PATCH 2/5] board: phytec: Fix function definitions in AM6x SOM detection
Functions are declared as phytec_am6* and not phytec_am62*.
Update the definitions to match the declarations.
Fixes: 9d152c23279c ("board: phytec: Add SOM detection for AM6x")
Signed-off-by: Wadim Egorov
---
board/phytec/common/am6_som_detection.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/board/phytec/common/am6_som_detection.c
b/board/phytec/common/am6_som_detection.c
index 2e9884dab44..7930ab42d1c 100644
--- a/board/phytec/common/am6_som_detection.c
+++ b/board/phytec/common/am6_som_detection.c
@@ -73,7 +73,7 @@ static u8 phytec_check_opt(struct phytec_eeprom_data *data,
u8 option)
* - The size
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data)
{
u8 ddr_id = phytec_check_opt(data, 3);
@@ -89,7 +89,7 @@ u8 __maybe_unused phytec_get_am62_ddr_size(struct
phytec_eeprom_data *data)
* - Otherwise a board depended code for the size.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data)
{
u8 spi = phytec_check_opt(data, 5);
@@ -105,7 +105,7 @@ u8 __maybe_unused phytec_get_am62_spi(struct
phytec_eeprom_data *data)
* - 0x1 if 10/100/1000 MBit Phy is populated.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data)
{
u8 eth = phytec_check_opt(data, 6);
@@ -121,7 +121,7 @@ u8 __maybe_unused phytec_get_am62_eth(struct
phytec_eeprom_data *data)
* - 1 if it is populated.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data)
{
u8 rtc = phytec_check_opt(data, 7);
@@ -131,28 +131,28 @@ u8 __maybe_unused phytec_get_am62_rtc(struct
phytec_eeprom_data *data)
#else
-inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data)
+inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data)
{
return -1;
}
inline u8 __maybe_unused
-phytec_get_am62_ddr_size(struct phytec_eeprom_data *data)
+phytec_get_am6_ddr_size(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
--
2.34.1
[PATCH 0/5] *** phyCORE-AM62x: DDR detection / Inject DDR timing deltas ***
PHYTEC stores details about the hardware in an EEPROM on the SoM. We can utilize this information and chose the proper DDR timings accordingly. Due to the limited SRAM memory on the AM62x, the concept was to store only the DDR timings deltas and not their full set, see Patch 4 & 5. The last patch adds support for a 1 GB and 4 GB RAM variant of the phyCORE-AM62x. Patch 4 & 5 are based on https://patchwork.ozlabs.org/project/uboot/list/?series=404273 Wadim Egorov (5): board: phytec: Make AM6 SoM detection depend on I2C board: phytec: Fix function definitions in AM6x SOM detection arm: mach-k3: am625: Call do_board_detect() before DDR probing board: phytec: common: Introduce a method to inject DDR timings deltas board: phytec: am62x: Add support for 1 & 4 GB RAM variants arch/arm/mach-k3/am625_init.c | 2 + board/phytec/common/Kconfig | 2 + board/phytec/common/am6_som_detection.c | 18 +- board/phytec/common/am6_som_detection.h | 8 + board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 ++ board/phytec/common/k3/k3_ddrss_patch.h | 28 +++ board/phytec/phycore_am62x/MAINTAINERS| 1 + board/phytec/phycore_am62x/phycore-am62x.c| 152 - board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig| 4 + 12 files changed, 483 insertions(+), 11 deletions(-) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h -- 2.34.1
Re: [PATCH 103/149] board: phytec: Remove and add needed includes
Am 01.05.24 um 04:42 schrieb Tom Rini: Remove from this board vendor directory and when needed add missing include files directly. Signed-off-by: Tom Rini Acked-by: Wadim Egorov --- Cc: Martyn Welch Cc: Parthiban Nallathambi Cc: "Albert ARIBAUD (3ADEV)" Cc: Niel Fourie Cc: Teresa Remmet Cc: Wadim Egorov Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Yannic Moog Cc: Daniel Schultz Cc: Benjamin Hahn Cc: Fabio Estevam --- board/phytec/common/imx8m_som_detection.c| 1 - board/phytec/common/phytec_som_detection.c | 1 - board/phytec/pcl063/spl.c| 2 +- board/phytec/pcm052/pcm052.c | 1 - board/phytec/pcm058/pcm058.c | 1 - board/phytec/phycore_am335x_r2/board.c | 2 +- board/phytec/phycore_am335x_r2/mux.c | 1 - board/phytec/phycore_imx8mm/phycore-imx8mm.c | 1 - board/phytec/phycore_imx8mm/spl.c| 1 - board/phytec/phycore_imx8mp/phycore-imx8mp.c | 1 - board/phytec/phycore_imx8mp/spl.c| 1 - board/phytec/phycore_rk3288/phycore-rk3288.c | 1 - 12 files changed, 2 insertions(+), 12 deletions(-) diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c index ee34a5b95791..bfd60ffb7773 100644 --- a/board/phytec/common/imx8m_som_detection.c +++ b/board/phytec/common/imx8m_som_detection.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 78c173df20d4..b14bb3dbb7fa 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b6d459fdfce6..b98c46dbcbd4 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -6,7 +6,7 @@ * Copyright (C) 2015-2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 0f7235979b04..20f2aac332da 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -6,7 +6,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index b37c6fe218da..ecc5b75d8d42 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -9,7 +9,6 @@ * Both NAND and eMMC cannot be set because they share the * same pins (SD4) */ -#include #include #include #include diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index 5700effbd3f6..2022525651dc 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -10,7 +10,7 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ -#include +#include #include #include #include diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c index 7091c985ba12..bb1c48da0fe5 100644 --- a/board/phytec/phycore_am335x_r2/mux.c +++ b/board/phytec/phycore_am335x_r2/mux.c @@ -6,7 +6,6 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index ef6472916903..06cffbca3a69 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index 690a51f7a72e..8d858590a39b 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index dbdd6bb79373..35683591433c 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index df158024654e..352f803e4541 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index 1ddb4a4f8085..a970634b4c33 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/bo
Re: [PATCH] configs: Make USB_GADGET_MANUFACTURER consistent over all PHYTEC boards
Am 03.05.24 um 09:00 schrieb Benjamin Hahn: Set CONFIG_USB_GADGET_MANUFACTURER to PHYTEC for all PHYTEC boards. Signed-off-by: Benjamin Hahn Acked-by: Wadim Egorov --- configs/phycore-imx8mp_defconfig | 2 +- configs/phycore_am64x_a53_defconfig | 2 +- configs/phycore_am64x_r5_defconfig | 2 +- configs/phycore_pcl063_defconfig | 2 +- configs/phycore_pcl063_ull_defconfig | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index e9a287cb441f..9f42edd72324 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -147,7 +147,7 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 1a9359773b45..9b52f8ad0644 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -159,7 +159,7 @@ CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 61d784fa17f6..15a7e7089e73 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -171,7 +171,7 @@ CONFIG_USB_STORAGE=y CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_SPL_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 017054a8e12b..2f6b158a6772 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -62,7 +62,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff CONFIG_CI_UDC=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index b3da43a5bf1e..b42a410da69c 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -53,7 +53,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff CONFIG_CI_UDC=y --- base-commit: 6fdb021f148f598a67eb3cac5e3eb4a569cdaacd change-id: 20240503-wip-bhahn-bspimx8m-3196-c1ebd0bab6ac Best regards,
Usage of fdt_addr vs fdt_addr_r
Hi, there are multiple definitions of fdt_addr and fdt_addr_r: usage/environment.rst: Tells us fdt_addr is in flash location and _r in RAM develop/distro.rst: fdt_addr -> Mandatory for any system that provides the DTB in HW (e.g. ROM) I also noticed that bootmeth_efi.c/distro_efi_try_bootflow_files() will copy the dtb it has found into fdt_addr_r. But efi_install_fdt() try to load first from fdt_addr. Shouldn't they use the same environment variable? Doing so would allow efiboot to use the dtb it has detected using bootflow. Right now it seems to fallback to fdtcontroladdr. Regards, Wadim
[PATCH 2/2] phycore_am64x_a53_defconfig: Enable CONFIG_BOARD_LATE_INIT
Enable CONFIG_BOARD_LATE_INIT to use PHYTECs common board_late_init() to set handy environment variables for u-boot. Also, resync after savedefconfig. Signed-off-by: Wadim Egorov --- configs/phycore_am64x_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index bd1e05bee58..8990d08d30a 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x18 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -- 2.34.1
[PATCH 0/2] *** Commonize board code for K3 based SoMs ***
Factor out code that we can reuse across all our K3 based SoMs. 2nd patch of this series require patch [1] to be applied first. [1] https://lists.denx.de/pipermail/u-boot/2024-April/552021.html Wadim Egorov (2): board: phytec: Commonize board code for K3 based SoMs phycore_am64x_a53_defconfig: Enable CONFIG_BOARD_LATE_INIT board/phytec/common/Makefile | 2 + board/phytec/common/k3/Makefile| 2 + board/phytec/common/k3/board.c | 73 ++ board/phytec/phycore_am62x/phycore-am62x.c | 67 configs/phycore_am64x_a53_defconfig| 1 + 5 files changed, 78 insertions(+), 67 deletions(-) create mode 100644 board/phytec/common/k3/Makefile create mode 100644 board/phytec/common/k3/board.c -- 2.34.1
[PATCH 1/2] board: phytec: Commonize board code for K3 based SoMs
Environment handling code can be reused across all our K3 based SoMs.
Instead of adding the same code for every new SoM, move it to a common
board.c file.
Signed-off-by: Wadim Egorov
---
board/phytec/common/Makefile | 2 +
board/phytec/common/k3/Makefile| 2 +
board/phytec/common/k3/board.c | 73 ++
board/phytec/phycore_am62x/phycore-am62x.c | 67
4 files changed, 77 insertions(+), 67 deletions(-)
create mode 100644 board/phytec/common/k3/Makefile
create mode 100644 board/phytec/common/k3/board.c
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index 35c81741306..0c738041565 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -5,6 +5,8 @@
ifdef CONFIG_SPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
+else
+obj-$(CONFIG_ARCH_K3) += k3/
endif
obj-y += phytec_som_detection.o
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile
new file mode 100644
index 000..bcca1a9f846
--- /dev/null
+++ b/board/phytec/common/k3/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0+
+obj-y += board.o
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
new file mode 100644
index 000..9cb168c36cb
--- /dev/null
+++ b/board/phytec/common/k3/board.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov
+ */
+
+#include
+#include
+#include
+
+#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
+int mmc_get_env_dev(void)
+{
+ u32 boot_device = get_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return 0;
+ case BOOT_DEVICE_MMC2:
+ return 1;
+ };
+
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 boot_device = get_boot_device();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ case BOOT_DEVICE_SPI:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ default:
+ return ENVL_NOWHERE;
+ };
+}
+
+#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
+int board_late_init(void)
+{
+ u32 boot_device = get_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ env_set_ulong("mmcdev", 0);
+ env_set("boot", "mmc");
+ break;
+ case BOOT_DEVICE_MMC2:
+ env_set_ulong("mmcdev", 1);
+ env_set("boot", "mmc");
+ break;
+ case BOOT_DEVICE_SPI:
+ env_set("boot", "spi");
+ break;
+ case BOOT_DEVICE_ETHERNET:
+ env_set("boot", "net");
+ break;
+ };
+
+ return 0;
+}
+#endif
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c
b/board/phytec/phycore_am62x/phycore-am62x.c
index 618b4c370d1..a082b886bda 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -5,11 +5,8 @@
*/
#include
-#include
-#include
#include
#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -57,67 +54,3 @@ void spl_board_init(void)
MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
}
#endif
-
-#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
-int mmc_get_env_dev(void)
-{
- u32 boot_device = get_boot_device();
-
- switch (boot_device) {
- case BOOT_DEVICE_MMC1:
- return 0;
- case BOOT_DEVICE_MMC2:
- return 1;
- };
-
- return CONFIG_SYS_MMC_ENV_DEV;
-}
-#endif
-
-enum env_location env_get_location(enum env_operation op, int prio)
-{
- u32 boot_device = get_boot_device();
-
- if (prio)
- return ENVL_UNKNOWN;
-
- switch (boot_device) {
- case BOOT_DEVICE_MMC1:
- case BOOT_DEVICE_MMC2:
- if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
- return ENVL_FAT;
- if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
- return ENVL_MMC;
- case BOOT_DEVICE_SPI:
- if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
- return ENVL_SPI_FLASH;
- default:
- return ENVL_NOWHERE;
- };
-}
-
-#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
-int board_late_init(void)
-{
- u32 boot_device = get_boot_device();
-
- switch (boot_device) {
- cas
[PATCH] arm: mach-k3: am642: Provide a way to obtain boot device for non SPLs
Let's provide get_boot_device() for AM64, similar to what we did
in commit 2f9095e2bf59 ("arm: mach-k3: am625: Provide a way to obtain boot
device for non SPLs") for AM62.
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am642_init.c | 92 +---
arch/arm/mach-k3/am64x/Makefile | 2 +
arch/arm/mach-k3/am64x/boot.c | 105
4 files changed, 109 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-k3/am64x/Makefile
create mode 100644 arch/arm/mach-k3/am64x/boot.c
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 1bd523329a4..3101f57d324 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o
endif
obj-y += common.o security.o
obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM642) += am64x/
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index ddf47ef0a9b..feadad8c5a8 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -285,97 +285,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32
boot_device)
}
}
-static u32 __get_backup_bootmedia(u32 main_devstat)
-{
- u32 bkup_bootmode =
- (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
- u32 bkup_bootmode_cfg =
- (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
-
- switch (bkup_bootmode) {
- case BACKUP_BOOT_DEVICE_UART:
- return BOOT_DEVICE_UART;
-
- case BACKUP_BOOT_DEVICE_DFU:
- if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
-
-
- case BACKUP_BOOT_DEVICE_ETHERNET:
- return BOOT_DEVICE_ETHERNET;
-
- case BACKUP_BOOT_DEVICE_MMC:
- if (bkup_bootmode_cfg)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BACKUP_BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BACKUP_BOOT_DEVICE_I2C:
- return BOOT_DEVICE_I2C;
- };
-
- return BOOT_DEVICE_RAM;
-}
-
-static u32 __get_primary_bootmedia(u32 main_devstat)
-{
- u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
- u32 bootmode_cfg =
- (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
-
- switch (bootmode) {
- case BOOT_DEVICE_OSPI:
- fallthrough;
- case BOOT_DEVICE_QSPI:
- fallthrough;
- case BOOT_DEVICE_XSPI:
- fallthrough;
- case BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BOOT_DEVICE_ETHERNET_RGMII:
- fallthrough;
- case BOOT_DEVICE_ETHERNET_RMII:
- return BOOT_DEVICE_ETHERNET;
-
- case BOOT_DEVICE_EMMC:
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_NAND:
- return BOOT_DEVICE_NAND;
-
- case BOOT_DEVICE_MMC:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
-MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_DFU:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
-
- case BOOT_DEVICE_NOBOOT:
- return BOOT_DEVICE_RAM;
- }
-
- return bootmode;
-}
-
u32 spl_boot_device(void)
{
- u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
-
- if (bootindex == K3_PRIMARY_BOOTMODE)
- return __get_primary_bootmedia(devstat);
- else
- return __get_backup_bootmedia(devstat);
+ return get_boot_device();
}
diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile
new file mode 100644
index 000..acf09c3426c
--- /dev/null
+++ b/arch/arm/mach-k3/am64x/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0+
+obj-y += boot.o
diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c
new file mode 100644
index 000..ce8ae941be6
--- /dev/null
+++ b/arch/arm/mach-k3/am64x/boot.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include
+#include
+#include
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+ u32 bkup_bootmode =
+ (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+ MAIN_DEVS
Re: [PATCH] arm: mach-k3: am642: Fix reset for workaround errata ID i2331
Am 18.04.24 um 19:58 schrieb Andrew Davis:
To workaround an issue in AM642 we reset the SoC in early boot. For that
we first probed the sysreset driver by calling uclass_get_device(). The
ti-sci sysreset driver is now probed during the ti-sci firmware probe.
Update this call to probe the firmware driver which will then probe
the sysreset driver allowing do_reset() to again function as expected.
Reported-by: Jonathan Humphreys
Fixes: fc5d40283483 ("firmware: ti_sci: Bind sysreset driver when enabled")
Signed-off-by: Andrew Davis
Tested-by: Wadim Egorov
on phycore-am64x
---
arch/arm/mach-k3/am642_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index ddf47ef0a9b..80c3cb3479f 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -226,7 +226,7 @@ void board_init_f(ulong dummy)
* The warm reset realigns internal clocks and prevents the lockup from
* happening.
*/
- ret = uclass_first_device_err(UCLASS_SYSRESET, );
+ ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, DM_DRIVER_GET(ti_sci),
);
if (ret)
printf("\n%s:uclass device error [%d]\n",__func__,ret);
[PATCH 2/3] phycore-am64x: Migrate to OF_UPSTREAM
The phycore-am64x can be migrated to OF_UPSTREAM.
Drop redundant device tree files, update MAINTAINERS and
defconfig's DEFAULT_DEVICE_TREE for ti vendor prefix accordingly.
While at it, drop the redundant definitions of AM642_PHYBOARD_ELECTRA_DTB
& SPL_AM642_PHYBOARD_ELECTRA_DTB from the binman dtsi file.
Signed-off-by: Wadim Egorov
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/k3-am64-phycore-som.dtsi | 320 --
.../arm/dts/k3-am642-phyboard-electra-rdk.dts | 302 -
arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 6 +-
arch/arm/mach-k3/am64x/Kconfig| 1 +
board/phytec/phycore_am64x/MAINTAINERS| 2 -
configs/phycore_am64x_a53_defconfig | 2 +-
7 files changed, 3 insertions(+), 631 deletions(-)
delete mode 100644 arch/arm/dts/k3-am64-phycore-som.dtsi
delete mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3646c64d05..48a2b85542 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1346,7 +1346,6 @@ dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \
- k3-am642-phyboard-electra-rdk.dtb \
k3-am642-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
diff --git a/arch/arm/dts/k3-am64-phycore-som.dtsi
b/arch/arm/dts/k3-am64-phycore-som.dtsi
deleted file mode 100644
index 1678e74cb7..00
--- a/arch/arm/dts/k3-am64-phycore-som.dtsi
+++ /dev/null
@@ -1,320 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
- * Author: Matt McKee
- *
- * Copyright (C) 2022 PHYTEC Messtechnik GmbH
- * Author: Wadim Egorov
- *
- * Product homepage:
- * https://www.phytec.com/product/phycore-am64x
- */
-
-#include
-#include
-#include
-
-/ {
- model = "PHYTEC phyCORE-AM64x";
- compatible = "phytec,am64-phycore-som", "ti,am642";
-
- aliases {
- ethernet0 = _port1;
- mmc0 =
- rtc0 = _som_rtc;
- };
-
- memory@8000 {
- device_type = "memory";
- reg = <0x 0x8000 0x 0x8000>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e80 {
- reg = <0x00 0x9e80 0x00 0x0180>; /* for OP-TEE
*/
- alignment = <0x1000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa000 0x00 0x10>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a010 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa010 0x00 0xf0>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a100 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa100 0x00 0x10>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a110 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa110 0x00 0xf0>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a200 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa200 0x00 0x10>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a210 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa210 0x00 0xf0>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a300 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa300 0x00 0x10>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a310 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa310 0x00 0xf0>;
- no-map;
- };
- };
-
- leds {
- compatible = "gpio-leds&qu
[PATCH 3/3] phycore-rk3288: Migrate to OF_UPSTREAM
The phycore-rk3288 can be migrated to OF_UPSTREAM.
Drop redundant device tree files, update MAINTAINERS and
defconfig's DEFAULT_DEVICE_TREE for rockchip vendor prefix accordingly.
Move device tree nodes required for u-boot to rk3288-phycore-rdk-u-boot.dtsi
such as chosen, i2c_eeprom_id and it's alias.
Signed-off-by: Wadim Egorov
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi | 19 +
arch/arm/dts/rk3288-phycore-rdk.dts | 271 ---
arch/arm/dts/rk3288-phycore-som.dtsi| 506
board/phytec/phycore_rk3288/MAINTAINERS | 2 -
configs/phycore-rk3288_defconfig| 7 +-
6 files changed, 23 insertions(+), 783 deletions(-)
delete mode 100644 arch/arm/dts/rk3288-phycore-rdk.dts
delete mode 100644 arch/arm/dts/rk3288-phycore-som.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 48a2b85542..a7a97a9f08 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -81,7 +81,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-evb.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
- rk3288-phycore-rdk.dtb \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
rk3288-rock-pi-n8.dtb \
diff --git a/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
index 383b383acc..12096eec54 100644
--- a/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
@@ -2,6 +2,16 @@
#include "rk3288-u-boot.dtsi"
+/ {
+ aliases {
+ eeprom0 = _eeprom_id;
+ };
+
+ chosen {
+ stdout-path =
+ };
+};
+
{
rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
@@ -29,6 +39,15 @@
bootph-all;
};
};
+
+ /* M24C32-D Identification page */
+ i2c_eeprom_id: eeprom@58 {
+ bootph-all;
+
+ compatible = "atmel,24c32";
+ reg = <0x58>;
+ pagesize = <32>;
+ };
};
{
diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts
b/arch/arm/dts/rk3288-phycore-rdk.dts
deleted file mode 100644
index ebea8e67ea..00
--- a/arch/arm/dts/rk3288-phycore-rdk.dts
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Device tree file for Phytec PCM-947 carrier board
- * Copyright (C) 2017 PHYTEC Messtechnik GmbH
- * Author: Wadim Egorov
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include
-#include "rk3288-phycore-som.dtsi"
-
-/ {
- model = "Phytec RK3288 PCM-947";
- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som",
"rockchip,rk3288";
-
- chosen {
- stdout-path =
- };
-
- user_buttons: user-buttons {
- compatible = "gpio-keys";
- pinctrl-names = "default";
-
[PATCH 1/3] phycore-am62x: Migrate to OF_UPSTREAM
The phycore-am62x can be migrated to OF_UPSTREAM.
Drop redundant device tree files, update MAINTAINERS and
defconfig's DEFAULT_DEVICE_TREE for ti vendor prefix accordingly.
Signed-off-by: Wadim Egorov
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/k3-am62-phycore-som.dtsi | 324 --
arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 --
arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 2 +-
arch/arm/mach-k3/am62x/Kconfig| 1 +
board/phytec/phycore_am62x/MAINTAINERS| 2 -
configs/phycore_am62x_a53_defconfig | 2 +-
7 files changed, 3 insertions(+), 595 deletions(-)
delete mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi
delete mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e..3646c64d05 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1354,7 +1354,6 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-beagleplay.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-r5.dtb \
- k3-am625-phyboard-lyra-rdk.dtb \
k3-am625-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
diff --git a/arch/arm/dts/k3-am62-phycore-som.dtsi
b/arch/arm/dts/k3-am62-phycore-som.dtsi
deleted file mode 100644
index aa43e7407e..00
--- a/arch/arm/dts/k3-am62-phycore-som.dtsi
+++ /dev/null
@@ -1,324 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
- * Author: Wadim Egorov
- *
- * Product homepage:
- * https://www.phytec.com/product/phycore-am62x
- */
-
-#include
-#include
-#include
-
-/ {
- model = "PHYTEC phyCORE-AM62x";
- compatible = "phytec,am62-phycore-som", "ti,am625";
-
- aliases {
- ethernet0 = _port1;
- gpio0 = _gpio0;
- gpio1 = _gpio1;
- i2c0 = _i2c0;
- mmc0 =
- rtc0 = _som_rtc;
- rtc1 = _rtc0;
- spi0 =
- };
-
- memory@8000 {
- device_type = "memory";
- reg = <0x 0x8000 0x 0x8000>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ramoops@9ca0 {
- compatible = "ramoops";
- reg = <0x00 0x9ca0 0x00 0x0010>;
- record-size = <0x8000>;
- console-size = <0x8000>;
- ftrace-size = <0x00>;
- pmsg-size = <0x8000>;
- };
-
- secure_tfa_ddr: tfa@9e78 {
- reg = <0x00 0x9e78 0x00 0x8>;
- alignment = <0x1000>;
- no-map;
- };
-
- secure_ddr: optee@9e80 {
- reg = <0x00 0x9e80 0x00 0x0180>; /* for OP-TEE
*/
- alignment = <0x1000>;
- no-map;
- };
-
- wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db0 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9db0 0x00 0x00c0>;
- no-map;
- };
- };
-
- vcc_5v0_som: regulator-vcc-5v0-som {
- compatible = "regulator-fixed";
- regulator-name = "VCC_5V0_SOM";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_1v8: regulator-vdd-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDD_1V8";
- regulator-min-microvolt = <180>;
- regulator-max-microvolt = <180>;
- vin-supply = <_5v0_som>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <_pins_default>;
-
- led-0 {
- color = ;
- gpios = <_gpio0 13 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- };
- };
-};
-
-_pmx0 {
- leds_pins_default: leds-default-pins {
-
[PATCH 0/3] *** Migrate some PHYTEC boards to OF_UPSTREAM ***
Migrate the boards I maintain to OF_UPSTREAM. Wadim Egorov (3): phycore-am62x: Migrate to OF_UPSTREAM phycore-am64x: Migrate to OF_UPSTREAM phycore-rk3288: Migrate to OF_UPSTREAM arch/arm/dts/Makefile | 3 - arch/arm/dts/k3-am62-phycore-som.dtsi | 324 --- arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 - arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 2 +- arch/arm/dts/k3-am64-phycore-som.dtsi | 320 --- .../arm/dts/k3-am642-phyboard-electra-rdk.dts | 302 --- arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 6 +- arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi | 19 + arch/arm/dts/rk3288-phycore-rdk.dts | 271 -- arch/arm/dts/rk3288-phycore-som.dtsi | 506 -- arch/arm/mach-k3/am62x/Kconfig| 1 + arch/arm/mach-k3/am64x/Kconfig| 1 + board/phytec/phycore_am62x/MAINTAINERS| 2 - board/phytec/phycore_am64x/MAINTAINERS| 2 - board/phytec/phycore_rk3288/MAINTAINERS | 2 - configs/phycore-rk3288_defconfig | 7 +- configs/phycore_am62x_a53_defconfig | 2 +- configs/phycore_am64x_a53_defconfig | 2 +- 18 files changed, 29 insertions(+), 2009 deletions(-) delete mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi delete mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts delete mode 100644 arch/arm/dts/k3-am64-phycore-som.dtsi delete mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk.dts delete mode 100644 arch/arm/dts/rk3288-phycore-rdk.dts delete mode 100644 arch/arm/dts/rk3288-phycore-som.dtsi -- 2.25.1
[PATCH v2 2/3] arm: mach-k3: am625: Provide a way to obtain boot device for non SPLs
Introduce get_boot_device() to obtain the booting device. Make it also
available for non SPL builds so u-boot can also know the device it is
booting from.
Signed-off-by: Wadim Egorov
---
v2:
- Make get_boot_device() read bootindex out of OCRAM
---
arch/arm/mach-k3/Makefile| 1 +
arch/arm/mach-k3/am625_init.c| 95 +
arch/arm/mach-k3/am62x/Makefile | 2 +
arch/arm/mach-k3/am62x/boot.c| 103 +++
arch/arm/mach-k3/include/mach/hardware.h | 1 +
5 files changed, 108 insertions(+), 94 deletions(-)
create mode 100644 arch/arm/mach-k3/am62x/Makefile
create mode 100644 arch/arm/mach-k3/am62x/boot.c
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 42161376469..61ec4ea13cf 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
endif
obj-y += common.o security.o
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index c9c97b6ce19..56078099f09 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -243,100 +243,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32
boot_device)
}
}
-static u32 __get_backup_bootmedia(u32 devstat)
-{
- u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
- u32 bkup_bootmode_cfg =
- (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
-
- switch (bkup_bootmode) {
- case BACKUP_BOOT_DEVICE_UART:
- return BOOT_DEVICE_UART;
-
- case BACKUP_BOOT_DEVICE_USB:
- return BOOT_DEVICE_USB;
-
- case BACKUP_BOOT_DEVICE_ETHERNET:
- return BOOT_DEVICE_ETHERNET;
-
- case BACKUP_BOOT_DEVICE_MMC:
- if (bkup_bootmode_cfg)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BACKUP_BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BACKUP_BOOT_DEVICE_I2C:
- return BOOT_DEVICE_I2C;
-
- case BACKUP_BOOT_DEVICE_DFU:
- if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
- };
-
- return BOOT_DEVICE_RAM;
-}
-
-static u32 __get_primary_bootmedia(u32 devstat)
-{
- u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
- u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
-
- switch (bootmode) {
- case BOOT_DEVICE_OSPI:
- fallthrough;
- case BOOT_DEVICE_QSPI:
- fallthrough;
- case BOOT_DEVICE_XSPI:
- fallthrough;
- case BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BOOT_DEVICE_ETHERNET_RGMII:
- fallthrough;
- case BOOT_DEVICE_ETHERNET_RMII:
- return BOOT_DEVICE_ETHERNET;
-
- case BOOT_DEVICE_EMMC:
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_MMC:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
- MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_DFU:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
-
- case BOOT_DEVICE_NOBOOT:
- return BOOT_DEVICE_RAM;
- }
-
- return bootmode;
-}
-
u32 spl_boot_device(void)
{
- u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
- u32 bootmedia;
-
- if (bootindex == K3_PRIMARY_BOOTMODE)
- bootmedia = __get_primary_bootmedia(devstat);
- else
- bootmedia = __get_backup_bootmedia(devstat);
-
- debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex =
%d\n",
- __func__, devstat, bootmedia, bootindex);
-
- return bootmedia;
+ return get_boot_device();
}
diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile
new file mode 100644
index 000..acf09c3426c
--- /dev/null
+++ b/arch/arm/mach-k3/am62x/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0+
+obj-y += boot.o
diff --git a/arch/arm/mach-k3/am62x/boot.c b/arch/arm/mach-k3/am62x/boot.c
new file mode 100644
index
[PATCH v2 3/3] board: phycore-am62x: Extend for better environment handling
Select environment location based on the device we boot from.
Also, introduce a "boot" variable that represents the current boot
device and can be used by scripts.
Signed-off-by: Wadim Egorov
---
board/phytec/phycore_am62x/phycore-am62x.c | 64 ++
configs/phycore_am62x_a53_defconfig| 1 +
2 files changed, 65 insertions(+)
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c
b/board/phytec/phycore_am62x/phycore-am62x.c
index 91a24018c40..618b4c370d1 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -57,3 +57,67 @@ void spl_board_init(void)
MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
}
#endif
+
+#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
+int mmc_get_env_dev(void)
+{
+ u32 boot_device = get_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return 0;
+ case BOOT_DEVICE_MMC2:
+ return 1;
+ };
+
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 boot_device = get_boot_device();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ case BOOT_DEVICE_SPI:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ default:
+ return ENVL_NOWHERE;
+ };
+}
+
+#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
+int board_late_init(void)
+{
+ u32 boot_device = get_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ env_set_ulong("mmcdev", 0);
+ env_set("boot", "mmc");
+ break;
+ case BOOT_DEVICE_MMC2:
+ env_set_ulong("mmcdev", 1);
+ env_set("boot", "mmc");
+ break;
+ case BOOT_DEVICE_SPI:
+ env_set("boot", "spi");
+ break;
+ case BOOT_DEVICE_ETHERNET:
+ env_set("boot", "net");
+ break;
+ };
+
+ return 0;
+}
+#endif
diff --git a/configs/phycore_am62x_a53_defconfig
b/configs/phycore_am62x_a53_defconfig
index ef6d08591a2..8e6f1786d81 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -34,6 +34,7 @@ CONFIG_BOOTSTD_FULL=y
CONFIG_SYS_BOOTM_LEN=0x80
CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80c8
--
2.34.1
[PATCH v2 1/3] arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL
Relocate booindex to OCRAM region after it gets opened by TIFS so the main domain bootloaders can have access to this data. Signed-off-by: Wadim Egorov --- v2: - Relocate bootindex to OCRAM, drop misleading comments and remove not needed changes --- arch/arm/mach-k3/am625_init.c | 8 arch/arm/mach-k3/include/mach/am62_hardware.h | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 6c96e881146..c9c97b6ce19 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -175,6 +175,14 @@ void board_init_f(ulong dummy) k3_sysfw_loader(true, NULL, NULL); } + /* +* Relocate boot information to OCRAM (after TIFS has opend this +* region for us) so the next bootloader stages can keep access to +* primary vs backup bootmodes. +*/ + if (IS_ENABLED(CONFIG_CPU_V7R)) + writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); + /* * Force probe of clk_k3 driver here to ensure basic default clock * configuration is always done. diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 54380f36e16..30c2f11062c 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -76,6 +76,7 @@ #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) #define ROM_EXTENDED_BOOT_DATA_INFO0x43c3f1e0 +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM0x7000F290 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c3 -- 2.34.1
[PATCH v2 0/3] *** Introduce get_boot_device() for K3 platform ***
It is handy to have some u-boot environment variables set based on the current booting device. Provide a way to obtain the boot device for non SPLs by factoring out spl_boot_device() into an own function get_boot_device(). v2: - Relocate bootindex to OCRAM, drop misleading comments and remove not needed changes - Make get_boot_device() read bootindex out of OCRAM - Add user for get_boot_device(), patch 3 v1: https://lists.denx.de/pipermail/u-boot/2024-February/546770.html Wadim Egorov (3): arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL arm: mach-k3: am625: Provide a way to obtain boot device for non SPLs board: phycore-am62x: Extend for better environment handling arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/am625_init.c | 103 ++ arch/arm/mach-k3/am62x/Makefile | 2 + arch/arm/mach-k3/am62x/boot.c | 103 ++ arch/arm/mach-k3/include/mach/am62_hardware.h | 1 + arch/arm/mach-k3/include/mach/hardware.h | 1 + board/phytec/phycore_am62x/phycore-am62x.c| 64 +++ configs/phycore_am62x_a53_defconfig | 1 + 8 files changed, 182 insertions(+), 94 deletions(-) create mode 100644 arch/arm/mach-k3/am62x/Makefile create mode 100644 arch/arm/mach-k3/am62x/boot.c -- 2.34.1
Re: [PATCH 1/2] arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL
Am 01.04.24 um 16:46 schrieb Bryan Brattlof:
On April 1, 2024 thus sayeth Wadim Egorov:
Hi Vignesh, Hi Bryan,
Am 05.03.24 um 18:36 schrieb Raghavendra, Vignesh:
On 3/5/2024 11:04 PM, Bryan Brattlof wrote:
On March 5, 2024 thus sayeth Vignesh Raghavendra:
On 05/03/24 01:57, Bryan Brattlof wrote:
Hey Vignesh!
On March 4, 2024 thus sayeth Vignesh Raghavendra:
Hi Wadim,
On 26/02/24 19:00, Wadim Egorov wrote:
Texas Instruments has begun enabling security settings on the SoCs it
produces to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.
One way ROM and TIFS do this is by enabling firewalls to protect the
OCSRAM and HSM RAM regions they're using during bootup.
The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect
itself from the main domain applications. This means the 'bootindex'
value in HSM RAM, left by ROM to indicate if we're using the primary
or secondary boot-method, must be moved to OCSRAM (that TIFS has open
for us) before we make the jump to the main domain so the main domain's
bootloaders can keep access to this information.
Based on commit
b672e8581070 ("arm: mach-k3: copy bootindex to OCRAM for main domain SPL")
I was thinking, even if the reason described here is not right or does not
apply to the am62x, it is still a valid solution for carrying this variable
into the context for next stage A53 bootloader.
store_boot_info_from_rom() stores the index to the bootindex (.data)
variable which makes sure it is valid in R5 SPL context. But the next stage
bootloader does not know anything about the bootindex variable. So from my
understanding it needs to be copied to a different region to preserve the
data for next stage bootloaders.
Or do I miss something?
That's correct. We typically put this bootindex variable in the same
location for both SPLs.
So basically the patch can stay almost as is, but maybe the misleading
comments in am62_hardware.h should be removed.
~Bryan
FYI, this is mostly a problem in non SPL flow (TI prosperity SBL for
example) where HSM RAM would be used by HSM firmware. This should be a
issue in R5 SPL flow. Do you see any issues today? If so, whats the
TIFS firmware being used?
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/Kconfig | 3 ++-
arch/arm/mach-k3/am625_init.c | 15 +--
arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 03898424c9..f5d06593f7 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -75,7 +75,8 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
- default 0x43c3f290 if SOC_K3_AM625
+ default 0x43c3f290 if SOC_K3_AM625 && CPU_V7R
+ default 0x7000f290 if SOC_K3_AM625 && ARM64
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
help
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 6c96e88114..67cf63b103 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -35,8 +35,10 @@ static struct rom_extended_boot_data bootdata
__section(".data");
static void store_boot_info_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
- memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
- sizeof(struct rom_extended_boot_data));
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+ }
}
static void ctrl_mmr_unlock(void)
@@ -175,6 +177,15 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(true, NULL, NULL);
}
+#if defined(CONFIG_CPU_V7R)
+ /*
+* Relocate boot information to OCRAM (after TIFS has opend this
+* region for us) so the next bootloader stages can keep access to
+* primary vs backup bootmodes.
+*/
+ writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM);
+#endif
+
/*
* Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done.
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h
b/arch/arm/mach-k3/include/mach/am62_hardware.h
index 54380f36e1..9f504f4642 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -76,8 +76,23 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
+#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
+/
Re: [PATCH 1/2] arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL
Hi Vignesh, Hi Bryan,
Am 05.03.24 um 18:36 schrieb Raghavendra, Vignesh:
On 3/5/2024 11:04 PM, Bryan Brattlof wrote:
On March 5, 2024 thus sayeth Vignesh Raghavendra:
On 05/03/24 01:57, Bryan Brattlof wrote:
Hey Vignesh!
On March 4, 2024 thus sayeth Vignesh Raghavendra:
Hi Wadim,
On 26/02/24 19:00, Wadim Egorov wrote:
Texas Instruments has begun enabling security settings on the SoCs it
produces to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.
One way ROM and TIFS do this is by enabling firewalls to protect the
OCSRAM and HSM RAM regions they're using during bootup.
The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect
itself from the main domain applications. This means the 'bootindex'
value in HSM RAM, left by ROM to indicate if we're using the primary
or secondary boot-method, must be moved to OCSRAM (that TIFS has open
for us) before we make the jump to the main domain so the main domain's
bootloaders can keep access to this information.
Based on commit
b672e8581070 ("arm: mach-k3: copy bootindex to OCRAM for main domain SPL")
I was thinking, even if the reason described here is not right or does
not apply to the am62x, it is still a valid solution for carrying this
variable into the context for next stage A53 bootloader.
store_boot_info_from_rom() stores the index to the bootindex (.data)
variable which makes sure it is valid in R5 SPL context. But the next
stage bootloader does not know anything about the bootindex variable. So
from my understanding it needs to be copied to a different region to
preserve the data for next stage bootloaders.
Or do I miss something?
Regards,
Wadim
FYI, this is mostly a problem in non SPL flow (TI prosperity SBL for
example) where HSM RAM would be used by HSM firmware. This should be a
issue in R5 SPL flow. Do you see any issues today? If so, whats the
TIFS firmware being used?
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/Kconfig | 3 ++-
arch/arm/mach-k3/am625_init.c | 15 +--
arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 03898424c9..f5d06593f7 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -75,7 +75,8 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
- default 0x43c3f290 if SOC_K3_AM625
+ default 0x43c3f290 if SOC_K3_AM625 && CPU_V7R
+ default 0x7000f290 if SOC_K3_AM625 && ARM64
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
help
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 6c96e88114..67cf63b103 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -35,8 +35,10 @@ static struct rom_extended_boot_data bootdata
__section(".data");
static void store_boot_info_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
- memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
- sizeof(struct rom_extended_boot_data));
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+ }
}
static void ctrl_mmr_unlock(void)
@@ -175,6 +177,15 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(true, NULL, NULL);
}
+#if defined(CONFIG_CPU_V7R)
+ /*
+* Relocate boot information to OCRAM (after TIFS has opend this
+* region for us) so the next bootloader stages can keep access to
+* primary vs backup bootmodes.
+*/
+ writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM);
+#endif
+
/*
* Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done.
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h
b/arch/arm/mach-k3/include/mach/am62_hardware.h
index 54380f36e1..9f504f4642 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -76,8 +76,23 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
+#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
+/*
+ * During the boot process ROM will kill anything that writes to OCSRAM.
R5 ROM is long gone when R5 SPL starts, how would it kill anything?
Looks like this was based on my patch long ago for the AM62Ax family.
From what little I remember about this was ROM is leaving behind a
firewall that we need TI
Re: [PATCH 2/3] configs: imx93-phyboard-segin: Add USB support.
Am 19.03.24 um 14:58 schrieb Marek Vasut: On 3/19/24 9:39 AM, Wadim Egorov wrote: Am 18.03.24 um 22:48 schrieb Marek Vasut: On 3/18/24 6:16 PM, Mathieu Othacehe wrote: Enable the `usb` command and some USB drivers. Signed-off-by: Mathieu Othacehe --- configs/imx93-phyboard-segin_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig index 24f9bd553aa..5acb987b817 100644 --- a/configs/imx93-phyboard-segin_defconfig +++ b/configs/imx93-phyboard-segin_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_STACK=0x20519dd0 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x72 CONFIG_CMD_DEKBLOB=y +CONFIG_CMD_USB=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x8800 CONFIG_SYS_LOAD_ADDR=0x8040 CONFIG_SYS_MEMTEST_START=0x8000 @@ -132,6 +133,13 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 Shouldn't this by Phytec or similar USB IDs ? AFAIK, PHYTEC does not have its own IDs registered yet. So the freescale IDs should be fine. Manufacturer can still be Phytec , can it not ? Yes, we can use PHYTEC for manufacturer.
Re: [PATCH 2/3] configs: imx93-phyboard-segin: Add USB support.
Am 18.03.24 um 22:48 schrieb Marek Vasut: On 3/18/24 6:16 PM, Mathieu Othacehe wrote: Enable the `usb` command and some USB drivers. Signed-off-by: Mathieu Othacehe --- configs/imx93-phyboard-segin_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig index 24f9bd553aa..5acb987b817 100644 --- a/configs/imx93-phyboard-segin_defconfig +++ b/configs/imx93-phyboard-segin_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_STACK=0x20519dd0 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x72 CONFIG_CMD_DEKBLOB=y +CONFIG_CMD_USB=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x8800 CONFIG_SYS_LOAD_ADDR=0x8040 CONFIG_SYS_MEMTEST_START=0x8000 @@ -132,6 +133,13 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 Shouldn't this by Phytec or similar USB IDs ? AFAIK, PHYTEC does not have its own IDs registered yet. So the freescale IDs should be fine.
Re: [PATCH 1/2] arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL
Hi Vignesh,
Am 04.03.24 um 06:06 schrieb Vignesh Raghavendra:
Hi Wadim,
On 26/02/24 19:00, Wadim Egorov wrote:
Texas Instruments has begun enabling security settings on the SoCs it
produces to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.
One way ROM and TIFS do this is by enabling firewalls to protect the
OCSRAM and HSM RAM regions they're using during bootup.
The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect
itself from the main domain applications. This means the 'bootindex'
value in HSM RAM, left by ROM to indicate if we're using the primary
or secondary boot-method, must be moved to OCSRAM (that TIFS has open
for us) before we make the jump to the main domain so the main domain's
bootloaders can keep access to this information.
Based on commit
b672e8581070 ("arm: mach-k3: copy bootindex to OCRAM for main domain SPL")
FYI, this is mostly a problem in non SPL flow (TI prosperity SBL for
example) where HSM RAM would be used by HSM firmware. This should be a
issue in R5 SPL flow. Do you see any issues today? If so, whats the
TIFS firmware being used?
I remember I was losing the bootindex using ti/downstream u-boot.
But can't figure out the exact version anymore.
Just did a bit of testing and I can not see the Issue with the current
u-boot.
Boot index in 0x43c3f290 stays intact.
Would it be okay to drop this patch and keep only the 2nd patch that
factors out into get_boot_device()?
Regards,
Wadim
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/Kconfig | 3 ++-
arch/arm/mach-k3/am625_init.c | 15 +--
arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 03898424c9..f5d06593f7 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -75,7 +75,8 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
- default 0x43c3f290 if SOC_K3_AM625
+ default 0x43c3f290 if SOC_K3_AM625 && CPU_V7R
+ default 0x7000f290 if SOC_K3_AM625 && ARM64
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
help
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 6c96e88114..67cf63b103 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -35,8 +35,10 @@ static struct rom_extended_boot_data bootdata
__section(".data");
static void store_boot_info_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
- memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
- sizeof(struct rom_extended_boot_data));
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+ }
}
static void ctrl_mmr_unlock(void)
@@ -175,6 +177,15 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(true, NULL, NULL);
}
+#if defined(CONFIG_CPU_V7R)
+ /*
+* Relocate boot information to OCRAM (after TIFS has opend this
+* region for us) so the next bootloader stages can keep access to
+* primary vs backup bootmodes.
+*/
+ writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM);
+#endif
+
/*
* Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done.
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h
b/arch/arm/mach-k3/include/mach/am62_hardware.h
index 54380f36e1..9f504f4642 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -76,8 +76,23 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
+#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
+/*
+ * During the boot process ROM will kill anything that writes to OCSRAM.
R5 ROM is long gone when R5 SPL starts, how would it kill anything?
+ * This means the wakeup SPL cannot use this region during boot. To
+ * complicate things, TIFS will set a firewall between HSM RAM and the
+ * main domain.
+ *
+ * So, during the wakeup SPL, we will need to store the EEPROM data
+ * somewhere in HSM RAM, and the main domain's SPL will need to store it
+ * somewhere in OCSRAM
+ */
+#ifdef CONFIG_CPU_V7R
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START0x43c3
+#else
+ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START0x7001
Why not 0x7000 ?
+#endif /* CONFIG_CPU_V7R */
Can't we store directly in OCRAM in both stages? Th
[PATCH] doc: board: phytec: phycore-am62x: Update artifact names
Use proper binary artifact names for HSFS devices. Do not use the *_unsigned binaries. Signed-off-by: Wadim Egorov --- doc/board/phytec/phycore-am62x.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index 1d641a78cf..bc6d524669 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -92,9 +92,9 @@ Assuming the uSD card is `/dev/mmcblk0`: To boot from a micro SD card on a HSFS device simply copy the following artifacts to the FAT partition: -* tiboot3.bin from R5 build as tiboot3.bin -* tispl.bin_unsigned from Cortex-A build as tispl.bin -* u-boot.img_unsigned from Cortex-A build as u-boot.img +* tiboot3.bin from R5 build +* tispl.bin from Cortex-A build +* u-boot.img from Cortex-A build Boot -- 2.34.1
[PATCH v3 2/2] doc: board: phytec: Add phyCORE-AM64x
Add documentation for PHYTEC phyCORE-AM64x SoM.
Signed-off-by: Wadim Egorov
Reviewed-by: Dhruva Gole
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am64x.rst | 159 +
2 files changed, 160 insertions(+)
create mode 100644 doc/board/phytec/phycore-am64x.rst
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index fea0b07620..99848a9e95 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -9,5 +9,6 @@ PHYTEC
imx8mm-phygate-tauri-l
imx93-phyboard-segin
phycore-am62x
+ phycore-am64x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am64x.rst
b/doc/board/phytec/phycore-am64x.rst
new file mode 100644
index 00..a27ad01027
--- /dev/null
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -0,0 +1,159 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov
+
+phyCORE-AM64x
+=
+
+The `phyCORE-AM64x <https://www.phytec.com/product/phycore-am64x>`_ is a
+SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family.
+
+A development Kit, called `phyBOARD-Lyra
<https://www.phytec.com/product/phyboard-am64x>`_
+is used as a carrier board reference design around the AM64x SoM.
+
+Quickstart
+--
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+---
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am64x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am64x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am64x
+ # we don't use any extra OPTEE parameters
+ unset OPTEE_EXTRA_ARGS
+
+.. include:: ../ti/am62x_sk.rst
+:start-after: .. am62x_evm_rst_include_start_build_steps
+:end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from a micro SD card on a HSFS device simply copy the following
+artifacts to the FAT partition:
+
+* tiboot3.bin from R5 build
+* tispl.bin from Cortex-A build
+* u-boot.img from Cortex-A build
+
+Boot
+
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+
+Boot Modes
+--
+
+The phyCORE-AM64x development kit supports booting from many different
+interfaces. By default, the development kit is set to boot from the micro-SD
+card. To change the boot device, DIP switches S5 and S6 can be used.
+Boot switches should be changed with power off.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW3: 12345678
+ - SW4: 12345678
+
+ * - uSD
+ - 1110
+ - 0100
+
+ * - eMMC
+ - 11010010
+
[PATCH v3 0/2] *** Add support for phyCORE-AM64x ***
Add basic support for the phyCORE-AM64x. v1: https://lists.denx.de/pipermail/u-boot/2024-January/544649.html v2: https://lists.denx.de/pipermail/u-boot/2024-February/546757.html v3: - Update doc to use proper binary artifacts for HSFS devices - Add Dhruva's Reviewed-by Wadim Egorov (2): board: phytec: am64x: Add PHYTEC phyCORE-AM64x SoM doc: board: phytec: Add phyCORE-AM64x arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi | 2189 + arch/arm/dts/k3-am64-phycore-som.dtsi | 320 +++ .../k3-am642-phyboard-electra-rdk-u-boot.dtsi | 147 ++ .../arm/dts/k3-am642-phyboard-electra-rdk.dts | 302 +++ arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 457 arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts | 140 ++ arch/arm/mach-k3/am64x/Kconfig| 19 + board/phytec/phycore_am64x/Kconfig| 33 + board/phytec/phycore_am64x/MAINTAINERS| 15 + board/phytec/phycore_am64x/Makefile |9 + board/phytec/phycore_am64x/board-cfg.yaml | 36 + board/phytec/phycore_am64x/phycore-am64x.c| 50 + board/phytec/phycore_am64x/phycore_am64x.env | 23 + board/phytec/phycore_am64x/pm-cfg.yaml| 12 + board/phytec/phycore_am64x/rm-cfg.yaml| 1215 + board/phytec/phycore_am64x/sec-cfg.yaml | 379 +++ configs/phycore_am64x_a53_defconfig | 167 ++ configs/phycore_am64x_r5_defconfig| 179 ++ doc/board/phytec/index.rst|1 + doc/board/phytec/phycore-am64x.rst| 159 ++ include/configs/phycore_am64x.h | 15 + 22 files changed, 5870 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am64-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk.dts create mode 100644 arch/arm/dts/k3-am642-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am64x/Kconfig create mode 100644 board/phytec/phycore_am64x/MAINTAINERS create mode 100644 board/phytec/phycore_am64x/Makefile create mode 100644 board/phytec/phycore_am64x/board-cfg.yaml create mode 100644 board/phytec/phycore_am64x/phycore-am64x.c create mode 100644 board/phytec/phycore_am64x/phycore_am64x.env create mode 100644 board/phytec/phycore_am64x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am64x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am64x/sec-cfg.yaml create mode 100644 configs/phycore_am64x_a53_defconfig create mode 100644 configs/phycore_am64x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am64x.rst create mode 100644 include/configs/phycore_am64x.h -- 2.34.1
Re: [PATCH v2 2/2] doc: board: phytec: Add phyCORE-AM64x
Am 28.02.24 um 06:45 schrieb Dhruva Gole: Hi, On Feb 26, 2024 at 13:23:41 +0100, Wadim Egorov wrote: Add documentation for PHYTEC phyCORE-AM64x SoM. Signed-off-by: Wadim Egorov --- doc/board/phytec/index.rst | 1 + doc/board/phytec/phycore-am64x.rst | 159 + 2 files changed, 160 insertions(+) create mode 100644 doc/board/phytec/phycore-am64x.rst diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index fea0b07620..99848a9e95 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -9,5 +9,6 @@ PHYTEC imx8mm-phygate-tauri-l imx93-phyboard-segin phycore-am62x + phycore-am64x phycore-imx8mm phycore-imx8mp diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst new file mode 100644 index 00..202b756dc4 --- /dev/null +++ b/doc/board/phytec/phycore-am64x.rst @@ -0,0 +1,159 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Wadim Egorov + +phyCORE-AM64x += + +The `phyCORE-AM64x <https://www.phytec.com/product/phycore-am64x>`_ is a +SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination +with different carrier boards. This module can come with different sizes and +models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family. + +A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am64x>`_ +is used as a carrier board reference design around the AM64x SoM. + +Quickstart +-- + +* Download sources and TI firmware blobs +* Build Trusted Firmware-A +* Build OP-TEE +* Build U-Boot for the R5 +* Build U-Boot for the A53 +* Create bootable uSD Card +* Boot + +Sources +--- + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_boot_sources +:end-before: .. k3_rst_include_end_boot_sources + +Build procedure +--- + +Setup the environment variables: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_desc +:end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_board_env_vars_desc +:end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_defn +:end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=phycore_am64x_r5_defconfig + $ export UBOOT_CFG_CORTEXA=phycore_am64x_a53_defconfig + $ export TFA_BOARD=lite + $ # we don't use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am64x + # we don't use any extra OPTEE parameters + unset OPTEE_EXTRA_ARGS + +.. include:: ../ti/am62x_sk.rst +:start-after: .. am62x_evm_rst_include_start_build_steps +:end-before: .. am62x_evm_rst_include_end_build_steps + +uSD Card creation +- + +Use fdisk to partition the uSD card. The layout should look similar to: + +.. code-block:: bash + + $ sudo fdisk -l /dev/mmcblk0 + Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors + Units: sectors of 1 * 512 = 512 bytes + Sector size (logical/physical): 512 bytes / 512 bytes + I/O size (minimum/optimal): 512 bytes / 512 bytes + Disklabel type: dos + Disk identifier: 0x6583d9a3 + + Device Boot Start End Sectors Size Id Type + /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA) + /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux + + +Once partitioned, the boot partition has to be formatted with a FAT filesystem. +Assuming the uSD card is `/dev/mmcblk0`: + +.. code-block:: bash + + $ mkfs.vfat /dev/mmcblk0p1 + +To boot from a micro SD card on a HSFS device simply copy the following +artifacts to the FAT partition: + +* tiboot3.bin from R5 build as tiboot3.bin +* tispl.bin_unsigned from Cortex-A build as tispl.bin +* u-boot.img_unsigned from Cortex-A build as u-boot.img Is the _unsigned really required? I guess the regular tispl and u-boot.img should also work right? It will just skip auth I guess. No, it is not required. Copy it from phycore-am62x.rst. Thanks, I will update both doc files. [...] Mostly looks good, thanks! Reviewed-by: Dhruva Gole
[PATCH 2/2] arm: mach-k3: am625: Provide a way to obtain boot device for non SPLs
Introduce get_boot_device() to obtain the booting device. Make it also
available for non SPL builds so u-boot can also know the device it is
booting from.
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/Makefile| 1 +
arch/arm/mach-k3/am625_init.c| 95 +
arch/arm/mach-k3/am62x/Makefile | 2 +
arch/arm/mach-k3/am62x/boot.c| 103 +++
arch/arm/mach-k3/include/mach/hardware.h | 1 +
5 files changed, 108 insertions(+), 94 deletions(-)
create mode 100644 arch/arm/mach-k3/am62x/Makefile
create mode 100644 arch/arm/mach-k3/am62x/boot.c
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 4216137646..61ec4ea13c 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
endif
obj-y += common.o security.o
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 67cf63b103..85cd3f895a 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -246,100 +246,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32
boot_device)
}
}
-static u32 __get_backup_bootmedia(u32 devstat)
-{
- u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
- u32 bkup_bootmode_cfg =
- (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
-
- switch (bkup_bootmode) {
- case BACKUP_BOOT_DEVICE_UART:
- return BOOT_DEVICE_UART;
-
- case BACKUP_BOOT_DEVICE_USB:
- return BOOT_DEVICE_USB;
-
- case BACKUP_BOOT_DEVICE_ETHERNET:
- return BOOT_DEVICE_ETHERNET;
-
- case BACKUP_BOOT_DEVICE_MMC:
- if (bkup_bootmode_cfg)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BACKUP_BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BACKUP_BOOT_DEVICE_I2C:
- return BOOT_DEVICE_I2C;
-
- case BACKUP_BOOT_DEVICE_DFU:
- if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
- };
-
- return BOOT_DEVICE_RAM;
-}
-
-static u32 __get_primary_bootmedia(u32 devstat)
-{
- u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
- u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
-
- switch (bootmode) {
- case BOOT_DEVICE_OSPI:
- fallthrough;
- case BOOT_DEVICE_QSPI:
- fallthrough;
- case BOOT_DEVICE_XSPI:
- fallthrough;
- case BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BOOT_DEVICE_ETHERNET_RGMII:
- fallthrough;
- case BOOT_DEVICE_ETHERNET_RMII:
- return BOOT_DEVICE_ETHERNET;
-
- case BOOT_DEVICE_EMMC:
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_MMC:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
- MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_DFU:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
-
- case BOOT_DEVICE_NOBOOT:
- return BOOT_DEVICE_RAM;
- }
-
- return bootmode;
-}
-
u32 spl_boot_device(void)
{
- u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
- u32 bootmedia;
-
- if (bootindex == K3_PRIMARY_BOOTMODE)
- bootmedia = __get_primary_bootmedia(devstat);
- else
- bootmedia = __get_backup_bootmedia(devstat);
-
- debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex =
%d\n",
- __func__, devstat, bootmedia, bootindex);
-
- return bootmedia;
+ return get_boot_device();
}
diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile
new file mode 100644
index 00..acf09c3426
--- /dev/null
+++ b/arch/arm/mach-k3/am62x/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0+
+obj-y += boot.o
diff --git a/arch/arm/mach-k3/am62x/boot.c b/arch/arm/mach-k3/am62x/boot.c
new file mode 100644
index 00..966500edc9
--- /dev/null
+++ b/arch/arm/mach-k3/am62
[PATCH 1/2] arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL
Texas Instruments has begun enabling security settings on the SoCs it
produces to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.
One way ROM and TIFS do this is by enabling firewalls to protect the
OCSRAM and HSM RAM regions they're using during bootup.
The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect
itself from the main domain applications. This means the 'bootindex'
value in HSM RAM, left by ROM to indicate if we're using the primary
or secondary boot-method, must be moved to OCSRAM (that TIFS has open
for us) before we make the jump to the main domain so the main domain's
bootloaders can keep access to this information.
Based on commit
b672e8581070 ("arm: mach-k3: copy bootindex to OCRAM for main domain SPL")
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/Kconfig | 3 ++-
arch/arm/mach-k3/am625_init.c | 15 +--
arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 03898424c9..f5d06593f7 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -75,7 +75,8 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
- default 0x43c3f290 if SOC_K3_AM625
+ default 0x43c3f290 if SOC_K3_AM625 && CPU_V7R
+ default 0x7000f290 if SOC_K3_AM625 && ARM64
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
help
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 6c96e88114..67cf63b103 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -35,8 +35,10 @@ static struct rom_extended_boot_data bootdata
__section(".data");
static void store_boot_info_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
- memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
- sizeof(struct rom_extended_boot_data));
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+ }
}
static void ctrl_mmr_unlock(void)
@@ -175,6 +177,15 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(true, NULL, NULL);
}
+#if defined(CONFIG_CPU_V7R)
+ /*
+* Relocate boot information to OCRAM (after TIFS has opend this
+* region for us) so the next bootloader stages can keep access to
+* primary vs backup bootmodes.
+*/
+ writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM);
+#endif
+
/*
* Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done.
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h
b/arch/arm/mach-k3/include/mach/am62_hardware.h
index 54380f36e1..9f504f4642 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -76,8 +76,23 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
#define ROM_EXTENDED_BOOT_DATA_INFO0x43c3f1e0
+#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
+/*
+ * During the boot process ROM will kill anything that writes to OCSRAM.
+ * This means the wakeup SPL cannot use this region during boot. To
+ * complicate things, TIFS will set a firewall between HSM RAM and the
+ * main domain.
+ *
+ * So, during the wakeup SPL, we will need to store the EEPROM data
+ * somewhere in HSM RAM, and the main domain's SPL will need to store it
+ * somewhere in OCSRAM
+ */
+#ifdef CONFIG_CPU_V7R
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c3
+#else
+ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START0x7001
+#endif /* CONFIG_CPU_V7R */
static inline int k3_get_core_nr(void)
{
--
2.34.1
[PATCH 0/2] *** Introduce get_boot_device() for K3 platform ***
It is handy to have some u-boot environment variables set based on the current booting device. Provide a way to obtain the boot device for non SPLs by factoring out spl_boot_device() into an own function get_boot_device(). Wadim Egorov (2): arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL arm: mach-k3: am625: Provide a way to obtain boot device for non SPLs arch/arm/mach-k3/Kconfig | 3 +- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/am625_init.c | 110 +++--- arch/arm/mach-k3/am62x/Makefile | 2 + arch/arm/mach-k3/am62x/boot.c | 103 arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++ arch/arm/mach-k3/include/mach/hardware.h | 1 + 7 files changed, 138 insertions(+), 97 deletions(-) create mode 100644 arch/arm/mach-k3/am62x/Makefile create mode 100644 arch/arm/mach-k3/am62x/boot.c -- 2.34.1
[PATCH v2 2/2] doc: board: phytec: Add phyCORE-AM64x
Add documentation for PHYTEC phyCORE-AM64x SoM.
Signed-off-by: Wadim Egorov
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am64x.rst | 159 +
2 files changed, 160 insertions(+)
create mode 100644 doc/board/phytec/phycore-am64x.rst
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index fea0b07620..99848a9e95 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -9,5 +9,6 @@ PHYTEC
imx8mm-phygate-tauri-l
imx93-phyboard-segin
phycore-am62x
+ phycore-am64x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am64x.rst
b/doc/board/phytec/phycore-am64x.rst
new file mode 100644
index 00..202b756dc4
--- /dev/null
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -0,0 +1,159 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov
+
+phyCORE-AM64x
+=
+
+The `phyCORE-AM64x <https://www.phytec.com/product/phycore-am64x>`_ is a
+SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family.
+
+A development Kit, called `phyBOARD-Lyra
<https://www.phytec.com/product/phyboard-am64x>`_
+is used as a carrier board reference design around the AM64x SoM.
+
+Quickstart
+--
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+---
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am64x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am64x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am64x
+ # we don't use any extra OPTEE parameters
+ unset OPTEE_EXTRA_ARGS
+
+.. include:: ../ti/am62x_sk.rst
+:start-after: .. am62x_evm_rst_include_start_build_steps
+:end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from a micro SD card on a HSFS device simply copy the following
+artifacts to the FAT partition:
+
+* tiboot3.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Boot
+
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+
+Boot Modes
+--
+
+The phyCORE-AM64x development kit supports booting from many different
+interfaces. By default, the development kit is set to boot from the micro-SD
+card. To change the boot device, DIP switches S5 and S6 can be used.
+Boot switches should be changed with power off.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW3: 12345678
+ - SW4: 12345678
+
+ * - uSD
+ - 1110
+ - 0100
+
[PATCH v2 0/2] *** Add support for phyCORE-AM64x ***
Add basic support for the phyCORE-AM64x. v1: https://lists.denx.de/pipermail/u-boot/2024-January/544649.html v2: - Resync configs after savedefconfig - Set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 in R5 config Wadim Egorov (2): board: phytec: am64x: Add PHYTEC phyCORE-AM64x SoM doc: board: phytec: Add phyCORE-AM64x arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi | 2189 + arch/arm/dts/k3-am64-phycore-som.dtsi | 320 +++ .../k3-am642-phyboard-electra-rdk-u-boot.dtsi | 147 ++ .../arm/dts/k3-am642-phyboard-electra-rdk.dts | 302 +++ arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 457 arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts | 140 ++ arch/arm/mach-k3/am64x/Kconfig| 19 + board/phytec/phycore_am64x/Kconfig| 33 + board/phytec/phycore_am64x/MAINTAINERS| 15 + board/phytec/phycore_am64x/Makefile |9 + board/phytec/phycore_am64x/board-cfg.yaml | 36 + board/phytec/phycore_am64x/phycore-am64x.c| 50 + board/phytec/phycore_am64x/phycore_am64x.env | 23 + board/phytec/phycore_am64x/pm-cfg.yaml| 12 + board/phytec/phycore_am64x/rm-cfg.yaml| 1215 + board/phytec/phycore_am64x/sec-cfg.yaml | 379 +++ configs/phycore_am64x_a53_defconfig | 167 ++ configs/phycore_am64x_r5_defconfig| 179 ++ doc/board/phytec/index.rst|1 + doc/board/phytec/phycore-am64x.rst| 159 ++ include/configs/phycore_am64x.h | 15 + 22 files changed, 5870 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am64-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk.dts create mode 100644 arch/arm/dts/k3-am642-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am64x/Kconfig create mode 100644 board/phytec/phycore_am64x/MAINTAINERS create mode 100644 board/phytec/phycore_am64x/Makefile create mode 100644 board/phytec/phycore_am64x/board-cfg.yaml create mode 100644 board/phytec/phycore_am64x/phycore-am64x.c create mode 100644 board/phytec/phycore_am64x/phycore_am64x.env create mode 100644 board/phytec/phycore_am64x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am64x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am64x/sec-cfg.yaml create mode 100644 configs/phycore_am64x_a53_defconfig create mode 100644 configs/phycore_am64x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am64x.rst create mode 100644 include/configs/phycore_am64x.h -- 2.34.1
[PATCH 2/2] doc: board: phytec: Add phyCORE-AM64x
Add documentation for PHYTEC phyCORE-AM64x SoM.
Signed-off-by: Wadim Egorov
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am64x.rst | 159 +
2 files changed, 160 insertions(+)
create mode 100644 doc/board/phytec/phycore-am64x.rst
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index 965d40de4d..bf247313a3 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -8,5 +8,6 @@ PHYTEC
imx8mm-phygate-tauri-l
phycore-am62x
+ phycore-am64x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am64x.rst
b/doc/board/phytec/phycore-am64x.rst
new file mode 100644
index 00..202b756dc4
--- /dev/null
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -0,0 +1,159 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov
+
+phyCORE-AM64x
+=
+
+The `phyCORE-AM64x <https://www.phytec.com/product/phycore-am64x>`_ is a
+SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family.
+
+A development Kit, called `phyBOARD-Lyra
<https://www.phytec.com/product/phyboard-am64x>`_
+is used as a carrier board reference design around the AM64x SoM.
+
+Quickstart
+--
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+---
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am64x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am64x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am64x
+ # we don't use any extra OPTEE parameters
+ unset OPTEE_EXTRA_ARGS
+
+.. include:: ../ti/am62x_sk.rst
+:start-after: .. am62x_evm_rst_include_start_build_steps
+:end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from a micro SD card on a HSFS device simply copy the following
+artifacts to the FAT partition:
+
+* tiboot3.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Boot
+
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+
+Boot Modes
+--
+
+The phyCORE-AM64x development kit supports booting from many different
+interfaces. By default, the development kit is set to boot from the micro-SD
+card. To change the boot device, DIP switches S5 and S6 can be used.
+Boot switches should be changed with power off.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW3: 12345678
+ - SW4: 12345678
+
+ * - uSD
+ - 1110
+ - 0100
+
+ * - eMMC
+ - 11010010
+
[PATCH 0/2] *** Add support for phyCORE-AM64x ***
Add basic support for the phyCORE-AM64x.. Wadim Egorov (2): board: phytec: am64x: Add PHYTEC phyCORE-AM64x SoM doc: board: phytec: Add phyCORE-AM64x arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi | 2189 + arch/arm/dts/k3-am64-phycore-som.dtsi | 320 +++ .../k3-am642-phyboard-electra-rdk-u-boot.dtsi | 147 ++ .../arm/dts/k3-am642-phyboard-electra-rdk.dts | 302 +++ arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 457 arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts | 140 ++ arch/arm/mach-k3/am64x/Kconfig| 19 + board/phytec/phycore_am64x/Kconfig| 33 + board/phytec/phycore_am64x/MAINTAINERS| 15 + board/phytec/phycore_am64x/Makefile |9 + board/phytec/phycore_am64x/board-cfg.yaml | 36 + board/phytec/phycore_am64x/phycore-am64x.c| 50 + board/phytec/phycore_am64x/phycore_am64x.env | 23 + board/phytec/phycore_am64x/pm-cfg.yaml| 12 + board/phytec/phycore_am64x/rm-cfg.yaml| 1215 + board/phytec/phycore_am64x/sec-cfg.yaml | 379 +++ configs/phycore_am64x_a53_defconfig | 168 ++ configs/phycore_am64x_r5_defconfig| 180 ++ doc/board/phytec/index.rst|1 + doc/board/phytec/phycore-am64x.rst| 159 ++ include/configs/phycore_am64x.h | 15 + 22 files changed, 5872 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am64-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am642-phyboard-electra-rdk.dts create mode 100644 arch/arm/dts/k3-am642-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am64x/Kconfig create mode 100644 board/phytec/phycore_am64x/MAINTAINERS create mode 100644 board/phytec/phycore_am64x/Makefile create mode 100644 board/phytec/phycore_am64x/board-cfg.yaml create mode 100644 board/phytec/phycore_am64x/phycore-am64x.c create mode 100644 board/phytec/phycore_am64x/phycore_am64x.env create mode 100644 board/phytec/phycore_am64x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am64x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am64x/sec-cfg.yaml create mode 100644 configs/phycore_am64x_a53_defconfig create mode 100644 configs/phycore_am64x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am64x.rst create mode 100644 include/configs/phycore_am64x.h -- 2.34.1
Re: [Upstream] [PATCH v4 0/2] *** Add support for phyCORE-AM62x ***
Hello, is there something missing in this series for it to be applied? I would like to add support for a 2nd k3/am64x board based on this. So it would be nice to know if I can do it the same way or should wait for more k3 changes to come in first? Regards, Wadim Am 20.12.23 um 10:18 schrieb Wadim Egorov: v4: - Rebase on current next - Drop schema file overrides from binman v3: https://lists.denx.de/pipermail/u-boot/2023-December/539779.html v2: https://lists.denx.de/pipermail/u-boot/2023-November/538971.html v1: https://lists.denx.de/pipermail/u-boot/2023-October/535750.html Wadim Egorov (2): board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM doc: board: phytec: Add phyCORE-AM62x arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi | 2190 + arch/arm/dts/k3-am62-phycore-som.dtsi | 324 +++ .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 166 ++ arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 ++ arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 314 +++ arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 119 + arch/arm/mach-k3/am62x/Kconfig| 17 + board/phytec/phycore_am62x/Kconfig| 33 + board/phytec/phycore_am62x/MAINTAINERS| 15 + board/phytec/phycore_am62x/Makefile |8 + board/phytec/phycore_am62x/board-cfg.yaml | 36 + board/phytec/phycore_am62x/phycore-am62x.c| 59 + board/phytec/phycore_am62x/phycore_am62x.env | 23 + board/phytec/phycore_am62x/pm-cfg.yaml| 12 + board/phytec/phycore_am62x/rm-cfg.yaml| 1088 board/phytec/phycore_am62x/sec-cfg.yaml | 379 +++ configs/phycore_am62x_a53_defconfig | 115 + configs/phycore_am62x_r5_defconfig| 130 + doc/board/phytec/index.rst|1 + doc/board/phytec/phycore-am62x.rst| 158 ++ doc/board/ti/k3.rst |1 + include/configs/phycore_am62x.h | 15 + 23 files changed, 5472 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts create mode 100644 arch/arm/dts/k3-am625-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62x/Kconfig create mode 100644 board/phytec/phycore_am62x/MAINTAINERS create mode 100644 board/phytec/phycore_am62x/Makefile create mode 100644 board/phytec/phycore_am62x/board-cfg.yaml create mode 100644 board/phytec/phycore_am62x/phycore-am62x.c create mode 100644 board/phytec/phycore_am62x/phycore_am62x.env create mode 100644 board/phytec/phycore_am62x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/sec-cfg.yaml create mode 100644 configs/phycore_am62x_a53_defconfig create mode 100644 configs/phycore_am62x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am62x.rst create mode 100644 include/configs/phycore_am62x.h
[PATCH v4 2/2] doc: board: phytec: Add phyCORE-AM62x
Add documentation for PHYTEC phyCORE-AM62x SoM.
Signed-off-by: Wadim Egorov
Reviewed-by: Dhruva Gole
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am62x.rst | 158 +
doc/board/ti/k3.rst| 1 +
3 files changed, 160 insertions(+)
create mode 100644 doc/board/phytec/phycore-am62x.rst
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index a5b442045e..b914cc3fbd 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -6,5 +6,6 @@ PHYTEC
.. toctree::
:maxdepth: 2
+ phycore-am62x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am62x.rst
b/doc/board/phytec/phycore-am62x.rst
new file mode 100644
index 00..1d641a78cf
--- /dev/null
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -0,0 +1,158 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov
+
+phyCORE-AM62x
+=
+
+The `phyCORE-AM62x <https://www.phytec.com/product/phycore-am62x>`_ is a
+SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family.
+
+A development Kit, called `phyBOARD-Lyra
<https://www.phytec.com/product/phyboard-am62x>`_
+is used as a carrier board reference design around the AM62x SoM.
+
+Quickstart
+--
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+---
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am62x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am62x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include:: ../ti/am62x_sk.rst
+:start-after: .. am62x_evm_rst_include_start_build_steps
+:end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from a micro SD card on a HSFS device simply copy the following
+artifacts to the FAT partition:
+
+* tiboot3.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Boot
+
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+
+Boot Modes
+--
+
+The phyCORE-AM62x development kit supports booting from many different
+interfaces. By default, the development kit is set to boot from the micro-SD
+card. To change the boot device, DIP switches S5 and S6 can be used.
+Boot switches should be changed with power off.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW5: 12345678
+ - SW6: 12345678
+
+ * - uSD
+ - 110
[PATCH v4 0/2] *** Add support for phyCORE-AM62x ***
v4: - Rebase on current next - Drop schema file overrides from binman v3: https://lists.denx.de/pipermail/u-boot/2023-December/539779.html v2: https://lists.denx.de/pipermail/u-boot/2023-November/538971.html v1: https://lists.denx.de/pipermail/u-boot/2023-October/535750.html Wadim Egorov (2): board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM doc: board: phytec: Add phyCORE-AM62x arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi | 2190 + arch/arm/dts/k3-am62-phycore-som.dtsi | 324 +++ .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 166 ++ arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 ++ arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 314 +++ arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 119 + arch/arm/mach-k3/am62x/Kconfig| 17 + board/phytec/phycore_am62x/Kconfig| 33 + board/phytec/phycore_am62x/MAINTAINERS| 15 + board/phytec/phycore_am62x/Makefile |8 + board/phytec/phycore_am62x/board-cfg.yaml | 36 + board/phytec/phycore_am62x/phycore-am62x.c| 59 + board/phytec/phycore_am62x/phycore_am62x.env | 23 + board/phytec/phycore_am62x/pm-cfg.yaml| 12 + board/phytec/phycore_am62x/rm-cfg.yaml| 1088 board/phytec/phycore_am62x/sec-cfg.yaml | 379 +++ configs/phycore_am62x_a53_defconfig | 115 + configs/phycore_am62x_r5_defconfig| 130 + doc/board/phytec/index.rst|1 + doc/board/phytec/phycore-am62x.rst| 158 ++ doc/board/ti/k3.rst |1 + include/configs/phycore_am62x.h | 15 + 23 files changed, 5472 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts create mode 100644 arch/arm/dts/k3-am625-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62x/Kconfig create mode 100644 board/phytec/phycore_am62x/MAINTAINERS create mode 100644 board/phytec/phycore_am62x/Makefile create mode 100644 board/phytec/phycore_am62x/board-cfg.yaml create mode 100644 board/phytec/phycore_am62x/phycore-am62x.c create mode 100644 board/phytec/phycore_am62x/phycore_am62x.env create mode 100644 board/phytec/phycore_am62x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/sec-cfg.yaml create mode 100644 configs/phycore_am62x_a53_defconfig create mode 100644 configs/phycore_am62x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am62x.rst create mode 100644 include/configs/phycore_am62x.h -- 2.34.1
[PATCH v3 2/2] doc: board: phytec: Add phyCORE-AM62x
Add documentation for PHYTEC phyCORE-AM62x SoM.
Signed-off-by: Wadim Egorov
Reviewed-by: Dhruva Gole
---
v3:
- Add boot modes chapter
- Reference tiboot3.bin instead of GP binary for default flashing
- Minor spelling fixes
- Pick up Reviewed-by: Dhruva Gole
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am62x.rst | 158 +
doc/board/ti/k3.rst| 1 +
3 files changed, 160 insertions(+)
create mode 100644 doc/board/phytec/phycore-am62x.rst
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index a5b442045e..b914cc3fbd 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -6,5 +6,6 @@ PHYTEC
.. toctree::
:maxdepth: 2
+ phycore-am62x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am62x.rst
b/doc/board/phytec/phycore-am62x.rst
new file mode 100644
index 00..de73226183
--- /dev/null
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -0,0 +1,158 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov
+
+phyCORE-AM62x
+=
+
+The `phyCORE-AM62x <https://www.phytec.com/product/phycore-am62x>`_ is a
+SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family.
+
+A development Kit, called `phyBOARD-Lyra
<https://www.phytec.com/product/phyboard-am62x>`_
+is used as a carrier board reference design around the AM62x SoM.
+
+Quickstart
+--
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+---
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am62x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am62x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include:: ../ti/am62x_sk.rst
+:start-after: .. am62x_evm_rst_include_start_build_steps
+:end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from a micro SD card on a HSFS device simply copy the following
+artifacts to the FAT partition:
+
+* tiboot3.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Boot
+
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+
+Boot Modes
+--
+
+The phyCORE-AM62x development kit supports booting from many different
+interfaces. By default, the development kit is set to boot from the micro-SD
+card. To change the boot device, DIP switches S5 and S6 can be used.
+Boot switches should be changed with power off.
+
+.. l
[PATCH v3 0/2] *** Add support for phyCORE-AM62x ***
v3: - Add boot modes chapter - Reference tiboot3.bin instead of GP binary for default flashing - Minor spelling fixes - Pick up Reviewed-by: Dhruva Gole v2: https://lists.denx.de/pipermail/u-boot/2023-November/538971.html v1: https://lists.denx.de/pipermail/u-boot/2023-October/535750.html Wadim Egorov (2): board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM doc: board: phytec: Add phyCORE-AM62x arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi | 2190 + arch/arm/dts/k3-am62-phycore-som.dtsi | 324 +++ .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 166 ++ arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 ++ arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 380 +++ arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 119 + arch/arm/mach-k3/am62x/Kconfig| 17 + board/phytec/phycore_am62x/Kconfig| 33 + board/phytec/phycore_am62x/MAINTAINERS| 15 + board/phytec/phycore_am62x/Makefile |8 + board/phytec/phycore_am62x/board-cfg.yaml | 36 + board/phytec/phycore_am62x/phycore-am62x.c| 59 + board/phytec/phycore_am62x/phycore_am62x.env | 23 + board/phytec/phycore_am62x/pm-cfg.yaml| 12 + board/phytec/phycore_am62x/rm-cfg.yaml| 1088 board/phytec/phycore_am62x/sec-cfg.yaml | 379 +++ configs/phycore_am62x_a53_defconfig | 115 + configs/phycore_am62x_r5_defconfig| 130 + doc/board/phytec/index.rst|1 + doc/board/phytec/phycore-am62x.rst| 158 ++ doc/board/ti/k3.rst |1 + include/configs/phycore_am62x.h | 15 + 23 files changed, 5538 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts create mode 100644 arch/arm/dts/k3-am625-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62x/Kconfig create mode 100644 board/phytec/phycore_am62x/MAINTAINERS create mode 100644 board/phytec/phycore_am62x/Makefile create mode 100644 board/phytec/phycore_am62x/board-cfg.yaml create mode 100644 board/phytec/phycore_am62x/phycore-am62x.c create mode 100644 board/phytec/phycore_am62x/phycore_am62x.env create mode 100644 board/phytec/phycore_am62x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/sec-cfg.yaml create mode 100644 configs/phycore_am62x_a53_defconfig create mode 100644 configs/phycore_am62x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am62x.rst create mode 100644 include/configs/phycore_am62x.h -- 2.34.1
Re: [PATCH v2 2/2] doc: board: phytec: Add phyCORE-AM62x
Hi Dhruva, Am 01.12.23 um 11:10 schrieb Dhruva Gole: Hi, On Nov 30, 2023 at 12:56:07 +0100, Wadim Egorov wrote: Add documentation for PHYTEC phyCORE-AM62x SoM. Signed-off-by: Wadim Egorov --- v2: Rebased on top of -next Please CC Tom Rini on the series. --- doc/board/phytec/index.rst | 1 + doc/board/phytec/phycore-am62x.rst | 125 + doc/board/ti/k3.rst| 1 + 3 files changed, 127 insertions(+) create mode 100644 doc/board/phytec/phycore-am62x.rst diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index a5b442045e..b914cc3fbd 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -6,5 +6,6 @@ PHYTEC .. toctree:: :maxdepth: 2 + phycore-am62x phycore-imx8mm phycore-imx8mp diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst new file mode 100644 index 00..46312a73bc --- /dev/null +++ b/doc/board/phytec/phycore-am62x.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Wadim Egorov + +phyCORE-AM62x += + +The `phyCORE-AM62x <https://www.phytec.com/product/phycore-am62x>`_ is a +SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination +with different carrier boards. This module can come with different sizes and +models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family. + +A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am62x>`_ +is used as a carrier board reference design around the AM62x SoM. + +Quickstart +-- + +* Download sources and TI firmware blobs +* Build Trusted Firmware-A +* Build OP-TEE +* Build U-Boot for the R5 +* Build U-Boot for the A53 +* Create bootable uSD Card +* Boot + +Sources +--- + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_boot_sources +:end-before: .. k3_rst_include_end_boot_sources + +Build procedure +--- + +Setup the environment variables: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_desc +:end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_board_env_vars_desc +:end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_defn +:end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=phycore_am62x_r5_defconfig + $ export UBOOT_CFG_CORTEXA=phycore_am62x_a53_defconfig + $ export TFA_BOARD=lite + $ # we don't use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am62x + $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" Does this need to be the case? If it's just copied from AM62x then I think I need to fix that documentation, not sure if we necessarily need SW_RNG and thus disable HW_RNG upstream. The context here was we were enabling SW_RNG a while back due to a crash after suspend resume on AM62x, however that issue no longer seems to cause any lock ups/ crash. Yep, copy I'll remove it. + +.. include:: ../ti/am62x_sk.rst +:start-after: .. am62x_evm_rst_include_start_build_steps +:end-before: .. am62x_evm_rst_include_end_build_steps + +uSD Card creation +- + +Use fdisk to partition the uSD card. The layout should look similar to: + +.. code-block:: bash + + $ sudo fdisk -l /dev/mmcblk0 + Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors + Units: sectors of 1 * 512 = 512 bytes + Sector size (logical/physical): 512 bytes / 512 bytes + I/O size (minimum/optimal): 512 bytes / 512 bytes + Disklabel type: dos + Disk identifier: 0x6583d9a3 + + Device Boot Start End Sectors Size Id Type + /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA) + /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux + + +Once partitioned, the boot partition has to be formatted with a FAT filesystem. +Assuming the uSD card is `/dev/mmcblk0`: + +.. code-block:: bash + + $ mkfs.vfat /dev/mmcblk0p1 + +To boot from an uSD on a GP device simply copy the following artifacts to the nit: "a" micro SD card not an Are most of the SoM's GP devices? Otherwise thinking if we should make the documentation for HSFS as a default and GP as an exception? Or else just say copy tiboot3.bin as is on the SD card for HSFS devices and for GP (as you have done below) Currently, most devices around are GPs. But this will change. So making HSFS as default makes sense. +FAT partition: + +* tiboot3-am62x-gp-phycore-som.bin from R5 build as tiboot3.bin +* tispl.bin_unsigned from Cortex-A build as tispl.bin +* u-boot.img_unsigned from Cortex-A build as u-boot.img + +Boot + + +Put the uSD card in the slot on the board a
[PATCH v2 2/2] doc: board: phytec: Add phyCORE-AM62x
Add documentation for PHYTEC phyCORE-AM62x SoM.
Signed-off-by: Wadim Egorov
---
v2: Rebased on top of -next
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am62x.rst | 125 +
doc/board/ti/k3.rst| 1 +
3 files changed, 127 insertions(+)
create mode 100644 doc/board/phytec/phycore-am62x.rst
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index a5b442045e..b914cc3fbd 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -6,5 +6,6 @@ PHYTEC
.. toctree::
:maxdepth: 2
+ phycore-am62x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am62x.rst
b/doc/board/phytec/phycore-am62x.rst
new file mode 100644
index 00..46312a73bc
--- /dev/null
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -0,0 +1,125 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov
+
+phyCORE-AM62x
+=
+
+The `phyCORE-AM62x <https://www.phytec.com/product/phycore-am62x>`_ is a
+SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family.
+
+A development Kit, called `phyBOARD-Lyra
<https://www.phytec.com/product/phyboard-am62x>`_
+is used as a carrier board reference design around the AM62x SoM.
+
+Quickstart
+--
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+---
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am62x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am62x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include:: ../ti/am62x_sk.rst
+:start-after: .. am62x_evm_rst_include_start_build_steps
+:end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from an uSD on a GP device simply copy the following artifacts to the
+FAT partition:
+
+* tiboot3-am62x-gp-phycore-som.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Boot
+
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+Further Information
+---
+
+Please see :doc:`../ti/am62x_sk` chapter for further AM62 SoC related
documentation
+and https://docs.phytec.com/phycore-am62x for vendor documentation.
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index a127215ce5..435c72a428 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -33,6 +33,7 @@ K3 Based SoCs
am62ax_sk
am62x_sk
../beagle/am62x_beagleplay
+ ../phytec/phycor
[PATCH v2 0/2] *** Add support for phyCORE-AM62x ***
As requested by Dhruva, this patch set comes now with a cover-letter :). This is a rebase on top of -next to address recent K3 updates. It should be noted that the huge files are generated or copy pasted from TI's evm. So I do not think they need big attention in the review process. - All yaml files are identical to TI's evm - k3-am62-phycore-som-ddr4-2gb.dtsi generated with TI's SysConfig DDR Tool - k3-am62-phycore-som.dtsi & k3-am625-phyboard-lyra-rdk.dts are 1:1 copies from Linux v6.7-rc3 v2: - Add cover-letter & mention Linux version I took the DTs from - Move board selection to mach-k3 - Add missing SPL_LDSCRIPT definition - Refactore binman file for templated FITs & drop key overrides - Drop SoC provided bootph params from dt files Note: Later we can drop more bootph params after we added them to Linux - Drop CONFIG_TI_SECURE_DEVICE as it is set as default for K3 - Drop cpsw3g custom DT property 'mac_efuse' and custom DT node cpsw-phy-sel as driver picks these from standard property/node (-u-boot.dtsi) - Add a53 cluster power to control from the rproc driver (a53 dt node) v1: https://lists.denx.de/pipermail/u-boot/2023-October/535750.html Wadim Egorov (2): board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM doc: board: phytec: Add phyCORE-AM62x arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi | 2190 + arch/arm/dts/k3-am62-phycore-som.dtsi | 324 +++ .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 166 ++ arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 ++ arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 380 +++ arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 118 + arch/arm/mach-k3/am62x/Kconfig| 17 + board/phytec/phycore_am62x/Kconfig| 33 + board/phytec/phycore_am62x/MAINTAINERS| 15 + board/phytec/phycore_am62x/Makefile |8 + board/phytec/phycore_am62x/board-cfg.yaml | 36 + board/phytec/phycore_am62x/phycore-am62x.c| 59 + board/phytec/phycore_am62x/phycore_am62x.env | 23 + board/phytec/phycore_am62x/pm-cfg.yaml| 12 + board/phytec/phycore_am62x/rm-cfg.yaml| 1088 board/phytec/phycore_am62x/sec-cfg.yaml | 379 +++ configs/phycore_am62x_a53_defconfig | 115 + configs/phycore_am62x_r5_defconfig| 130 + doc/board/phytec/index.rst|1 + doc/board/phytec/phycore-am62x.rst| 125 + doc/board/ti/k3.rst |1 + include/configs/phycore_am62x.h | 15 + 23 files changed, 5504 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts create mode 100644 arch/arm/dts/k3-am625-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62x/Kconfig create mode 100644 board/phytec/phycore_am62x/MAINTAINERS create mode 100644 board/phytec/phycore_am62x/Makefile create mode 100644 board/phytec/phycore_am62x/board-cfg.yaml create mode 100644 board/phytec/phycore_am62x/phycore-am62x.c create mode 100644 board/phytec/phycore_am62x/phycore_am62x.env create mode 100644 board/phytec/phycore_am62x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/sec-cfg.yaml create mode 100644 configs/phycore_am62x_a53_defconfig create mode 100644 configs/phycore_am62x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am62x.rst create mode 100644 include/configs/phycore_am62x.h -- 2.34.1
Re: [PATCH 1/2] board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM
Am 02.11.23 um 00:21 schrieb Tom Rini: On Wed, Nov 01, 2023 at 07:23:24PM +0100, Wadim Egorov wrote: Hi Dhruva, Am 01.11.23 um 16:57 schrieb Dhruva Gole: Hi, On Oct 31, 2023 at 14:37:31 +0100, Wadim Egorov wrote: Add basic support for PHYTEC phyCORE-AM62x SoM. Supported features: - 2GB DDR4 RAM - eMMC Flash - OSPI NOR Flash - external uSD - Ethernet - debug UART Product page SoM: https://www.phytec.com/product/phycore-am62x Signed-off-by: Wadim Egorov --- arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi | 2190 + arch/arm/dts/k3-am62-phycore-som.dtsi | 324 +++ .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 229 ++ arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 ++ arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 532 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 134 + arch/arm/mach-k3/Kconfig |1 + board/phytec/phycore_am62x/Kconfig| 52 + board/phytec/phycore_am62x/MAINTAINERS| 15 + board/phytec/phycore_am62x/Makefile |8 + board/phytec/phycore_am62x/board-cfg.yaml | 36 + board/phytec/phycore_am62x/phycore-am62x.c| 59 + board/phytec/phycore_am62x/phycore_am62x.env | 23 + board/phytec/phycore_am62x/pm-cfg.yaml| 12 + board/phytec/phycore_am62x/rm-cfg.yaml| 1088 board/phytec/phycore_am62x/sec-cfg.yaml | 379 +++ configs/phycore_am62x_a53_defconfig | 116 + configs/phycore_am62x_r5_defconfig| 131 + include/configs/phycore_am62x.h | 15 + 20 files changed, 5613 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts create mode 100644 arch/arm/dts/k3-am625-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62x/Kconfig create mode 100644 board/phytec/phycore_am62x/MAINTAINERS create mode 100644 board/phytec/phycore_am62x/Makefile create mode 100644 board/phytec/phycore_am62x/board-cfg.yaml create mode 100644 board/phytec/phycore_am62x/phycore-am62x.c create mode 100644 board/phytec/phycore_am62x/phycore_am62x.env create mode 100644 board/phytec/phycore_am62x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/sec-cfg.yaml create mode 100644 configs/phycore_am62x_a53_defconfig create mode 100644 configs/phycore_am62x_r5_defconfig create mode 100644 include/configs/phycore_am62x.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 55aceb51cd..8b371266dc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1383,7 +1383,9 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-beagleplay.dtb \ k3-am625-r5-beagleplay.dtb \ k3-am625-verdin-wifi-dev.dtb \ - k3-am625-verdin-r5.dtb + k3-am625-verdin-r5.dtb \ + k3-am625-phyboard-lyra-rdk.dtb \ + k3-am625-r5-phycore-som-2gb.dtb Thanks for upstreaming Wadim! However I would prefer that you split all these patches into smaller chunks for each file (preferrably) or group together files that have like 20-30 lines of changes. Hm, seems to be difficult and not really reasonable to split like that. The big files are generated files or copy pasted from TI's evm. So I do not think they need a big attention in the review process. - All yaml files are identical to TI's evm - k3-am62-phycore-som-ddr4-2gb.dtsi generated with TI's SysConfig DDR Tool - k3-am62-phycore-som.dtsi & k3-am625-phyboard-lyra-rdk.dts are 1:1 copies from vanilla Linux tree The rest is pretty small and reviewable IMO. I agree, I should have created a cover letter. I can do that in the next series. Please let me know if you still want me to split it into more patches. But it would be nice if you could tell me how to split it exactly without ending up with broken pieces. Yes, I don't see the value in splitting this up further, but we do need to note where the upstream dts files are synced from. Took the devicetrees from linux v6.6-rc7. I can mention that in the commit message in a v2.
Re: [PATCH 1/2] board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM
Hi Dhruva, Am 01.11.23 um 16:57 schrieb Dhruva Gole: Hi, On Oct 31, 2023 at 14:37:31 +0100, Wadim Egorov wrote: Add basic support for PHYTEC phyCORE-AM62x SoM. Supported features: - 2GB DDR4 RAM - eMMC Flash - OSPI NOR Flash - external uSD - Ethernet - debug UART Product page SoM: https://www.phytec.com/product/phycore-am62x Signed-off-by: Wadim Egorov --- arch/arm/dts/Makefile |4 +- .../arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi | 2190 + arch/arm/dts/k3-am62-phycore-som.dtsi | 324 +++ .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 229 ++ arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 ++ arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 532 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 134 + arch/arm/mach-k3/Kconfig |1 + board/phytec/phycore_am62x/Kconfig| 52 + board/phytec/phycore_am62x/MAINTAINERS| 15 + board/phytec/phycore_am62x/Makefile |8 + board/phytec/phycore_am62x/board-cfg.yaml | 36 + board/phytec/phycore_am62x/phycore-am62x.c| 59 + board/phytec/phycore_am62x/phycore_am62x.env | 23 + board/phytec/phycore_am62x/pm-cfg.yaml| 12 + board/phytec/phycore_am62x/rm-cfg.yaml| 1088 board/phytec/phycore_am62x/sec-cfg.yaml | 379 +++ configs/phycore_am62x_a53_defconfig | 116 + configs/phycore_am62x_r5_defconfig| 131 + include/configs/phycore_am62x.h | 15 + 20 files changed, 5613 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts create mode 100644 arch/arm/dts/k3-am625-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62x/Kconfig create mode 100644 board/phytec/phycore_am62x/MAINTAINERS create mode 100644 board/phytec/phycore_am62x/Makefile create mode 100644 board/phytec/phycore_am62x/board-cfg.yaml create mode 100644 board/phytec/phycore_am62x/phycore-am62x.c create mode 100644 board/phytec/phycore_am62x/phycore_am62x.env create mode 100644 board/phytec/phycore_am62x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/sec-cfg.yaml create mode 100644 configs/phycore_am62x_a53_defconfig create mode 100644 configs/phycore_am62x_r5_defconfig create mode 100644 include/configs/phycore_am62x.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 55aceb51cd..8b371266dc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1383,7 +1383,9 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-beagleplay.dtb \ k3-am625-r5-beagleplay.dtb \ k3-am625-verdin-wifi-dev.dtb \ - k3-am625-verdin-r5.dtb + k3-am625-verdin-r5.dtb \ + k3-am625-phyboard-lyra-rdk.dtb \ + k3-am625-r5-phycore-som-2gb.dtb Thanks for upstreaming Wadim! However I would prefer that you split all these patches into smaller chunks for each file (preferrably) or group together files that have like 20-30 lines of changes. Hm, seems to be difficult and not really reasonable to split like that. The big files are generated files or copy pasted from TI's evm. So I do not think they need a big attention in the review process. - All yaml files are identical to TI's evm - k3-am62-phycore-som-ddr4-2gb.dtsi generated with TI's SysConfig DDR Tool - k3-am62-phycore-som.dtsi & k3-am625-phyboard-lyra-rdk.dts are 1:1 copies from vanilla Linux tree The rest is pretty small and reviewable IMO. I agree, I should have created a cover letter. I can do that in the next series. Please let me know if you still want me to split it into more patches. But it would be nice if you could tell me how to split it exactly without ending up with broken pieces. Regards, Wadim It's difficult to review thousands of lines of code at once, hope you understand. Also would appreciate it if you sent the series with a cover letter summarising your changes. You can also attach boot logs or any additional info you may want the people reviewing/ testing the patches to know in the cover letter. dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \ k3-am62a7-r5-sk.dtb [..snip..]
[PATCH 2/2] doc: board: phytec: Add phyCORE-AM62x
Add documentation for PHYTEC phyCORE-AM62x SoM.
Signed-off-by: Wadim Egorov
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am62x.rst | 125 +
doc/board/ti/k3.rst| 1 +
3 files changed, 127 insertions(+)
create mode 100644 doc/board/phytec/phycore-am62x.rst
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index a5b442045e..b914cc3fbd 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -6,5 +6,6 @@ PHYTEC
.. toctree::
:maxdepth: 2
+ phycore-am62x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am62x.rst
b/doc/board/phytec/phycore-am62x.rst
new file mode 100644
index 00..46312a73bc
--- /dev/null
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -0,0 +1,125 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov
+
+phyCORE-AM62x
+=
+
+The `phyCORE-AM62x <https://www.phytec.com/product/phycore-am62x>`_ is a
+SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family.
+
+A development Kit, called `phyBOARD-Lyra
<https://www.phytec.com/product/phyboard-am62x>`_
+is used as a carrier board reference design around the AM62x SoM.
+
+Quickstart
+--
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+---
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_boot_sources
+:end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_desc
+:end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_board_env_vars_desc
+:end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+:start-after: .. k3_rst_include_start_common_env_vars_defn
+:end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am62x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am62x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include:: ../ti/am62x_sk.rst
+:start-after: .. am62x_evm_rst_include_start_build_steps
+:end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from an uSD on a GP device simply copy the following artifacts to the
+FAT partition:
+
+* tiboot3-am62x-gp-phycore-som.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Boot
+
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+Further Information
+---
+
+Please see :doc:`../ti/am62x_sk` chapter for further AM62 SoC related
documentation
+and https://docs.phytec.com/phycore-am62x for vendor documentation.
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 89d70db886..f659398200 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -32,6 +32,7 @@ K3 Based SoCs
am62x_beagleplay
am62x_sk
+ ../phytec/phycore-am62x
../toradex/verdin-am62
am64x_evm
am65x_evm
--
2.34.1
Re: [PATCH] serial: ns16550: Enable clocks during probe
Hi Stefan, Am 13.12.22 um 07:14 schrieb Stefan Roese: > Hi Samuel, > > On 12/13/22 02:46, Samuel Holland wrote: >> On 12/12/22 12:54, Tom Rini wrote: >>> On Sun, Nov 27, 2022 at 11:48:34PM -0600, Samuel Holland wrote: >>> If the UART bus or baud clock has a gate, it must be enabled before the UART can be used. Signed-off-by: Samuel Holland Reviewed-by: Stefan Roese >>> >>> This breaks building on phycore-rk3288 >> >> I get: >> >> binman: Error 1 running 'mkimage -d ./mkimage.simple-bin.mkimage -n >> rk3288 -T rksd ./idbloader.img': Error: SPL image is too large (size >> 0x8800 than 0x8000) >> >> Before applying this patch: >> >> $ ls -l spl/u-boot-spl.bin >> -rw-r--r-- 1 samuel samuel 32704 Dec 12 19:35 spl/u-boot-spl.bin >> >> So the board was quite close to its SPL size limit already. >> >> I was trying to be general with this patch, but I suppose for my >> immediate purposes (Allwinner D1), I only care about the first clock. If >> I use clk_get_by_index() instead of clk_get_bulk(), the phycore-rk3288 >> build passes with 4 bytes to spare: >> >> $ ls -l spl/u-boot-spl.bin >> -rw-r--r-- 1 samuel samuel 32760 Dec 12 19:36 spl/u-boot-spl.bin >> >> I will send a v2, but I imagine some other unsuspecting patch will run >> into this limit again before long. > > Why not enable LTO to save more space. I just checked this on this > platform: > > w/o LTO: > spl/u-boot-spl.bin 32604 > > with LTO enabled: > spl/u-boot-spl.bin 30016 > > Not tested though. Thanks for the hint with the LTO. I just send out a patch to enable it for the phycore-rk3288 https://lists.denx.de/pipermail/u-boot/2022-December/502125.html Regards, Wadim > > Thanks, > Stefan
[PATCH] configs: phycore-rk3288: Enable CONFIG_LTO
The phycore-rk3288 SPL binary is reaching the limits of 32KB very often. Enable CONFIG_LTO to reduce the size of the SPL and make the board more future proof for changes increasing the SPL size. Signed-off-by: Wadim Egorov --- configs/phycore-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 8a274187d0..aa015c5502 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_UART_BASE=0xff69 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_LTO=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10 CONFIG_SYS_MONITOR_LEN=614400 -- 2.34.1
Re: [PATCH v1] rockchip: phycore_rk3288: remove phycore_init() function
Am 19.10.22 um 00:35 schrieb Johan Jonker:
>
> On 10/18/22 13:43, Wadim Egorov wrote:
>> Hi Johan,
>>
>> thanks for this Patch. You were faster with the patch.
>>
>> I hope the size reduction is enough to make it buildable with Kevers patch.
> This patch only reduces the SPL size a few hundred bytes.
> U-boot tend to grow over time.
Yes, I noticed. This discussion is coming up often.
> To be future proof your SPL > TPL size must be significantly reduced (>kB)
> below this limit.
In other words this sounds like you are forcing RK3288 towards TPL. Is that the
case?
But if I take a look at other RK3288 based boards, I can see that most boards
do
not select TPL.
As the "special" phyCORE-RK3288 SPL setup code is gone with this patch, our
board now looks very similar to others from an SPL perspective.
With this fact, other non TPL RK3288 boards should have exactly the same size
issue. How is this handled for them?
> Only someone with hardware can check that.
> People with a recent DT are unable to sync from Linux, because of inactive
> board maintainers.
> Could you indicate if Phytec is interested to take up that task?
At the moment the RK3288 board is not in my focus a lot. I am not able to run
u-boot/master tests regularly.
But I would like to keep the phyCORE-RK3288 in u-boot.
So it would be very helpful if you could clarify the future plan for SPLs on
RK3288 SoCs.
After that I can take action to make the board more future proof (Switch to TPL
or other things to reduce size).
Regards,
Wadim
>
> Johan
>
>
>>
>> Am 18.10.22 um 13:25 schrieb Johan Jonker:
>>> The phycore_rk3288 board has a SPL size problem,
>>> so remove phycore_init() function to stay within the limits.
>>>
>>> Signed-off-by: Johan Jonker
>> Reviewed-by: Wadim Egorov
>>
>>
>>> ---
>>>arch/arm/mach-rockchip/rk3288/Kconfig| 1 -
>>>board/phytec/phycore_rk3288/phycore-rk3288.c | 46
>>>2 files changed, 47 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig
>>> b/arch/arm/mach-rockchip/rk3288/Kconfig
>>> index e8c57843..1be2b585 100644
>>> --- a/arch/arm/mach-rockchip/rk3288/Kconfig
>>> +++ b/arch/arm/mach-rockchip/rk3288/Kconfig
>>> @@ -89,7 +89,6 @@ config TARGET_MIQI_RK3288
>>>config TARGET_PHYCORE_RK3288
>>> bool "phyCORE-RK3288"
>>>select BOARD_LATE_INIT
>>> - select SPL_BOARD_INIT if SPL
>>> help
>>> Add basic support for the PCM-947 carrier board, a RK3288 based
>>> development board made by PHYTEC. This board works in a combination
>>> diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c
>>> b/board/phytec/phycore_rk3288/phycore-rk3288.c
>>> index 17b987f6..3f49f39e 100644
>>> --- a/board/phytec/phycore_rk3288/phycore-rk3288.c
>>> +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
>>> @@ -19,8 +19,6 @@
>>>#include
>>>#include
>>>#include "som.h"
>>> -#include
>>> -#include
>>>
>>>static int valid_rk3288_som(struct rk3288_som *som)
>>>{
>>> @@ -77,47 +75,3 @@ int rk3288_board_late_init(void)
>>>
>>> return 0;
>>>}
>>> -
>>> -#ifdef CONFIG_SPL_BUILD
>>> -#if !defined(CONFIG_SPL_OF_PLATDATA)
>>> -static int phycore_init(void)
>>> -{
>>> - struct udevice *pmic;
>>> - int ret;
>>> -
>>> - ret = uclass_first_device_err(UCLASS_PMIC, );
>>> - if (ret)
>>> - return ret;
>>> -
>>> -#if defined(CONFIG_SPL_POWER)
>>> - /* Increase USB input current to 2A */
>>> - ret = rk818_spl_configure_usb_input_current(pmic, 2000);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - /* Close charger when USB lower then 3.26V */
>>> - ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 326);
>>> - if (ret)
>>> - return ret;
>>> -#endif
>>> -
>>> - return 0;
>>> -}
>>> -#endif
>>> -
>>> -void spl_board_init(void)
>>> -{
>>> -#if !defined(CONFIG_SPL_OF_PLATDATA)
>>> - int ret;
>>> -
>>> - if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
>>> - ret = phycore_init();
>>> - if (ret) {
>>> - debug("Failed to set up phycore power settings: %d\n",
>>> - ret);
>>> - return;
>>> - }
>>> - }
>>> -#endif
>>> -}
>>> -#endif
>>
Re: [PATCH v1] rockchip: phycore_rk3288: remove phycore_init() function
Hi Johan,
thanks for this Patch. You were faster with the patch.
I hope the size reduction is enough to make it buildable with Kevers patch.
Am 18.10.22 um 13:25 schrieb Johan Jonker:
> The phycore_rk3288 board has a SPL size problem,
> so remove phycore_init() function to stay within the limits.
>
> Signed-off-by: Johan Jonker
Reviewed-by: Wadim Egorov
> ---
> arch/arm/mach-rockchip/rk3288/Kconfig| 1 -
> board/phytec/phycore_rk3288/phycore-rk3288.c | 46
> 2 files changed, 47 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig
> b/arch/arm/mach-rockchip/rk3288/Kconfig
> index e8c57843..1be2b585 100644
> --- a/arch/arm/mach-rockchip/rk3288/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3288/Kconfig
> @@ -89,7 +89,6 @@ config TARGET_MIQI_RK3288
> config TARGET_PHYCORE_RK3288
> bool "phyCORE-RK3288"
> select BOARD_LATE_INIT
> - select SPL_BOARD_INIT if SPL
> help
> Add basic support for the PCM-947 carrier board, a RK3288 based
> development board made by PHYTEC. This board works in a combination
> diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c
> b/board/phytec/phycore_rk3288/phycore-rk3288.c
> index 17b987f6..3f49f39e 100644
> --- a/board/phytec/phycore_rk3288/phycore-rk3288.c
> +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
> @@ -19,8 +19,6 @@
> #include
> #include
> #include "som.h"
> -#include
> -#include
>
> static int valid_rk3288_som(struct rk3288_som *som)
> {
> @@ -77,47 +75,3 @@ int rk3288_board_late_init(void)
>
> return 0;
> }
> -
> -#ifdef CONFIG_SPL_BUILD
> -#if !defined(CONFIG_SPL_OF_PLATDATA)
> -static int phycore_init(void)
> -{
> - struct udevice *pmic;
> - int ret;
> -
> - ret = uclass_first_device_err(UCLASS_PMIC, );
> - if (ret)
> - return ret;
> -
> -#if defined(CONFIG_SPL_POWER)
> - /* Increase USB input current to 2A */
> - ret = rk818_spl_configure_usb_input_current(pmic, 2000);
> - if (ret)
> - return ret;
> -
> - /* Close charger when USB lower then 3.26V */
> - ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 326);
> - if (ret)
> - return ret;
> -#endif
> -
> - return 0;
> -}
> -#endif
> -
> -void spl_board_init(void)
> -{
> -#if !defined(CONFIG_SPL_OF_PLATDATA)
> - int ret;
> -
> - if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
> - ret = phycore_init();
> - if (ret) {
> - debug("Failed to set up phycore power settings: %d\n",
> - ret);
> - return;
> - }
> - }
> -#endif
> -}
> -#endif
Re: [PATCH v6 0/6] rockchip: Add Binman support
Hi Jagan, On 09.01.20 14:59, Jagan Teki wrote: > On Wed, Jan 8, 2020 at 5:04 PM Wadim Egorov wrote: >> Hi, >> >> On 07.01.20 10:59, Kever Yang wrote: >>> Add Wadim in cc, >>> >>> Hi Jagan, >>> >>> After this patch set apply, the phycore-rk3288 board's SPL size is >>> overflow: >>> >>>arm: + phycore-rk3288 >>> +Error: SPL image is too large (size 0x9000 than 0x8000) >>> +Error: Bad parameters for image type >>> >>> Maybe we need to enable the TPL for this board? @Wadim >> I would like it to keep the SPL for the phyCORE board. In this thread >> [1] I pointed out that you can drop the phycore_init() function that was >> sometimes blowing up the size of the phyCORE SPL image. So if there is >> no new other feature that increases the SPL size, we can just remove the >> code and the SPL should fit again. If you like I can take a look at this >> next week. > This won't help much, but one possibility is to use SPL_OF_PLATDATA > (I've verified). Can you help us to try as quickly as possible? or do > you want us to try? Or we can simply disable CONFIG_SPL_I2C_SUPPORT and CONFIG_SPL_POWER_SUPPORT in the phycore-rk3288_defconfig. What do you want me to do now? Testing your patches with SPL_OF_PLATDATA=y on our board? If so, I can help you next week with testing.
Re: [PATCH v6 0/6] rockchip: Add Binman support
Hi, On 07.01.20 10:59, Kever Yang wrote: > Add Wadim in cc, > > Hi Jagan, > > After this patch set apply, the phycore-rk3288 board's SPL size is > overflow: > > arm: + phycore-rk3288 > +Error: SPL image is too large (size 0x9000 than 0x8000) > +Error: Bad parameters for image type > > Maybe we need to enable the TPL for this board? @Wadim I would like it to keep the SPL for the phyCORE board. In this thread [1] I pointed out that you can drop the phycore_init() function that was sometimes blowing up the size of the phyCORE SPL image. So if there is no new other feature that increases the SPL size, we can just remove the code and the SPL should fit again. If you like I can take a look at this next week. [1] https://lists.denx.de/pipermail/u-boot/2019-July/378112.html Regards, Wadim > > > Thanks, > > - Kever > > On 2020/1/4 下午4:38, Jagan Teki wrote: >> This is v6 set for Binman support in rockchip, [1] here is >> previous patchset. >> >> This series add single boot image with binman for arm32 and >> pad_cat for arm64 rockchip platforms both TPL + SPL and SPL-alone >> targets. >> >> Changes for v6: >> - drop idbloader.img filename change patch >> - update rockchip.rst to include, rockchip TPL, SPI boot as TODO >> Changes for v5: >> - collect kever review tag >> - drop idbloader.img from clean target >> Changes for v4: >> - support all rockchip platforms >> - add new patches for dtsi changes >> - update documentation >> - format proper commit message >> - rebase on master >> Changes for v3: >> - rebase on master >> - add binman for rk3288, rk3328, rk3368, rk3399 >> - added rst documentation for rockchip >> Changes for v2: >> - Add few clean target patches >> - update bl31.elf env handling code, with logging >> - support puma itb, via BL31 and PMUM0 env >> - enable BUILD_TARGET for ROCKCHIP_RK3399 >> >> [1] https://patchwork.ozlabs.org/cover/1216263/ >> >> Any inputs? >> Jagan. >> >> Jagan Teki (6): >> Makefile: Add rockchip image type >> Makefile: rockchip: Suffix platform type with tpl name >> Makefile: rockchip: Support SPL-alone mkimage >> arm: dts: rk3036: Add rk3036-u-boot.dtsi >> rockchip: Add Single boot image (with binman, pad_cat) >> doc: boards: Add rockchip documentation >> >> Makefile | 36 ++-- >> arch/arm/Kconfig | 1 + >> arch/arm/dts/rk3036-sdk-u-boot.dtsi | 2 + >> arch/arm/dts/rk3036-u-boot.dtsi | 6 ++ >> arch/arm/dts/rk3288-u-boot.dtsi | 2 + >> arch/arm/dts/rockchip-u-boot.dtsi | 21 + >> doc/board/rockchip/index.rst | 10 +++ >> doc/board/rockchip/rockchip.rst | 130 >> include/configs/rockchip-common.h | 3 + >> 9 files changed, 206 insertions(+), 5 deletions(-) >> create mode 100644 arch/arm/dts/rk3036-u-boot.dtsi >> create mode 100644 arch/arm/dts/rockchip-u-boot.dtsi >> create mode 100644 doc/board/rockchip/index.rst >> create mode 100644 doc/board/rockchip/rockchip.rst >> > >
Re: [U-Boot] [PATCH 03/15] rockchip: rk3288: Print reset reason
On 14.08.19 11:40, Jagan Teki wrote:
> On Mon, Aug 5, 2019 at 6:00 PM Kever Yang wrote:
>>
>> On 2019/7/29 下午3:46, Jagan Teki wrote:
>>> Print the reason for reset instead of storing it into
>>> env variable in rk3288.
>>>
>>> This would help to find the reset reason directly
>>> on U-Boot proper logs.
>>>
>>> Cc: Wadim Egorov
>>> Signed-off-by: Jagan Teki
>>> ---
>>> arch/arm/mach-rockchip/rk3288-board.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-rockchip/rk3288-board.c
>>> b/arch/arm/mach-rockchip/rk3288-board.c
>>> index d3ec141fea..613264d7ee 100644
>>> --- a/arch/arm/mach-rockchip/rk3288-board.c
>>> +++ b/arch/arm/mach-rockchip/rk3288-board.c
>>> @@ -72,7 +72,7 @@ static void rk3288_detect_reset_reason(void)
>>> reason = "unknown reset";
>>> }
>>>
>>> - env_set("reset_reason", reason);
>>> + printf("Reset cause: %s\n", reason);
>>
>> Why this need to set as env before? I didn't touch this code when I migrate
> Don't know the proper reason for this, ie why I have CCed Wadim.
>
> Wadim, any comments?
If we put the reset_reason inside an environment variable we can later
reuse it from a script, e.g. changing the boot behavior for special
cases. Right now I have no usecase for it. So from my side you can just
print the reason instead of setting the environment. AFAIR I copied the
env-method from another board.
btw, board/xilinx/zynqmp/zynqmp.c is doing both.
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Re: [U-Boot] [PATCH 18/35] rockchip: rk3288-phycore: move phycore_init() to its own board file
Hi Kever,
this is fine for me. You can drop the phycore_init() code completely. No
need to carry this around in our board code.
The SOM was redesigned and is equipped with an STM8 connected to the
RK818. The required setup we did before in the SPL is now done by the ST
controller. I know there are only a few SOMs without the STM8 out in the
wild. So if you remove it it will affect only a few people who probably
already have both boards.
Thanks,
Wadim
On 22.07.19 13:59, Kever Yang wrote:
> phycore_init() is use for phycore board only, it should be move back
> to phycore-rk3288.c
>
> Signed-off-by: Kever Yang
> ---
>
> arch/arm/mach-rockchip/rk3288-board-spl.c| 39
> arch/arm/mach-rockchip/rk3288/Kconfig| 1 +
> board/phytec/phycore_rk3288/phycore-rk3288.c | 47
> 3 files changed, 48 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> index 6db5369a10..13cd86079b 100644
> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> @@ -25,8 +25,6 @@
> #include
> #include
> #include
> -#include
> -#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -81,32 +79,6 @@ fallback:
> return BOOT_DEVICE_MMC1;
> }
>
> -#if !defined(CONFIG_SPL_OF_PLATDATA)
> -static int phycore_init(void)
> -{
> - struct udevice *pmic;
> - int ret;
> -
> - ret = uclass_first_device_err(UCLASS_PMIC, );
> - if (ret)
> - return ret;
> -
> -#if defined(CONFIG_SPL_POWER_SUPPORT)
> - /* Increase USB input current to 2A */
> - ret = rk818_spl_configure_usb_input_current(pmic, 2000);
> - if (ret)
> - return ret;
> -
> - /* Close charger when USB lower then 3.26V */
> - ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 326);
> - if (ret)
> - return ret;
> -#endif
> -
> - return 0;
> -}
> -#endif
> -
> __weak int arch_cpu_init(void)
> {
> return 0;
> @@ -175,17 +147,6 @@ void board_init_f(ulong dummy)
> return;
> }
>
> -#if !defined(CONFIG_SPL_OF_PLATDATA)
> - if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
> - ret = phycore_init();
> - if (ret) {
> - debug("Failed to set up phycore power settings: %d\n",
> - ret);
> - return;
> - }
> - }
> -#endif
> -
> #if !defined(CONFIG_SUPPORT_TPL)
> debug("\nspl:init dram\n");
> ret = uclass_get_device(UCLASS_RAM, 0, );
> diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig
> b/arch/arm/mach-rockchip/rk3288/Kconfig
> index 6e3ab1d06b..87d0786ba8 100644
> --- a/arch/arm/mach-rockchip/rk3288/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3288/Kconfig
> @@ -85,6 +85,7 @@ config TARGET_MIQI_RK3288
> config TARGET_PHYCORE_RK3288
> bool "phyCORE-RK3288"
> select BOARD_LATE_INIT
> + select SPL_BOARD_INIT if SPL
> help
> Add basic support for the PCM-947 carrier board, a RK3288 based
> development board made by PHYTEC. This board works in a combination
> diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c
> b/board/phytec/phycore_rk3288/phycore-rk3288.c
> index ffe1833b06..fbf1511978 100644
> --- a/board/phytec/phycore_rk3288/phycore-rk3288.c
> +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
> @@ -8,10 +8,13 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> #include "som.h"
> +#include
> +#include
>
> static int valid_rk3288_som(struct rk3288_som *som)
> {
> @@ -68,3 +71,47 @@ int rk_board_late_init(void)
>
> return 0;
> }
> +
> +#ifdef CONFIG_SPL_BUILD
> +#if !defined(CONFIG_SPL_OF_PLATDATA)
> +static int phycore_init(void)
> +{
> + struct udevice *pmic;
> + int ret;
> +
> + ret = uclass_first_device_err(UCLASS_PMIC, );
> + if (ret)
> + return ret;
> +
> +#if defined(CONFIG_SPL_POWER_SUPPORT)
> + /* Increase USB input current to 2A */
> + ret = rk818_spl_configure_usb_input_current(pmic, 2000);
> + if (ret)
> + return ret;
> +
> + /* Close charger when USB lower then 3.26V */
> + ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 326);
> + if (ret)
> + return ret;
> +#endif
> +
> + return 0;
> +}
> +#endif
> +
> +void spl_board_init(void)
> +{
> +#if !defined(CONFIG_SPL_OF_PLATDATA)
> + int ret;
> +
> + if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
> + ret = phycore_init();
> + if (ret) {
> + debug("Failed to set up phycore power settings: %d\n",
> + ret);
> + return;
> + }
> + }
> +#endif
> +}
> +#endif
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Re: [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
On 07.05.19 16:43, Niel Fourie wrote:
> Hi Tom,
>
> On 5/7/19 3:19 PM, Tom Rini wrote:
>> On Tue, May 07, 2019 at 11:39:12AM +0200, Niel Fourie wrote:
>>> Hi Tom,
>>>
>>> On 5/6/19 7:24 PM, Tom Rini wrote:
On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
> Hi Tom,
>
> On 5/6/19 4:18 PM, Tom Rini wrote:
>> On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
>>
>>> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
>>> phyBOARD-Wega AM335x.
>>>
>>> CPU : AM335X-GP rev 2.1
>>> Model: Phytec AM335x phyBOARD-WEGA
>>> DRAM: 256 MiB
>>> NAND: 256 MiB
>>> MMC: OMAP SD/MMC: 0
>>> eth0: ethernet@4a10
>>>
>>> Working:
>>> - Eth0
>>> - i2C
>>> - MMC/SD
>>> - NAND
>>> - UART
>>> - USB (host)
>>>
>>> Device trees were taken from Linux mainline:
>>> commit 37624b58542f ("Linux 5.1-rc7")
>>>
>>> Signed-off-by: Niel Fourie
>>> [snip]
>
> void sdram_init(void)
> {
> /* Configure memory to maximum supported size for detection */
> int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> config_ddr(DDR_CLK_MHZ, ,
> _timings[ram_type_index].ddr3_data,
> _cmd_ctrl_data,
> _timings[ram_type_index].ddr3_emif_reg_data,
> 0);
>
> /* Detect memory physically present */
> gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
> CONFIG_MAX_RAM_BANK_SIZE);
>
> /* Reconfigure memory for actual detected size */
> switch (gd->ram_size) {
> case SZ_1G:
> ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> break;
> case SZ_512M:
> ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
> break;
> case SZ_256M:
> default:
> ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> break;
> }
> config_ddr(DDR_CLK_MHZ, ,
> _timings[ram_type_index].ddr3_data,
> _cmd_ctrl_data,
> _timings[ram_type_index].ddr3_emif_reg_data,
> 0);
> }
>
> The ugliest part of this is, as you pointed out, that directly
> after this is
> called, get_ram_size() will be called again from sdram_init(). But
> it at
> least noninvasive, and no longer requires the device tree.
I don't think it's safe to call config_ddr twice, especially with the
possibly wrong parameters. What's barebox doing in this case, being
told the presumably correct DDR size in the device tree?
>>>
>>> Good point. Barebox uses the above mechanism to detect the memory
>>> size, and
>>> I could find no equivalent memory size specified in its internal device
>>> tree.
>>
>> Configure for 1GB and then see how much we can actually talk to?
>
> Yes. If you are interested, you can see their implementation here [1],
> where get_minimal_timings() returns the configuration for 1GiB;
> everything is in that file. (I did credit the author.)
>
> [1]
> https://git.pengutronix.de/cgit/barebox/tree/arch/arm/boards/phytec-som-am335x/lowlevel.c#n167
>
>>> Marek originally proposed using the memory size specified in the
>>> device tree
>>> as an improvement over specifying the size in the defconfig (as in
>>> v1 of the
>>> patch).
>>
>> But then you aren't populating 3 device trees nor making it clear / easy
>> to say which module you're on, and then still need to change the config
>> for which DT you're picking up. These SOMs really don't provide any
>> run-time method to see which one you're on? There's no GPIOs to poke?
>
> Agreed, the device tree solution is inferior to autodetection. The
> SOMs manual makes no mention of how different variants can be
> distinguished/detected, and the board specific code in Barebox
> (written by Phytec) does not contain any other detection code (except
> for the RAM), like checking GPIOs. Unfortunately there is no publicly
> available schematic, so I can't be completely sure. So I am going to
> assume it, there is no other way of detection.
You are right, for our AM335 based SOMs there is no way to detect the
variant. The barebox generates for every possible RAM configuration an
own MLO. The nice thing is that barebox generates all variants with one
build by using its multi image mechanism.
Besides the RAM, the phyCORE can be populated with different AM335x
variants, NANDs, RTC/EEPROM/Eth-PHY(yes/no) and maybe other things I
don't remember now.
I think it would be a good Idea to maintain a list of article numbers
(that fully describes the SOM variant) which are supported by the
current u-boot version.
Regards,
Wadim
>
> Best regards,
> Niel Fourie
>
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Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060
Hi, On 19.04.19 17:20, Marek Vasut wrote: > On 4/19/19 5:06 PM, Parthiban Nallathambi wrote: >> Hello Marek, >> >> On 4/19/19 3:35 PM, Marek Vasut wrote: >>> On 4/19/19 3:18 PM, Parthiban Nallathambi wrote: >>> >>> Hi, >>> >>> [...] >>> >> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig >> index d29f1ca0b5..9336439340 100644 >> --- a/arch/arm/mach-omap2/Kconfig >> +++ b/arch/arm/mach-omap2/Kconfig >> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig" >> source "board/ti/am335x/Kconfig" >> source "board/compulab/cm_t335/Kconfig" >> source "board/compulab/cm_t43/Kconfig" >> +source "board/phytec/phycore_pcl060/Kconfig" > Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ? > > [1] > https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/ > [...] This differs only by the connector. PCM variants are pluggable and PCL variants are direct soliderable to the carrier board. Copied from [1]: The PCL-060 System On Module is a connector-less, BGA style variant of the PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that support high density connectors, the PCL-060 SOM is directly soldered down to the phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). This solution offers an ultra-low cost Single Board Computer for the AM335x processor, while maintaining most of the advantages of the SOM concept. [1] https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf >>> Ah damn, this looks like a consistency problem is coming up. We have >>> multiple PCM* SoMs in U-Boot, one PCL* SoM and now another PCL/PCM SoM. >>> But the PCL063 isn't even manufactured in variant with connectors, so I >>> guess we can ignore that one. >>> >>> I wonder whether we should stick to PCM* for all of the Phytec SoMs for >>> consistency sake and document that PCL060 is also supported or maybe >>> there's a better way ? >> Does PCX/PCx makes sense? But we have the same problem with variscite [1] >> SoM's >> (either SODIMM or solderable). >> >> [1] https://lists.denx.de/pipermail/u-boot/2019-April/365667.html > PCX would introduce another option, in addition to PCM/PCL, one which > cannot be easily found on the internet, so I'd like to avoid that. I > am banking toward the sticking with PCM where possible (simply because > that's what $searchengine spits out first when you look for that SoM, > and because we already have plenty of PCM-nnn SoMs), but maybe someone > has a better idea . why not simply use the full name of the module instead? - phyCORE-AM335x - phyCORE-AM335x R2 I did the same for the phyCORE-RK3288. There is no real difference between a PCM and PCL SOM. You can take look at the barebox code for this modules to get some inspiration on how to handle the different SOM variants. https://git.pengutronix.de/cgit/barebox/tree/arch/arm/boards/phytec-som-am335x Regards, Wadim > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM
Martyn,
On 09.04.19 12:46, Martyn Welch wrote:
> On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
>> Hello Martyn,
>>
>> On 4/9/19 10:49 AM, Martyn Welch wrote:
>>> On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
> On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
>> diff --git a/board/phytec/pcl063/spl.c
>> b/board/phytec/pcl063/spl.c
>> index b93cd493f2..73a774645d 100644
>> --- a/board/phytec/pcl063/spl.c
>> +++ b/board/phytec/pcl063/spl.c
>> @@ -13,6 +13,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>>
>> /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x
>> 16 x 8
>> ->
>> 256MiB */
>> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
>> usdhc1_pads[] =
>> {
>> MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> };
>>
>> +#ifndef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> +MX6_PAD_NAND_RE_B__USDHC2_CLK|
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_WE_B__USDHC2_CMD|
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +#endif
>> +
> Umm, these pins are already used a few lines up for the NAND,
> via
> gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC
together. I
comes
either with eMMC or NAND.
>>> Opps, sorry, just realised that I added this comment in the wrong
>>> place. This is in relation to the following being added to
>>> pcl063-common.dtsi:
>>>
>>> +
>>> + pinctrl_usdhc2: usdhc2grp {
>>> + fsl,pins = <
>>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x1
>>> 00f9
>>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x1
>>> 70f9
>>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x1
>>> 70f9
>>> + >;
>>> + };
>>>
>>> If there exists pcl063 modules that have eMMC and others that have
>>> NAND
>>> using the same pins, then this configuration is not common and
>>> therefore shouldn't be in pcl063-common.dtsi. Is it dependent on
>>> the
>>> flavour of i.MX used? If so I'd suggest the gpmi config needs to be
>>> pulled out into imx6ul-phycore-segin.dts and the usdhc2 config
>>> needs to
>>> be in imx6ull-phycore-segin.dts.
>> From phytec I understand that pcl063 SoM is a common platform for
>> imx6UL
>> and imx6ULL. This can either be shipped with eMMC or NAND, but not
>> both.
This is correct. There are PCL-063 SOMs with eMMC or NAND. And each
PCL-063 can be a 6UL or 6ULL.
>>
> Looking a bit deeper, this seems a little odd as the product
> description suggests that NAND is provided onboard and 2 SD/SDIO/MMC
> connections are provided to the edge connector of the pcl063 for
> expansion.
>
> The schematic suggests the only way they could achieve eMMC onboard
> would be with an eMMC that is pin compatible with the NAND they use.
eMMC is connected via usdhc2. The usdhc2 pins conflict with the gpmi pins.
>
> Additionally, looking at the DTBs for this board in Phytec's own kernel
> tree, the only use of usdhc2 that I can see is for their WLAN expansion
> board[1] and I would have expected their tree to have supported such an
> option if it was available (they seem to have gone to some length to
> support a lot of configurations there).
>
> Are you sure that the eMMC is provided on the pcl063 and not off board?
eMMC is on the PCL-063 and not on a carrier board.
>
> (CCing Wadim who might be able to shed some light on this)
>
>> So there exist a possibility
[U-Boot] rk3288 SPL size
Hi, it seems the new common rockchip pinctrl driver does not really fit into our phycore-rk3288 SPL setup. It works for every other rk3288 based board because they don't need special power configurations at the SPL stage. So my question is: is there any work going on to reduce the SPL size even more? Besides that, I think I can remove the power stuff at the SPL stage from our board. The SOM was redesigned and is equipped with an STM8 connected to the RK818. The required setup we did before in the SPL is now done by the ST controller. I know there are only a few SOMs without the STM8 out in the wild. So if I remove it it will affect only a few people who probably already have both boards. Regards, Wadim ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] RK3399/RK3288 same-as-spl Option
Hi Philipp, Am 30.01.19 um 13:56 schrieb Philipp Tomsich: > Wadim, > >> On 30.01.2019, at 13:50, Wadim Egorov > <mailto:w.ego...@phytec.de>> wrote: >> >> I want to know if there is a reason why the same-as-spl boot order >> option [1] was not added for the RK3288. Do the chromebooks or other >> RK3288 based boards don't want/need this option? >> > For starters I don’t have a RK3288-based board or a Chromebook. > The code was designed to be generic enough to easily retarget to new > boards. > > It’s good to see that it’s not just our modules that face the > challenge of requiring a configurable boot-order ;-) Yes, this popped up again for me after the "eMMC/sd index distro boot order" discussion. >> It seems the RK3288 has the same Register that marks the boot source >> device: >> RK3399_BROM_BOOTSOURCE_ID_ADDR: 0xff8c0010 >> For RK3288 it is 0xff700010. I know it is not documented in the >> TRM. But it works. >> > I had asked Kever for the address (back in the day), as it was not > documented neither for the RK3368 nor for the RK3399. >> >> Any opinions in reworking the RK3288 code to use this Register for >> "same-as-spl" boot? >> > There’s a task in my to-do list to move most of the configuration in > the GRF (e.g. selecting RGMII vs. GMII) to an ioctl-based scheme. > This resulted as the “best available choice” from a prior discussion > between me an Simon. > > If you want to tackle this, I would advise a DM-based solution for > interfacing with our BootROM. Thanks, I will keep this in mind. Right know it is not that important for us. And I just wanted to know why nobody else had the idea to use the same-as-spl process before. Maybe because this Register was not known for a long time. Regards, Wadim > > Thanks, > Philipp., ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] RK3399/RK3288 same-as-spl Option
Hi, I want to know if there is a reason why the same-as-spl boot order option [1] was not added for the RK3288. Do the chromebooks or other RK3288 based boards don't want/need this option? It seems the RK3288 has the same Register that marks the boot source device: RK3399_BROM_BOOTSOURCE_ID_ADDR: 0xff8c0010 For RK3288 it is 0xff700010. I know it is not documented in the TRM. But it works. Any opinions in reworking the RK3288 code to use this Register for "same-as-spl" boot? [1] https://patchwork.ozlabs.org/cover/812927/ Regards, Wadim ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESENT PATCH v3] rockchip: update emmc/sd index for distro boot order
Hi Kever, Am 30.11.18 um 02:27 schrieb Kever Yang: > + Andreas from SUSE and Thomas from Armbian > > Hi Wadim, > > > On 11/29/2018 05:54 PM, Wadim Egorov wrote: >> Hi, >> >> Am 29.11.18 um 02:48 schrieb Kever Yang: >>> On 11/28/2018 05:15 PM, Philipp Tomsich wrote: >>>> Kever, >>>> >>>>> On 28.11.2018, at 03:06, Kever Yang wrote: >>>>> >>>>> According to the emmc/sdcard index in dts alias, emmc is always 0 and >>>>> sdcard index is 1, let's update to using correct mmc number for distro >>>>> boot order in common header. >>>>> >>>>> SD card suppost to have higher priority so that people can boot into >>>>> the firmware in SD card, this is very convenient for developer try with >>>>> distro img from SUSE, Fedora and etc. Developer only need to 'dd' the >>>>> Distro image(which id download from OS vendor release) into SD card >>>>> without >>>>> any modify and then we can boot it up directly. >>>> You never addressed the review comment from Klaus (from the review in May): >>> I do address the review comment and that's why this patch has been V3 >>> but not a RESEND for V1. The source code does not change, while the commit >>> message has update to make it more clear why this patch is needed. >>> >>> I'm sorry to Klaus for not sure if I have reply to him directly, but I >>> do this >>> because I always not get response after I send out my comments in this >>> channel, >>> then I thought send a new patch with necessary update may be more fast to >>> make patch merged. >>> >>>>> Also prioritising SD card over eMMC does not make any sense to me. At >>>>> least on >>>>> RK3399 and RK3368 the default ROM boot order is first eMMC then SD card. >>>>> So >>>>> starting U-Boot from eMMC and then loading the Kernel from SD-card >>>>> doesn’t sound >>>>> right for me. >> +1 for keeping the ROM boot order also for u-boot. >> >> >>>> This will change default behaviour and may break things for users in the >>>> field. >>>> Before we can move forward, we really need to establish a consensus on this >>>> and how users will be affected. >>>> >>>> While this doesn’t matter much for our boards, as we have logic to rewrite >>>> the >>>> default boot during boot-up anyway, I expect a lot of trouble for mainline >>>> users >>>> with their own boards... >>> First we have to understand what we want and what we should do, I think the >>> origin comment "First try to boot from SD (index 0), then eMMC (index 1)" is >>> what we want, but the index is wrong, so we have to correct it, and my first >>> commit message is about "index fix". >>> And I do explain in latest commit message about why we need boot SD first, >>> but I'm not sure if you have read it. >>> >>> Rockchip private loaders always make SD as higher priority then eMMC, >>> because >>> we may need use SD to update the firmware for eMMC or just a temporary test >>> only image to check if the PCB is good or not. >>> I think most of SBC developers prefer to use SD card instead of eMMC, >>> because >>> write a SD is easier then update eMMC firmware with vendor tools, and we can >>> use SD card just like we try a Ubuntu in a Udisk without install it in >>> hard disk for PC, >>> just like I write in the commit message. >> If that is the case, then the SBC developers can override >> BOOT_TARGET_DEVICES to their needs in the specific board include file. > This need a updated of U-Boot into there eMMC, right? yes, you are right. But this should not be an issue for SBCs shipped with rockchip private loaders since - as you mentioned before - they already prioritize the SD card. > Most of boards with Rockchip SoC will ship with rockchip default U-Boot, > what I want to do > is the default behavior, developers can boot the system from SD card by > default. > But, please note that every one wants to play with U-Boot. >> >>> If we keep eMMC as higher priority, then people have no chance to use >>> firmware >>> in SD card if there already have firmware in eMMC. >> AFAIK most of the rockchip boards provide a jumper to somehow cut the >> eMMC clock and bypass the fixed ROM boot order. > No, not for all the products like box and tablet, and m
Re: [U-Boot] [RESENT PATCH v3] rockchip: update emmc/sd index for distro boot order
Hi, Am 29.11.18 um 02:48 schrieb Kever Yang: > > On 11/28/2018 05:15 PM, Philipp Tomsich wrote: >> Kever, >> >>> On 28.11.2018, at 03:06, Kever Yang wrote: >>> >>> According to the emmc/sdcard index in dts alias, emmc is always 0 and >>> sdcard index is 1, let's update to using correct mmc number for distro >>> boot order in common header. >>> >>> SD card suppost to have higher priority so that people can boot into >>> the firmware in SD card, this is very convenient for developer try with >>> distro img from SUSE, Fedora and etc. Developer only need to 'dd' the >>> Distro image(which id download from OS vendor release) into SD card without >>> any modify and then we can boot it up directly. >> You never addressed the review comment from Klaus (from the review in May): > I do address the review comment and that's why this patch has been V3 > but not a RESEND for V1. The source code does not change, while the commit > message has update to make it more clear why this patch is needed. > > I'm sorry to Klaus for not sure if I have reply to him directly, but I > do this > because I always not get response after I send out my comments in this > channel, > then I thought send a new patch with necessary update may be more fast to > make patch merged. > >>> Also prioritising SD card over eMMC does not make any sense to me. At least >>> on >>> RK3399 and RK3368 the default ROM boot order is first eMMC then SD card. So >>> starting U-Boot from eMMC and then loading the Kernel from SD-card doesn’t >>> sound >>> right for me. +1 for keeping the ROM boot order also for u-boot. >> This will change default behaviour and may break things for users in the >> field. >> Before we can move forward, we really need to establish a consensus on this >> and how users will be affected. >> >> While this doesn’t matter much for our boards, as we have logic to rewrite >> the >> default boot during boot-up anyway, I expect a lot of trouble for mainline >> users >> with their own boards... > First we have to understand what we want and what we should do, I think the > origin comment "First try to boot from SD (index 0), then eMMC (index 1)" is > what we want, but the index is wrong, so we have to correct it, and my first > commit message is about "index fix". > And I do explain in latest commit message about why we need boot SD first, > but I'm not sure if you have read it. > > Rockchip private loaders always make SD as higher priority then eMMC, > because > we may need use SD to update the firmware for eMMC or just a temporary test > only image to check if the PCB is good or not. > I think most of SBC developers prefer to use SD card instead of eMMC, > because > write a SD is easier then update eMMC firmware with vendor tools, and we can > use SD card just like we try a Ubuntu in a Udisk without install it in > hard disk for PC, > just like I write in the commit message. If that is the case, then the SBC developers can override BOOT_TARGET_DEVICES to their needs in the specific board include file. > > If we keep eMMC as higher priority, then people have no chance to use > firmware > in SD card if there already have firmware in eMMC. AFAIK most of the rockchip boards provide a jumper to somehow cut the eMMC clock and bypass the fixed ROM boot order. Regards, Wadim > > Then let's check if this "break things for users in the field ", this > patch only affect the > case both eMMC and SD have available firmware(boot.img), right? > I think people only write firmware to SD when they want to boot from it, > or else > people would never do it, the SD will be a normal external storage if > they want to use > the firmware in eMMC. I don't think there will be "a lot of trouble for > mainline users ". > > With this patch, people can use firmware in SD card if they want; > Without this patch, people never able to use firmware in SD card if eMMC > firmware exist > (even if it's broken). > > > Hi Klaus, > How do you think? > > Thanks, > - Kever >>> Signed-off-by: Kever Yang >>> --- >>> >>> Changes in v3: >>> - update the commit message >>> Series-changes: 2 >>> - update the commit message >>> >>> include/configs/rockchip-common.h | 6 +++--- >>> 1 file changed, 3 insertions(+), 3 deletions(-) >>> >>> diff --git a/include/configs/rockchip-common.h >>> b/include/configs/rockchip-common.h >>> index 68e1105a4b..8a72613e52 100644 >>> --- a/include/configs/rockchip-common.h >>> +++ b/include/configs/rockchip-common.h >>> @@ -11,11 +11,11 @@ >>> >>> #ifndef CONFIG_SPL_BUILD >>> >>> -/* First try to boot from SD (index 0), then eMMC (index 1) */ >>> +/* First try to boot from SD (index 1), then eMMC (index 0) */ >>> #if CONFIG_IS_ENABLED(CMD_MMC) >>> #define BOOT_TARGET_MMC(func) \ >>> - func(MMC, mmc, 0) \ >>> - func(MMC, mmc, 1) >>> + func(MMC, mmc, 1) \ >>> + func(MMC, mmc, 0) >>> #else >>> #define BOOT_TARGET_MMC(func) >>> #endif >>> -- >>> 2.18.0 >>> > >
Re: [U-Boot] [PATCH v2 3/3] imx: Add PHYTEC phyBOARD-i.MX6UL-Segin
Hi Martyn,
thanks for upstreaming this board. For the three patches & with
u-boot.imx image type,
Tested-by: Wadim Egorov
But it seems, phycore_pcl063_spl_defconfig is not working:
U-Boot spl 2018.11-00307-g74b1be3 (Nov 27 2018 - 15:05:14 +0100)
Trying to boot from MMC1
MMC Device 0 not found
spl: could not find mmc device 0. error: -19
spl: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Also, some nits below.
Am 23.11.18 um 17:47 schrieb Martyn Welch:
> Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
> the PHYTEC phyCORE-i.MX6UL SOM (PCL063). This port provides both SPL and
> DCD based boot options (hence the two defconfigs).
>
> CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
> CPU: Industrial temperature grade (-40C to 105C) at 44C
> Reset cause: POR
> Board: PHYTEC phyCORE-i.MX6UL
> I2C: ready
> DRAM: 256 MiB
> NAND: 512 MiB
> MMC: FSL_SDHC: 0
> In:serial
> Out: serial
> Err: serial
> Net: FEC0
>
> Working:
> - Eth0
> - i2C
> - MMC/SD
> - NAND
> - UART (1 & 5)
> - USB (host & otg)
>
> Signed-off-by: Martyn Welch
>
> ---
>
> Changes in v2:
> - Switch to driver model
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/imx6ul-pcl063.dtsi | 180 ++
> arch/arm/dts/imx6ul-phycore-segin.dts | 76 ++
> arch/arm/mach-imx/mx6/Kconfig | 13 ++
> board/phytec/pcl063/Kconfig | 12 ++
> board/phytec/pcl063/MAINTAINERS | 9 ++
> board/phytec/pcl063/Makefile | 7 +
> board/phytec/pcl063/README| 43 ++
> board/phytec/pcl063/imximage.cfg | 177 ++
> board/phytec/pcl063/pcl063.c | 206 ++
> board/phytec/pcl063/spl.c | 118 +++
> configs/phycore_pcl063_defconfig | 66 +
> configs/phycore_pcl063_spl_defconfig | 71 +
> include/configs/pcl063.h | 100 +
> 14 files changed, 1080 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi
> create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts
> create mode 100644 board/phytec/pcl063/Kconfig
> create mode 100644 board/phytec/pcl063/MAINTAINERS
> create mode 100644 board/phytec/pcl063/Makefile
> create mode 100644 board/phytec/pcl063/README
> create mode 100644 board/phytec/pcl063/imximage.cfg
> create mode 100644 board/phytec/pcl063/pcl063.c
> create mode 100644 board/phytec/pcl063/spl.c
> create mode 100644 configs/phycore_pcl063_defconfig
> create mode 100644 configs/phycore_pcl063_spl_defconfig
> create mode 100644 include/configs/pcl063.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index d36447d18d..ffda97a291 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -444,7 +444,8 @@ dtb-$(CONFIG_MX6UL) += \
> imx6ul-isiot-nand.dtb \
> imx6ul-opos6uldev.dtb \
> imx6ul-14x14-evk.dtb \
> - imx6ul-9x9-evk.dtb
> + imx6ul-9x9-evk.dtb \
> + imx6ul-phycore-segin.dtb
>
> dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
>
> diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-pcl063.dtsi
> new file mode 100644
> index 00..fa63911480
> --- /dev/null
> +++ b/arch/arm/dts/imx6ul-pcl063.dtsi
> @@ -0,0 +1,180 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Collabora Ltd.
> + *
> + * Based on dts[i] from Phytech barebox port:
it's Phytec
> + * Copyright (C) 2016 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ul.dtsi"
> +
> +/ {
> + model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
> + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
> +
> + memory {
> + reg = <0x8000 0x2000>;
> + };
> +
> + chosen {
> + stdout-path =
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_enet1>;
> + phy-mode = "rmii";
> + phy-handle = <>;
> + status = "okay";
> +
> + mdio: mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
Re: [U-Boot] [PATCH v2 01/11] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init
Hi Philipp, Am 18.07.2018 um 11:05 schrieb Dr. Philipp Tomsich: > Janine, > >> On 18 Jul 2018, at 10:46, Janine Hagemann wrote: >> >> At start-up, the regulators have to be enabled. Let's use >> regulators_enable_boot_on() to enable the regulators needed >> for boot. >> >> Signed-off-by: Wadim Egorov >> Signed-off-by: Janine Hagemann > An equivalent change from Carlo has already been applied to U-Boot master. > Please review whether there’s additional changes needed, otherwise I’ll just > skip this one when processing. I don't see this patch on master. Anyway, Carlos patch enables the regulators only for the google veyrons. Regards, Wadim > > Thanks, > Philipp. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC
Hi, Am 08.05.2018 um 10:05 schrieb Dr. Philipp Tomsich: > Looks like the designware GMAC driver is trying to enable a clock and > can’t deal with the -ENOENT. Could you try to see which clock it is > requesting and add the necessary entries in the clock-enable function? > > If you have a patch, I’ll try to prioritise it, so we get these regressions > cleaned up quickly (note that these had all been in rc3—if we’d known > earlier, I could have reverted them out for the release). > > @Wadim: could you please also look into this, as your board should have > similar problems (unless your device-tree is very different). unfortunately I am not able to test ethernet on our board right now, because there are a few things missing in the designware/gmac part. But someone is working on it right now :) Anyway, it looks like Jonathan fixed the problem, right? Regards, Wadim > > Thanks, > Philipp. > >> On 8 May 2018, at 09:51, Jonathan Gray <j...@jsg.id.au> wrote: >> >> On Thu, Apr 26, 2018 at 09:05:33AM +0200, Philipp Tomsich wrote: >>>> The generic ehci-driver (ehci-generic.c) will try to enable the clocks >>>> listed in the DTSI. If this fails (e.g. due to clk_enable not being >>>> implemented in a driver and -ENOSYS being returned by the clk-uclass), >>>> the driver will bail our and print an error message. >>>> >>>> This implements a minimal clk_enable for the RK3288 and supports the >>>> clocks mandatory for the EHCI controllers; as these are enabled by >>>> default we simply return success. >>>> >>>> Signed-off-by: Wadim Egorov <w.ego...@phytec.de> >>>> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> >>>> Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> >>>> --- >>>> drivers/clk/rockchip/clk_rk3288.c | 13 + >>>> 1 file changed, 13 insertions(+) >>>> >>> Applied to u-boot-rockchip, thanks! >> This change broke Ethernet on tinker-rk3288. >> >> U-Boot 2018.05-2-g6ea9f3dd70 (May 08 2018 - 17:21:32 +1000) >> >> Model: Tinker-RK3288 >> DRAM: 2 GiB >> MMC: dwmmc@ff0c: 1 >> Loading Environment from MMC... *** Warning - bad CRC, using default >> environment >> >> Failed (-5) >> In:serial >> Out: serial >> Err: serial >> Model: Tinker-RK3288 >> Net: failed to enable clock 0 >> No ethernet found. >> >> After reverting it: >> >> U-Boot 2018.05-3-g338bfe2fbf (May 08 2018 - 17:40:09 +1000) >> >> Model: Tinker-RK3288 >> DRAM: 2 GiB >> MMC: dwmmc@ff0c: 1 >> Loading Environment from MMC... *** Warning - bad CRC, using default >> environment >> >> Failed (-5) >> In:serial >> Out: serial >> Err: serial >> Model: Tinker-RK3288 >> Net: eth0: ethernet@ff29 >> Hit any key to stop autoboot: 0 >> >> If the default case returned ENOSYS or ENOTSUPP instead of ENOENT it >> would work given the changes that were made last time this broke. >> >> commit 1693a577be14a92e61563bad306aa11a359757f5 >> Author: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> >> Date: Tue Feb 6 17:12:09 2018 +0300 >> >>NET: designware: fix clock enable ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
