[U-Boot] [Patch V6 0/4] add mips64 cpus support
I'm so sorry, because of my careless, I made a serious fault in last version. I wish everything is ok in this version. Changes in V6: - reorganise patch - add flash support Changes in V5: - omit camel-case style - avoid running git bisect failed - some code style problem corrected Changes in V4: - Add both big-endian and little-endian support - Remove cache probe - Add standalone support for mips64 Changes in V3: - merge related files into one patch, no longer one file one patch. - add detailed commit message. - remove standalone example. it's too complicate. Zhizhou Zhang (4): MIPS: don't use camel-case style MIPS: change address related header files MIPS: remove board/qemu-mips/config.mk MIPS: add board qemu-mips64 support Zhizhou Zhang (4): MIPS: don't use camel-case style MIPS: change address related header files MIPS: remove board/qemu-mips/config.mk MIPS: add board qemu-mips64 support arch/mips/cpu/mips32/cache.S| 10 +- arch/mips/cpu/mips32/cpu.c |8 +- arch/mips/cpu/mips64/Makefile | 45 ++ arch/mips/cpu/mips64/cache.S| 229 +++ arch/mips/cpu/mips64/config.mk | 40 ++ arch/mips/cpu/mips64/cpu.c | 111 +++ arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S| 256 +++ arch/mips/cpu/mips64/time.c | 87 arch/mips/cpu/xburst/cpu.c | 12 +- arch/mips/cpu/xburst/start.S|4 +- arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/asm.h |2 +- arch/mips/include/asm/cacheops.h| 82 +-- arch/mips/include/asm/io.h | 16 +++ arch/mips/include/asm/posix_types.h |6 + board/qemu-mips/config.mk | 10 -- board/qemu-mips/u-boot.lds |8 ++ boards.cfg |2 + examples/standalone/mips64.lds | 59 include/configs/qemu-mips.h |1 + include/configs/qemu-mips64.h | 175 22 files changed, 1129 insertions(+), 70 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c delete mode 100644 board/qemu-mips/config.mk create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V6 1/4] MIPS: don't use camel-case style
Replace camel-case style with upper-case style globally.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips32/cache.S | 10 ++---
arch/mips/cpu/mips32/cpu.c |8 ++--
arch/mips/cpu/xburst/cpu.c | 12 +++---
arch/mips/cpu/xburst/start.S |4 +-
arch/mips/include/asm/asm.h |2 +-
arch/mips/include/asm/cacheops.h | 82 +++---
6 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8b..64dfad0 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDUt1, t0, a1
-1: cache_opIndex_Store_Tag_I t0
+1: cache_opINDEX_STORE_TAG_I t0
PTR_ADDUt0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
-2: cache_opFill t0
+2: cache_opFILL t0
PTR_ADDUt0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
-1: cache_opIndex_Store_Tag_I t0
+1: cache_opINDEX_STORE_TAG_I t0
PTR_ADDUt0, a2
bne t0, t1, 1b
9: jr ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDUt1, t0, a1
-1: cache_opIndex_Store_Tag_D t0
+1: cache_opINDEX_STORE_TAG_D t0
PTR_ADDUt0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
-1: cache_opIndex_Store_Tag_D t0
+1: cache_opINDEX_STORE_TAG_D t0
PTR_ADDUt0, a2
bne t0, t1, 1b
9: jr ra
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 7b49e1b..50bb248 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
return;
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
while (1) {
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..cc190df 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) ~(lsize - 1);
for (; addr = aend; addr += lsize) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
}
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
for (; addr = aend; addr += lsize)
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
for (; addr = aend; addr += lsize)
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
for (addr = CKSEG0; addr CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Store_Tag_I, addr);
+ cache_op(INDEX_STORE_TAG_I, addr);
}
/* invalidate btb */
@@ -139,7 +139,7 @@ void
[U-Boot] [Patch V6 3/4] MIPS: remove board/qemu-mips/config.mk
We define CONFIG_SYS_TEXT_BASE in board's specified header file. So config.mk is useless, then remove it. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- board/qemu-mips/config.mk | 10 -- include/configs/qemu-mips.h |1 + 2 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 board/qemu-mips/config.mk diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk deleted file mode 100644 index 27cd34a..000 --- a/board/qemu-mips/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# Qemu -M mips system emulator -# See http://fabrice.bellard.free.fr/qemu -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xbfc0 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80001000 diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index b8b9705..f45f78b 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -137,6 +137,7 @@ */ /* The following #defines are needed to get flash environment right */ +#define CONFIG_SYS_TEXT_BASE 0xbfc0 /* Rom version */ #define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 10) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V6 2/4] MIPS: change address related header files
Prepare for upcoming mips64 support. This patch add mips64 address
support.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/addrspace.h |2 +-
arch/mips/include/asm/io.h | 16
arch/mips/include/asm/posix_types.h |6 ++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h
b/arch/mips/include/asm/posix_types.h
index 879aae2..6566ad0 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int__kernel_ipc_pid_t;
typedef int__kernel_uid_t;
typedef int__kernel_gid_t;
+#ifndef CONFIG_MIPS64
typedef unsigned int __kernel_size_t;
typedef int__kernel_ssize_t;
typedef int__kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
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[U-Boot] [Patch V6 4/4] MIPS: add board qemu-mips64 support
Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/Makefile | 45 +++ arch/mips/cpu/mips64/cache.S | 229 + arch/mips/cpu/mips64/config.mk| 40 ++ arch/mips/cpu/mips64/cpu.c| 111 arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S | 256 + arch/mips/cpu/mips64/time.c | 87 + board/qemu-mips/u-boot.lds|8 ++ boards.cfg|2 + examples/standalone/mips64.lds| 59 + include/configs/qemu-mips64.h | 175 + 11 files changed, 1046 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..be38664 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o cache.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S new file mode 100644 index 000..036f035 --- /dev/null +++ b/arch/mips/cpu/mips64/cache.S @@ -0,0 +1,229 @@ +/* + * Cache-handling routined for MIPS CPUs + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/asm.h +#include asm/regdef.h +#include asm/mipsregs.h +#include asm/addrspace.h +#include asm/cacheops.h + +#define RA t9 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE0x1 + +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .setpush + .setnoreorder + .setmips3
[U-Boot] [Patch V5 0/4] add mips64 cpus support
This patch add mips64 cpu support. In this version, I have tested it both when configured running in ram version and running in rom version. qemu-system-mips64 -M mips -cpu MIPS64R2-generic -bios u-boot.bin -nographic U-Boot 2012.07-00146-g42c7773 (Sep 04 2012 - 21:56:46) Board: Qemu -M mips CPU: unknown proc_id=0x1 DRAM: 128 MiB Using default environment In:serial Out: serial Err: serial Net: NE2000 qemu-mips64 # Changes in V5: - omit camel-case style - avoid running git bisect failed - some code style problem corrected Changes in V4: - Add both big-endian and little-endian support - Remove cache probe - Add standalone support for mips64 Changes in V3: - merge related files into one patch, no longer one file one patch. - add detailed commit message. - remove standalone example. it's too complicate. Zhizhou Zhang (4): MIPS: Don't use camel-case style MIPS: change address related header files MIPS: don't define CONFIG_SYS_TEXT_BASE in config.mk MIPS: add board qemu-mips64 support arch/mips/cpu/mips32/cache.S| 10 +- arch/mips/cpu/mips32/cpu.c |8 +- arch/mips/cpu/mips64/Makefile | 45 ++ arch/mips/cpu/mips64/cache.S| 229 +++ arch/mips/cpu/mips64/config.mk | 40 ++ arch/mips/cpu/mips64/cpu.c | 111 +++ arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S| 256 +++ arch/mips/cpu/mips64/time.c | 87 arch/mips/cpu/xburst/cpu.c | 12 +- arch/mips/cpu/xburst/start.S|4 +- arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/asm.h |2 +- arch/mips/include/asm/cacheops.h| 82 +-- arch/mips/include/asm/io.h | 16 +++ arch/mips/include/asm/posix_types.h |6 + board/qemu-mips/config.mk | 10 -- board/qemu-mips/u-boot.lds |8 ++ boards.cfg |2 + examples/standalone/mips64.lds | 59 include/configs/qemu-mips.h |1 + include/configs/qemu-mips64.h | 171 +++ 22 files changed, 1125 insertions(+), 70 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c delete mode 100644 board/qemu-mips/config.mk create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 2/4] MIPS: change address related header files
Prepare for upcoming mips64 support. This patch add mips64 address
space support.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/addrspace.h |2 +-
arch/mips/include/asm/asm.h |2 +-
arch/mips/include/asm/io.h | 16
arch/mips/include/asm/posix_types.h |6 ++
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 608cfcf..933ccb1 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -401,7 +401,7 @@ symbol = value
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include asm/cacheops.h
-#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
+#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
#else
#define R10KCBARRIER(addr)
#endif
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h
b/arch/mips/include/asm/posix_types.h
index 879aae2..6566ad0 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int__kernel_ipc_pid_t;
typedef int__kernel_uid_t;
typedef int__kernel_gid_t;
+#ifndef CONFIG_MIPS64
typedef unsigned int __kernel_size_t;
typedef int__kernel_ssize_t;
typedef int__kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
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[U-Boot] [Patch V5 1/4] MIPS: Don't use camel-case style
Replace camel-case style with upper-case style globally.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips32/cache.S | 10 ++---
arch/mips/cpu/mips32/cpu.c |8 ++--
arch/mips/cpu/xburst/cpu.c | 12 +++---
arch/mips/cpu/xburst/start.S |4 +-
arch/mips/include/asm/cacheops.h | 82 +++---
5 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8b..64dfad0 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDUt1, t0, a1
-1: cache_opIndex_Store_Tag_I t0
+1: cache_opINDEX_STORE_TAG_I t0
PTR_ADDUt0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
-2: cache_opFill t0
+2: cache_opFILL t0
PTR_ADDUt0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
-1: cache_opIndex_Store_Tag_I t0
+1: cache_opINDEX_STORE_TAG_I t0
PTR_ADDUt0, a2
bne t0, t1, 1b
9: jr ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDUt1, t0, a1
-1: cache_opIndex_Store_Tag_D t0
+1: cache_opINDEX_STORE_TAG_D t0
PTR_ADDUt0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
-1: cache_opIndex_Store_Tag_D t0
+1: cache_opINDEX_STORE_TAG_D t0
PTR_ADDUt0, a2
bne t0, t1, 1b
9: jr ra
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 7b49e1b..50bb248 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
return;
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
while (1) {
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..cc190df 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) ~(lsize - 1);
for (; addr = aend; addr += lsize) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
}
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
for (; addr = aend; addr += lsize)
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) ~(lsize - 1);
for (; addr = aend; addr += lsize)
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
for (addr = CKSEG0; addr CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Store_Tag_I, addr);
+ cache_op(INDEX_STORE_TAG_I, addr);
}
/* invalidate btb */
@@ -139,7 +139,7 @@ void flush_dcache_all(void)
for (addr = CKSEG0
[U-Boot] [Patch V5 3/4] MIPS: don't define CONFIG_SYS_TEXT_BASE in config.mk
We define CONFIG_SYS_TEXT_BASE in board's specified header file. So config.mk is useless, then remove it. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- board/qemu-mips/config.mk | 10 -- include/configs/qemu-mips.h |1 + 2 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 board/qemu-mips/config.mk diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk deleted file mode 100644 index 27cd34a..000 --- a/board/qemu-mips/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# Qemu -M mips system emulator -# See http://fabrice.bellard.free.fr/qemu -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xbfc0 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80001000 diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index b8b9705..f45f78b 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -137,6 +137,7 @@ */ /* The following #defines are needed to get flash environment right */ +#define CONFIG_SYS_TEXT_BASE 0xbfc0 /* Rom version */ #define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 10) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support
Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/Makefile | 45 +++ arch/mips/cpu/mips64/cache.S | 229 + arch/mips/cpu/mips64/config.mk| 40 ++ arch/mips/cpu/mips64/cpu.c| 111 arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S | 256 + arch/mips/cpu/mips64/time.c | 87 + board/qemu-mips/u-boot.lds|8 ++ boards.cfg|2 + examples/standalone/mips64.lds| 59 + include/configs/qemu-mips64.h | 171 + 11 files changed, 1042 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..be38664 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o cache.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S new file mode 100644 index 000..036f035 --- /dev/null +++ b/arch/mips/cpu/mips64/cache.S @@ -0,0 +1,229 @@ +/* + * Cache-handling routined for MIPS CPUs + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/asm.h +#include asm/regdef.h +#include asm/mipsregs.h +#include asm/addrspace.h +#include asm/cacheops.h + +#define RA t9 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE0x1 + +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .setpush + .setnoreorder + .setmips3
[U-Boot] [Patch V4 2/4] MIPS: change related header files
The most important difference between mips32 and mips64 is the address
space. This patch solve This problem.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/addrspace.h |2 +-
arch/mips/include/asm/io.h | 16
arch/mips/include/asm/posix_types.h |6 ++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h
b/arch/mips/include/asm/posix_types.h
index 879aae2..1164652 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int__kernel_ipc_pid_t;
typedef int__kernel_uid_t;
typedef int__kernel_gid_t;
+#ifndef CONFIG_MIPS64
typedef unsigned int __kernel_size_t;
typedef int__kernel_ssize_t;
typedef int__kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
___
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[U-Boot] [Patch V4 0/4] MIPS: add mips64 cpu support
This patch add mips64 cpu support. Changes in V4: - Add both big-endian and little-endian support - Remove cache probe - Add standalone support for mips64 Changes in V3: - merge related files into one patch, no longer one file one patch. - add detailed commit message. - remove standalone example. it's too complicate. Zhizhou Zhang (4): MIPS: Add support for MIPS64 cpus MIPS: change related header files MIPS: add board qemu-mips64 support MIPS: add mips64 standalone support arch/mips/cpu/mips64/Makefile | 46 +++ arch/mips/cpu/mips64/cache.S| 229 +++ arch/mips/cpu/mips64/config.mk | 40 ++ arch/mips/cpu/mips64/cpu.c | 111 +++ arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S| 256 +++ arch/mips/cpu/mips64/time.c | 87 arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/io.h | 16 +++ arch/mips/include/asm/posix_types.h |6 + board/qemu-mips/config.mk | 10 -- board/qemu-mips/u-boot.lds |8 ++ boards.cfg |2 + examples/standalone/mips64.lds | 59 include/configs/qemu-mips.h |1 + include/configs/qemu-mips64.h | 179 16 files changed, 1075 insertions(+), 11 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c delete mode 100644 board/qemu-mips/config.mk create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V4 1/4] MIPS: Add support for MIPS64 cpus
These files are derived from arch/mips/cpu/mips32/*. The main changes are: 1, changes ABI o32 to n64, 2, add mips64 build cflags. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/Makefile | 46 +++ arch/mips/cpu/mips64/cache.S | 229 + arch/mips/cpu/mips64/config.mk| 40 ++ arch/mips/cpu/mips64/cpu.c| 111 arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S | 256 + arch/mips/cpu/mips64/time.c | 87 + 7 files changed, 803 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..f4c88f5 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o cache.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S new file mode 100644 index 000..ba7c1b8 --- /dev/null +++ b/arch/mips/cpu/mips64/cache.S @@ -0,0 +1,229 @@ +/* + * Cache-handling routined for MIPS CPUs + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/asm.h +#include asm/regdef.h +#include asm/mipsregs.h +#include asm/addrspace.h +#include asm/cacheops.h + +#define RA t9 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE0x1 + +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .setpush + .setnoreorder + .setmips3 + cache \op, 0(\addr) + .setpop + .endm + + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S
[U-Boot] [Patch V4 3/4] MIPS: add board qemu-mips64 support
Both big-endian and little-endian are tested with below commands:
qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/u-boot.lds|8 ++
boards.cfg|2 +
include/configs/qemu-mips64.h | 179 +
3 files changed, 189 insertions(+)
create mode 100644 include/configs/qemu-mips64.h
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..4d9580f 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT(elf64-tradbigmips, elf64-tradbigmips, elf64-tradlittlemips)
+#else
OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips)
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) 3;
+#else
num_got_entries = (__got_end - __got_start) 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
diff --git a/boards.cfg b/boards.cfg
index 6b54941..ff4bb0c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -380,6 +380,8 @@ M5485HFE m68kmcf547x_8x m548xevb
freescale -
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mipsmipsmips32 qemu-mips -
- qemu-mips:SYS_BIG_ENDIAN
qemu_mipsel mipsmips32 qemu-mips -
- qemu-mips:SYS_LITTLE_ENDIAN
+qemu_mips64 mipsmips64 qemu-mips -
- qemu-mips64:SYS_BIG_ENDIAN
+qemu_mips64elmipsmips64 qemu-mips -
- qemu-mips64:SYS_LITTLE_ENDIAN
vct_platinum mipsmips32 vct
micronas - vct:VCT_PLATINUM
vct_platinumavc mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 000..c1962a0
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 /* MIPS64 CPU core */
+#define CONFIG_QEMU_MIPS1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP10.0.2.2/* Server IP address */
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ addmisc=setenv bootargs ${bootargs} \
+ console=ttyS0,${baudrate} \
+ panic=1\0 \
+ bootfile=/tftpboot/vmlinux\0 \
+ load=tftp 8050 ${u-boot}\0\
+
+
+#define CONFIG_BOOTCOMMAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration
[U-Boot] [Patch V4 4/4] MIPS: add mips64 standalone support
Move CONFIG_SYS_TEXT_BASE to the board specified header file. So
change qemu-mips.h also. board/qemu-mips/config.mk is not used, then
remove it.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/config.mk | 10 ---
examples/standalone/mips64.lds | 59
include/configs/qemu-mips.h|1 +
3 files changed, 60 insertions(+), 10 deletions(-)
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 examples/standalone/mips64.lds
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc0
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds
new file mode 100644
index 000..9b27ef4
--- /dev/null
+++ b/examples/standalone/mips64.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
+*/
+OUTPUT_FORMAT(elf64-tradbigmips, elf64-tradbigmips, elf64-tradlittlemips)
+OUTPUT_ARCH(mips)
+SECTIONS
+{
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ .sdata : { *(.sdata*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
+
+ _end = .;
+}
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index b8b9705..bab3fb1 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -137,6 +137,7 @@
*/
/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE 0xbfc0 /* Rom version */
#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 10)
--
1.7.9.5
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[U-Boot] [Patch V4 0/4] MIPS: add mips64 cpu support
This patch add mips64 cpu support. Changes in V4: - Add both big-endian and little-endian support - Remove cache probe - Add standalone support for mips64 Changes in V3: - merge related files into one patch, no longer one file one patch. - add detailed commit message. - remove standalone example. it's too complicate. Zhizhou Zhang (4): MIPS: Add support for MIPS64 cpus MIPS: change related header files MIPS: add board qemu-mips64 support MIPS: add mips64 standalone support arch/mips/cpu/mips64/Makefile | 46 +++ arch/mips/cpu/mips64/cache.S| 229 +++ arch/mips/cpu/mips64/config.mk | 40 ++ arch/mips/cpu/mips64/cpu.c | 111 +++ arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S| 256 +++ arch/mips/cpu/mips64/time.c | 87 arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/io.h | 16 +++ arch/mips/include/asm/posix_types.h |6 + board/qemu-mips/config.mk | 10 -- board/qemu-mips/u-boot.lds |8 ++ boards.cfg |2 + examples/standalone/mips64.lds | 59 include/configs/qemu-mips.h |1 + include/configs/qemu-mips64.h | 179 16 files changed, 1075 insertions(+), 11 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c delete mode 100644 board/qemu-mips/config.mk create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V4 1/4] MIPS: Add support for MIPS64 cpus
These files are derived from arch/mips/cpu/mips32/*. The main changes are: 1, changes ABI o32 to n64, 2, add mips64 build cflags. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/Makefile | 46 +++ arch/mips/cpu/mips64/cache.S | 229 + arch/mips/cpu/mips64/config.mk| 40 ++ arch/mips/cpu/mips64/cpu.c| 111 arch/mips/cpu/mips64/interrupts.c | 34 + arch/mips/cpu/mips64/start.S | 256 + arch/mips/cpu/mips64/time.c | 87 + 7 files changed, 803 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..f4c88f5 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o cache.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S new file mode 100644 index 000..ba7c1b8 --- /dev/null +++ b/arch/mips/cpu/mips64/cache.S @@ -0,0 +1,229 @@ +/* + * Cache-handling routined for MIPS CPUs + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/asm.h +#include asm/regdef.h +#include asm/mipsregs.h +#include asm/addrspace.h +#include asm/cacheops.h + +#define RA t9 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE0x1 + +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .setpush + .setnoreorder + .setmips3 + cache \op, 0(\addr) + .setpop + .endm + + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S
[U-Boot] [Patch V4 2/4] MIPS: change related header files
The most important difference between mips32 and mips64 is the address
space. This patch solve This problem.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/addrspace.h |2 +-
arch/mips/include/asm/io.h | 16
arch/mips/include/asm/posix_types.h |6 ++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h
b/arch/mips/include/asm/posix_types.h
index 879aae2..1164652 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int__kernel_ipc_pid_t;
typedef int__kernel_uid_t;
typedef int__kernel_gid_t;
+#ifndef CONFIG_MIPS64
typedef unsigned int __kernel_size_t;
typedef int__kernel_ssize_t;
typedef int__kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
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[U-Boot] [Patch V4 3/4] MIPS: add board qemu-mips64 support
Both big-endian and little-endian are tested with below commands:
qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/u-boot.lds|8 ++
boards.cfg|2 +
include/configs/qemu-mips64.h | 179 +
3 files changed, 189 insertions(+)
create mode 100644 include/configs/qemu-mips64.h
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..4d9580f 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT(elf64-tradbigmips, elf64-tradbigmips, elf64-tradlittlemips)
+#else
OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips)
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) 3;
+#else
num_got_entries = (__got_end - __got_start) 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
diff --git a/boards.cfg b/boards.cfg
index 6b54941..ff4bb0c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -380,6 +380,8 @@ M5485HFE m68kmcf547x_8x m548xevb
freescale -
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mipsmipsmips32 qemu-mips -
- qemu-mips:SYS_BIG_ENDIAN
qemu_mipsel mipsmips32 qemu-mips -
- qemu-mips:SYS_LITTLE_ENDIAN
+qemu_mips64 mipsmips64 qemu-mips -
- qemu-mips64:SYS_BIG_ENDIAN
+qemu_mips64elmipsmips64 qemu-mips -
- qemu-mips64:SYS_LITTLE_ENDIAN
vct_platinum mipsmips32 vct
micronas - vct:VCT_PLATINUM
vct_platinumavc mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 000..c1962a0
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 /* MIPS64 CPU core */
+#define CONFIG_QEMU_MIPS1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP10.0.2.2/* Server IP address */
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ addmisc=setenv bootargs ${bootargs} \
+ console=ttyS0,${baudrate} \
+ panic=1\0 \
+ bootfile=/tftpboot/vmlinux\0 \
+ load=tftp 8050 ${u-boot}\0\
+
+
+#define CONFIG_BOOTCOMMAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration
[U-Boot] [Patch V4 4/4] MIPS: add mips64 standalone support
Move CONFIG_SYS_TEXT_BASE to the board specified header file. So
change qemu-mips.h also. board/qemu-mips/config.mk is not used, then
remove it.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/config.mk | 10 ---
examples/standalone/mips64.lds | 59
include/configs/qemu-mips.h|1 +
3 files changed, 60 insertions(+), 10 deletions(-)
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 examples/standalone/mips64.lds
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc0
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds
new file mode 100644
index 000..9b27ef4
--- /dev/null
+++ b/examples/standalone/mips64.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
+*/
+OUTPUT_FORMAT(elf64-tradbigmips, elf64-tradbigmips, elf64-tradlittlemips)
+OUTPUT_ARCH(mips)
+SECTIONS
+{
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ .sdata : { *(.sdata*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
+
+ _end = .;
+}
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index b8b9705..bab3fb1 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -137,6 +137,7 @@
*/
/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE 0xbfc0 /* Rom version */
#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 10)
--
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[U-Boot] [Patch V3 0/4] add mips64 cpu support
This patch add mips64 cpu support. Changes in V3: - merge related files into one patch, no longer one file one patch. - add detailed commit message. - remove standalone example. it's too complicate. Zhizhou Zhang (4): [MIPS] Add support for MIPS64 cpus [MIPS] add mips64 support in mips head files [MIPS] Add qemu-mips building configs [MIPS] Disable standalone while building MIPS64 Makefile|2 + arch/mips/cpu/mips64/Makefile | 47 +++ arch/mips/cpu/mips64/config.mk | 39 ++ arch/mips/cpu/mips64/cpu.c | 124 + arch/mips/cpu/mips64/interrupts.c | 39 ++ arch/mips/cpu/mips64/start.S| 256 +++ arch/mips/cpu/mips64/time.c | 86 arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/cache.h | 21 +++ arch/mips/include/asm/io.h | 18 ++- arch/mips/include/asm/posix_types.h | 12 +- board/qemu-mips/config.mk | 10 -- board/qemu-mips/u-boot.lds |8 ++ boards.cfg |1 + include/configs/qemu-mips.h |3 + include/configs/qemu-mips64.h | 171 +++ 16 files changed, 824 insertions(+), 15 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c delete mode 100644 board/qemu-mips/config.mk create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
These files are derived from arch/mips/cpu/mips32/*. Howerver some Changes are made: *.S: changes ABI o32 to n64 config.mk: add mips64 building cflags cpu.c: add cache size probe interrupts.c: implement enable_interrupts and disable_interrupts Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/Makefile | 47 +++ arch/mips/cpu/mips64/config.mk| 39 ++ arch/mips/cpu/mips64/cpu.c| 124 ++ arch/mips/cpu/mips64/interrupts.c | 39 ++ arch/mips/cpu/mips64/start.S | 256 + arch/mips/cpu/mips64/time.c | 86 + 6 files changed, 591 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..335fe88 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 000..26f79e6 --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +PLATFORM_LDFLAGS += -m elf64ltsmip + diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c new file mode 100644 index 000..348ccfe --- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de + * Zhi-zhou Zhang etou...@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more
[U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files
The most important difference between mips32 and mips64 is the address
space. changes in addrspace.h and io.h are for this sake. And this patch
add cache discribe struct in cache.h, and make compatible to mips64 of
some types in posix_types.h.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/addrspace.h |2 +-
arch/mips/include/asm/cache.h | 21 +
arch/mips/include/asm/io.h | 18 +-
arch/mips/include/asm/posix_types.h | 12 +---
4 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 5406d5d..e41b9b4 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -33,4 +33,25 @@
#define ARCH_DMA_MINALIGN 128
#endif
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int size; /* total size */
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets;/* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+};
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ .setpush\n \
+ .setnoreorder \n \
+ .setmips64\n\t \n \
+ cache %0, %1 \n \
+ .setpop \n \
+ : \
+ : i (op), R (*(unsigned char *)(addr)))
+
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..1b82c61 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
- return (void *)KSEG0ADDR(address);
+#ifndef CONFIG_64BIT
+ return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h
b/arch/mips/include/asm/posix_types.h
index 879aae2..0da1dde 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int__kernel_ipc_pid_t;
typedef int__kernel_uid_t;
typedef int__kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int__kernel_ssize_t;
-typedef int__kernel_ptrdiff_t;
+#ifndef CONFIG_MIPS64
+ typedef unsigned int __kernel_size_t;
+ typedef int __kernel_ssize_t;
+ typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
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[U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
I think copy mips.lds to mips64.lds with only one line changed is not good. So I disable it in top Makefile. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- Makefile |2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index 5ce5cc3..626d888 100644 --- a/Makefile +++ b/Makefile @@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep sinclude $(obj)include/autoconf.mk ifndef CONFIG_SANDBOX +ifndef CONFIG_MIPS64 SUBDIRS += $(SUBDIR_EXAMPLES) endif +endif # load ARCH, BOARD, and CPU configuration include $(obj)include/config.mk -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs
This patch add qemu-mips64 config. And here uses qemu-mips board rather
then a new board qemu-mips64 for the sake of reduce code copying. Below
are the changes:
config.mk: We must define CONFIG_SYS_TEXT_BASE in configs/*.h, not
here, so remove this file.
u-boot.lds: add mips64 link statements.
boards.cfg: add mips64 cpu define.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/config.mk | 10 ---
board/qemu-mips/u-boot.lds|8 ++
boards.cfg|1 +
include/configs/qemu-mips.h |3 +
include/configs/qemu-mips64.h | 171 +
5 files changed, 183 insertions(+), 10 deletions(-)
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 include/configs/qemu-mips64.h
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc0
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..06db68d 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+#else
OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips)
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) 3;
+#else
num_got_entries = (__got_end - __got_start) 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..a6806b8 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -379,6 +379,7 @@ M5485GFE m68kmcf547x_8x m548xevb
freescale -
M5485HFEm68kmcf547x_8x m548xevb
freescale -
M5485EVB:SYS_BUSCLK=1,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mipsmipsmips32 qemu-mips -
- qemu-mips
+qemu_mips64 mipsmips64 qemu-mips -
- qemu-mips64
vct_platinum mipsmips32 vct
micronas - vct:VCT_PLATINUM
vct_platinumavc mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 306c173..bb85bbe 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -135,6 +135,9 @@
#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 10)
+#define CONFIG_SYS_TEXT_BASE 0xbfc0 /* Rom version */
+//#define CONFIG_SYS_TEXT_BASE 0x80001000 /* RAM Version */
+
#define CONFIG_SYS_INIT_SP_OFFSET 0x40
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 000..2f39494
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
+#define CONFIG_64BIT 1
+#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15
[U-Boot] [Patch V3 0/4] add mips64 cpu support
This patch add mips64 cpu support. Changes in V3: - merge related files into one patch, no longer one file one patch. - add detailed commit message. - remove standalone example. it's too complicate. Zhizhou Zhang (4): [MIPS] Add support for MIPS64 cpus [MIPS] add mips64 support in mips head files [MIPS] Add qemu-mips building configs [MIPS] Disable standalone while building MIPS64 Makefile|2 + arch/mips/cpu/mips64/Makefile | 47 +++ arch/mips/cpu/mips64/config.mk | 39 ++ arch/mips/cpu/mips64/cpu.c | 124 + arch/mips/cpu/mips64/interrupts.c | 39 ++ arch/mips/cpu/mips64/start.S| 256 +++ arch/mips/cpu/mips64/time.c | 86 arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/cache.h | 21 +++ arch/mips/include/asm/io.h | 18 ++- arch/mips/include/asm/posix_types.h | 12 +- board/qemu-mips/config.mk | 10 -- board/qemu-mips/u-boot.lds |8 ++ boards.cfg |1 + include/configs/qemu-mips.h |3 + include/configs/qemu-mips64.h | 171 +++ 16 files changed, 824 insertions(+), 15 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c delete mode 100644 board/qemu-mips/config.mk create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
These files are derived from arch/mips/cpu/mips32/*. Howerver some Changes are made: *.S: changes ABI o32 to n64 config.mk: add mips64 building cflags cpu.c: add cache size probe interrupts.c: implement enable_interrupts and disable_interrupts Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/Makefile | 47 +++ arch/mips/cpu/mips64/config.mk| 39 ++ arch/mips/cpu/mips64/cpu.c| 124 ++ arch/mips/cpu/mips64/interrupts.c | 39 ++ arch/mips/cpu/mips64/start.S | 256 + arch/mips/cpu/mips64/time.c | 86 + 6 files changed, 591 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..335fe88 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 000..26f79e6 --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +PLATFORM_LDFLAGS += -m elf64ltsmip + diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c new file mode 100644 index 000..348ccfe --- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de + * Zhi-zhou Zhang etou...@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more
[U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files
The most important difference between mips32 and mips64 is the address
space. changes in addrspace.h and io.h are for this sake. And this patch
add cache discribe struct in cache.h, and make compatible to mips64 of
some types in posix_types.h.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/addrspace.h |2 +-
arch/mips/include/asm/cache.h | 21 +
arch/mips/include/asm/io.h | 18 +-
arch/mips/include/asm/posix_types.h | 12 +---
4 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 5406d5d..e41b9b4 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -33,4 +33,25 @@
#define ARCH_DMA_MINALIGN 128
#endif
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int size; /* total size */
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets;/* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+};
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ .setpush\n \
+ .setnoreorder \n \
+ .setmips64\n\t \n \
+ cache %0, %1 \n \
+ .setpop \n \
+ : \
+ : i (op), R (*(unsigned char *)(addr)))
+
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..1b82c61 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
- return (void *)KSEG0ADDR(address);
+#ifndef CONFIG_64BIT
+ return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h
b/arch/mips/include/asm/posix_types.h
index 879aae2..0da1dde 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int__kernel_ipc_pid_t;
typedef int__kernel_uid_t;
typedef int__kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int__kernel_ssize_t;
-typedef int__kernel_ptrdiff_t;
+#ifndef CONFIG_MIPS64
+ typedef unsigned int __kernel_size_t;
+ typedef int __kernel_ssize_t;
+ typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
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[U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs
This patch add qemu-mips64 config. And here uses qemu-mips board rather
then a new board qemu-mips64 for the sake of reduce code copying. Below
are the changes:
config.mk: We must define CONFIG_SYS_TEXT_BASE in configs/*.h, not
here, so remove this file.
u-boot.lds: add mips64 link statements.
boards.cfg: add mips64 cpu define.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/config.mk | 10 ---
board/qemu-mips/u-boot.lds|8 ++
boards.cfg|1 +
include/configs/qemu-mips.h |3 +
include/configs/qemu-mips64.h | 171 +
5 files changed, 183 insertions(+), 10 deletions(-)
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 include/configs/qemu-mips64.h
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc0
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..06db68d 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+#else
OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips)
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) 3;
+#else
num_got_entries = (__got_end - __got_start) 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..a6806b8 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -379,6 +379,7 @@ M5485GFE m68kmcf547x_8x m548xevb
freescale -
M5485HFEm68kmcf547x_8x m548xevb
freescale -
M5485EVB:SYS_BUSCLK=1,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mipsmipsmips32 qemu-mips -
- qemu-mips
+qemu_mips64 mipsmips64 qemu-mips -
- qemu-mips64
vct_platinum mipsmips32 vct
micronas - vct:VCT_PLATINUM
vct_platinumavc mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mipsmips32 vct
micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 306c173..bb85bbe 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -135,6 +135,9 @@
#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 10)
+#define CONFIG_SYS_TEXT_BASE 0xbfc0 /* Rom version */
+//#define CONFIG_SYS_TEXT_BASE 0x80001000 /* RAM Version */
+
#define CONFIG_SYS_INIT_SP_OFFSET 0x40
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 000..2f39494
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
+#define CONFIG_64BIT 1
+#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15
[U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
I think copy mips.lds to mips64.lds with only one line changed is not good. So I disable it in top Makefile. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- Makefile |2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index 5ce5cc3..626d888 100644 --- a/Makefile +++ b/Makefile @@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep sinclude $(obj)include/autoconf.mk ifndef CONFIG_SANDBOX +ifndef CONFIG_MIPS64 SUBDIRS += $(SUBDIR_EXAMPLES) endif +endif # load ARCH, BOARD, and CPU configuration include $(obj)include/config.mk -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 01/16] add mips64 standalone support
Daniel Schwierzeck told me to do it with macro, But it seems not work. For u-boot.lds was genarete by gcc. It's hard to do that without a lot modify. --- arch/mips/config.mk |4 1 file changed, 4 insertions(+) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..56996cc 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,11 @@ CROSS_COMPILE ?= mips_4KC- +ifeq $(CPU) mips64 +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff8020 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds +endif PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 03/16] add cpu/mips64/config.mk
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/config.mk | 39 +++ 1 file changed, 39 insertions(+) create mode 100644 arch/mips/cpu/mips64/config.mk diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 000..26f79e6 --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +PLATFORM_LDFLAGS += -m elf64ltsmip + -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 02/16] add cpu/mips64/Makefile
--- arch/mips/cpu/mips64/Makefile | 47 + 1 file changed, 47 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..335fe88 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 07/16] add cpu/mips64/time.c
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips64/time.c | 86 +++
1 file changed, 86 insertions(+)
create mode 100644 arch/mips/cpu/mips64/time.c
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 000..350896a
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mipsregs.h
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ /
2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) 0x7fff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return (timestamp - base);
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 100));
+ while ((tmo - read_c0_count()) 0x7fff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--
1.7.9.5
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[U-Boot] [[Patch V2] mips: 06/16] add cpu/mips64/start.S
remove cache init Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/start.S | 373 ++ 1 file changed, 373 insertions(+) create mode 100644 arch/mips/cpu/mips64/start.S diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S new file mode 100644 index 000..375f0c7 --- /dev/null +++ b/arch/mips/cpu/mips64/start.S @@ -0,0 +1,373 @@ +/* + * Startup Code for MIPS64 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any dlater version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/regdef.h +#include asm/mipsregs.h + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + + /* +* For the moment disable interrupts, mark the kernel mode and +* set ST0_KX so that the CPU does not spit fire when using +* 64-bit addresses. +*/ + .macro setup_c0_status set clr + .setpush + mfc0t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0t0, CP0_STATUS + .setnoreorder + sll zero, 3 # ehb + .setpop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + +#define RVECENT(f,n) \ + b f; \ + nop +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder + + .globl _start + .text +_start: + RVECENT(reset,0)# U-boot entry point + RVECENT(reset,1)# software reboot + RVECENT(romReserved,2) + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77
[U-Boot] [[Patch V2] mips: 08/16] Let UNCACHED_SDRAM be available to mips64
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/include/asm/addrspace.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3a1e6d6..b768bb5 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,7 +136,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000) #else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) #endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 09/16] add cache description struct
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/cache.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 5406d5d..45e546d 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -33,4 +33,15 @@
#define ARCH_DMA_MINALIGN 128
#endif
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int size; /* total size */
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets;/* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+};
+
#endif /* __MIPS_CACHE_H__ */
--
1.7.9.5
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[U-Boot] [[Patch V2] mips: 10/16] modify io operation for mips64
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/io.h | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..1b82c61 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
- return (void *)KSEG0ADDR(address);
+#ifndef CONFIG_64BIT
+ return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
--
1.7.9.5
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[U-Boot] [[Patch V2] mips: 12/16] modify u-boot.lds for mips64
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/u-boot.lds |8
1 file changed, 8 insertions(+)
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..06db68d 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+#else
OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips)
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) 3;
+#else
num_got_entries = (__got_end - __got_start) 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
--
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[U-Boot] [[Patch V2] mips: 14/16] add mips64 standalone link script
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
examples/standalone/mips64.lds | 59
1 file changed, 59 insertions(+)
create mode 100644 examples/standalone/mips64.lds
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds
new file mode 100644
index 000..00b96da
--- /dev/null
+++ b/examples/standalone/mips64.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
+*/
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+OUTPUT_ARCH(mips)
+SECTIONS
+{
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ .sdata : { *(.sdata*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
+
+ _end = .;
+}
--
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[U-Boot] [[Patch V2] mips: 15/16] add configs/qemu-mips64.h
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
include/configs/qemu-mips64.h | 171 +
1 file changed, 171 insertions(+)
create mode 100644 include/configs/qemu-mips64.h
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 000..2f39494
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
+#define CONFIG_64BIT 1
+#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP10.0.2.2/* Server IP address */
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ addmisc=setenv bootargs ${bootargs} \
+ console=ttyS0,${baudrate} \
+ panic=1\0 \
+ bootfile=/tftpboot/vmlinux\0 \
+ load=tftp 8050 ${u-boot}\0\
+
+
+#define CONFIG_BOOTCOMMAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include config_cmd_default.h
+#define CONFIG_DP83902A
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE (0xb4000300)
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1(0xb40003f8)
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
+#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
+#define CONFIG_SYS_ATA_DATA_OFFSET (0)
+#define CONFIG_SYS_ATA_REG_OFFSET (0)
+#define CONFIG_SYS_ATA_BASE_ADDR (0xb400)
+
+#define CONFIG_SYS_IDE_MAXDEVICE (4)
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP/* undef to save memory
*/
+
+#define CONFIG_SYS_PROMPT qemu-mips64 # /* Monitor
Command Prompt */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer
Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /*
Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of
command args */
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_SDRAM_BASE 0x8000 /* Cached addr
*/
+
+#define CONFIG_SYS_LOAD_ADDR 0x8100 /* default load
address */
+
+#define CONFIG_SYS_MEMTEST_START 0x8010
+#define CONFIG_SYS_MEMTEST_END 0x8080
[U-Boot] [[Patch V2] mips: 16/16] modify qemu-mips/config.mk
Though I defined CONFIG_SYS_TEXT_BASE in configs/qemu-mips64.h, but the value is still affected by this file. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- board/qemu-mips/config.mk |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk index 27cd34a..a1514a0 100644 --- a/board/qemu-mips/config.mk +++ b/board/qemu-mips/config.mk @@ -2,9 +2,10 @@ # Qemu -M mips system emulator # See http://fabrice.bellard.free.fr/qemu # - +ifeq $(CPU) mips # ROM version CONFIG_SYS_TEXT_BASE = 0xbfc0 # RAM version #CONFIG_SYS_TEXT_BASE = 0x80001000 +endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 00/16] add mips64 support to U-Boot
This patch add mips64 support. --- Change log for V2: - move mips64 build flags to cpu/mips64.mk - add cache size probe - remove cache.S Zhizhou Zhang (16): add mips64 standalone support add cpu/mips64/Makefile add cpu/mips64/config.mk add cpu/mips64/cpu.c add cpu/mips64/interrupts.c add cpu/mips64/start.S add cpu/mips64/time.c Let UNCACHED_SDRAM be available to mips64 add cache description struct modify io operation for mips64 Make size_t equaled to unsigned long modify u-boot.lds for mips64 add board define in boards.cfg add mips64 standalone link script add configs/qemu-mips64.h modify qemu-mips/config.mk arch/mips/config.mk |4 + arch/mips/cpu/mips64/Makefile | 47 + arch/mips/cpu/mips64/config.mk | 39 arch/mips/cpu/mips64/cpu.c | 133 + arch/mips/cpu/mips64/interrupts.c | 39 arch/mips/cpu/mips64/start.S| 373 +++ arch/mips/cpu/mips64/time.c | 86 arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/cache.h | 11 ++ arch/mips/include/asm/io.h | 18 +- arch/mips/include/asm/posix_types.h | 12 +- board/qemu-mips/config.mk |3 +- board/qemu-mips/u-boot.lds |8 + boards.cfg |1 + examples/standalone/mips64.lds | 59 ++ include/configs/qemu-mips64.h | 171 16 files changed, 1000 insertions(+), 6 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 01/16] add mips64 standalone support
Daniel Schwierzeck told me to do it with macro, But it seems not work. For u-boot.lds was genarete by gcc. It's hard to do that without a lot modify. --- arch/mips/config.mk |4 1 file changed, 4 insertions(+) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..56996cc 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,11 @@ CROSS_COMPILE ?= mips_4KC- +ifeq $(CPU) mips64 +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff8020 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds +endif PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 02/16] add cpu/mips64/Makefile
--- arch/mips/cpu/mips64/Makefile | 47 + 1 file changed, 47 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..335fe88 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 04/16] add cpu/mips64/cpu.c
add icache and dcache probe here. but scache was not probed. For
I don't know how to determine it implemented or not.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips64/cpu.c | 133
1 file changed, 133 insertions(+)
create mode 100644 arch/mips/cpu/mips64/cpu.c
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 000..ea9c28a
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ * Zhi-zhou Zhang etou...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include command.h
+#include netdev.h
+#include asm/mipsregs.h
+#include asm/cacheops.h
+#include asm/reboot.h
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ .setpush\n \
+ .setnoreorder \n \
+ .setmips64\n\t \n \
+ cache %0, %1 \n \
+ .setpop \n \
+ : \
+ : i (op), R (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ fprintf(stderr, *** reset failed ***\n);
+ return 0;
+}
+
+static struct cache_desc icache, dcache;
+
+void cache_probe()
+{
+ int config, lsize;
+
+ config = read_c0_config1();
+ lsize = (config 19) 7;
+ if (lsize) { /* icache present */
+ icache.linesz = 2 lsize;
+ icache.sets = 32 (((config 22) + 1) 7);
+ icache.ways = 1 + ((config 16) 7);
+ icache.size = icache.sets *
+ icache.ways *
+ icache.linesz;
+ }
+
+ lsize = (config 10) 7;
+ if (lsize) { /* dcache present */
+ dcache.linesz = 2 lsize;
+ dcache.sets = 32 (((config 13) + 1) 7);
+ dcache.ways = 1 + ((config 7) 7);
+ dcache.size = dcache.sets *
+ dcache.ways *
+ dcache.linesz;
+ }
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long addr, aend;
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ addr = start_addr ~(icache.linesz - 1);
+ aend = (start_addr + size - 1) ~(icache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Invalidate_I, addr);
+ if (addr == aend)
+ break;
+ addr += icache.linesz;
+ }
+
+ addr = start_addr ~(dcache.linesz - 1);
+ aend = (start_addr + size - 1) ~(dcache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Invalidate_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
--
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[U-Boot] [[Patch V2] mips: 05/16] add cpu/mips64/interrupts.c
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips64/interrupts.c | 39 +
1 file changed, 39 insertions(+)
create mode 100644 arch/mips/cpu/mips64/interrupts.c
diff --git a/arch/mips/cpu/mips64/interrupts.c
b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644
index 000..f661fb0
--- /dev/null
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ * Zhi-zhou Zhang etou...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mipsregs.h
+
+void enable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status | ST0_IE);
+}
+
+int disable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status ~ST0_IE);
+ return status | ST0_IE;
+}
--
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[U-Boot] [[Patch V2] mips: 06/16] add cpu/mips64/start.S
remove cache init Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/start.S | 373 ++ 1 file changed, 373 insertions(+) create mode 100644 arch/mips/cpu/mips64/start.S diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S new file mode 100644 index 000..375f0c7 --- /dev/null +++ b/arch/mips/cpu/mips64/start.S @@ -0,0 +1,373 @@ +/* + * Startup Code for MIPS64 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any dlater version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/regdef.h +#include asm/mipsregs.h + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + + /* +* For the moment disable interrupts, mark the kernel mode and +* set ST0_KX so that the CPU does not spit fire when using +* 64-bit addresses. +*/ + .macro setup_c0_status set clr + .setpush + mfc0t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0t0, CP0_STATUS + .setnoreorder + sll zero, 3 # ehb + .setpop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + +#define RVECENT(f,n) \ + b f; \ + nop +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder + + .globl _start + .text +_start: + RVECENT(reset,0)# U-boot entry point + RVECENT(reset,1)# software reboot + RVECENT(romReserved,2) + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77
[U-Boot] [[Patch V2] mips: 07/16] add cpu/mips64/time.c
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips64/time.c | 86 +++
1 file changed, 86 insertions(+)
create mode 100644 arch/mips/cpu/mips64/time.c
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 000..350896a
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mipsregs.h
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ /
2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) 0x7fff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return (timestamp - base);
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 100));
+ while ((tmo - read_c0_count()) 0x7fff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--
1.7.9.5
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[U-Boot] [[Patch V2] mips: 08/16] Let UNCACHED_SDRAM be available to mips64
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/include/asm/addrspace.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3a1e6d6..b768bb5 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,7 +136,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000) #else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) #endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 09/16] add cache description struct
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/cache.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 5406d5d..45e546d 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -33,4 +33,15 @@
#define ARCH_DMA_MINALIGN 128
#endif
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int size; /* total size */
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets;/* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+};
+
#endif /* __MIPS_CACHE_H__ */
--
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[U-Boot] [[Patch V2] mips: 10/16] modify io operation for mips64
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/io.h | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..1b82c61 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
- return (void *)KSEG0ADDR(address);
+#ifndef CONFIG_64BIT
+ return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
--
1.7.9.5
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[U-Boot] [[Patch V2] mips: 12/16] modify u-boot.lds for mips64
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
board/qemu-mips/u-boot.lds |8
1 file changed, 8 insertions(+)
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..06db68d 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+#else
OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips)
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) 3;
+#else
num_got_entries = (__got_end - __got_start) 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
--
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[U-Boot] [[Patch V2] mips: 11/16] Make size_t equaled to unsigned long
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/include/asm/posix_types.h | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae2..0da1dde 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,9 +24,15 @@ typedef int __kernel_pid_t; typedef int__kernel_ipc_pid_t; typedef int__kernel_uid_t; typedef int__kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int__kernel_ssize_t; -typedef int__kernel_ptrdiff_t; +#ifndef CONFIG_MIPS64 + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + typedef int __kernel_ptrdiff_t; +#else +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 13/16] add board define in boards.cfg
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- boards.cfg |1 + 1 file changed, 1 insertion(+) diff --git a/boards.cfg b/boards.cfg index fdb84ad..a6806b8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,6 +379,7 @@ M5485GFE m68kmcf547x_8x m548xevb freescale - M5485HFEm68kmcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=1,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO microblaze-generic microblaze microblaze microblaze-generic xilinx qemu_mipsmipsmips32 qemu-mips - - qemu-mips +qemu_mips64 mipsmips64 qemu-mips - - qemu-mips64 vct_platinum mipsmips32 vct micronas - vct:VCT_PLATINUM vct_platinumavc mipsmips32 vct micronas - vct:VCT_PLATINUMAVC vct_platinumavc_onenand mipsmips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 14/16] add mips64 standalone link script
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
examples/standalone/mips64.lds | 59
1 file changed, 59 insertions(+)
create mode 100644 examples/standalone/mips64.lds
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds
new file mode 100644
index 000..00b96da
--- /dev/null
+++ b/examples/standalone/mips64.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
+*/
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+OUTPUT_ARCH(mips)
+SECTIONS
+{
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ .sdata : { *(.sdata*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
+
+ _end = .;
+}
--
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[U-Boot] [[Patch V2] mips: 15/16] add configs/qemu-mips64.h
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
include/configs/qemu-mips64.h | 171 +
1 file changed, 171 insertions(+)
create mode 100644 include/configs/qemu-mips64.h
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 000..2f39494
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
+#define CONFIG_64BIT 1
+#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP10.0.2.2/* Server IP address */
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ addmisc=setenv bootargs ${bootargs} \
+ console=ttyS0,${baudrate} \
+ panic=1\0 \
+ bootfile=/tftpboot/vmlinux\0 \
+ load=tftp 8050 ${u-boot}\0\
+
+
+#define CONFIG_BOOTCOMMAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include config_cmd_default.h
+#define CONFIG_DP83902A
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE (0xb4000300)
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1(0xb40003f8)
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
+#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
+#define CONFIG_SYS_ATA_DATA_OFFSET (0)
+#define CONFIG_SYS_ATA_REG_OFFSET (0)
+#define CONFIG_SYS_ATA_BASE_ADDR (0xb400)
+
+#define CONFIG_SYS_IDE_MAXDEVICE (4)
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP/* undef to save memory
*/
+
+#define CONFIG_SYS_PROMPT qemu-mips64 # /* Monitor
Command Prompt */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer
Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /*
Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of
command args */
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_SDRAM_BASE 0x8000 /* Cached addr
*/
+
+#define CONFIG_SYS_LOAD_ADDR 0x8100 /* default load
address */
+
+#define CONFIG_SYS_MEMTEST_START 0x8010
+#define CONFIG_SYS_MEMTEST_END 0x8080
[U-Boot] [[Patch V2] mips: 00/16] add mips64 support to U-Boot
This patch add mips64 support. --- Change log for V2: - move mips64 build flags to cpu/mips64.mk - add cache size probe - remove cache.S Zhizhou Zhang (16): add mips64 standalone support add cpu/mips64/Makefile add cpu/mips64/config.mk add cpu/mips64/cpu.c add cpu/mips64/interrupts.c add cpu/mips64/start.S add cpu/mips64/time.c Let UNCACHED_SDRAM be available to mips64 add cache description struct modify io operation for mips64 Make size_t equaled to unsigned long modify u-boot.lds for mips64 add board define in boards.cfg add mips64 standalone link script add configs/qemu-mips64.h modify qemu-mips/config.mk arch/mips/config.mk |4 + arch/mips/cpu/mips64/Makefile | 47 + arch/mips/cpu/mips64/config.mk | 39 arch/mips/cpu/mips64/cpu.c | 133 + arch/mips/cpu/mips64/interrupts.c | 39 arch/mips/cpu/mips64/start.S| 373 +++ arch/mips/cpu/mips64/time.c | 86 arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/cache.h | 11 ++ arch/mips/include/asm/io.h | 18 +- arch/mips/include/asm/posix_types.h | 12 +- board/qemu-mips/config.mk |3 +- board/qemu-mips/u-boot.lds |8 + boards.cfg |1 + examples/standalone/mips64.lds | 59 ++ include/configs/qemu-mips64.h | 171 16 files changed, 1000 insertions(+), 6 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 05/16] add cpu/mips64/interrupts.c
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips64/interrupts.c | 39 +
1 file changed, 39 insertions(+)
create mode 100644 arch/mips/cpu/mips64/interrupts.c
diff --git a/arch/mips/cpu/mips64/interrupts.c
b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644
index 000..f661fb0
--- /dev/null
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ * Zhi-zhou Zhang etou...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mipsregs.h
+
+void enable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status | ST0_IE);
+}
+
+int disable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status ~ST0_IE);
+ return status | ST0_IE;
+}
--
1.7.9.5
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[U-Boot] [[Patch V2] mips: 11/16] Make size_t equaled to unsigned long
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/include/asm/posix_types.h | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae2..0da1dde 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,9 +24,15 @@ typedef int __kernel_pid_t; typedef int__kernel_ipc_pid_t; typedef int__kernel_uid_t; typedef int__kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int__kernel_ssize_t; -typedef int__kernel_ptrdiff_t; +#ifndef CONFIG_MIPS64 + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + typedef int __kernel_ptrdiff_t; +#else +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 13/16] add board define in boards.cfg
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- boards.cfg |1 + 1 file changed, 1 insertion(+) diff --git a/boards.cfg b/boards.cfg index fdb84ad..a6806b8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,6 +379,7 @@ M5485GFE m68kmcf547x_8x m548xevb freescale - M5485HFEm68kmcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=1,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO microblaze-generic microblaze microblaze microblaze-generic xilinx qemu_mipsmipsmips32 qemu-mips - - qemu-mips +qemu_mips64 mipsmips64 qemu-mips - - qemu-mips64 vct_platinum mipsmips32 vct micronas - vct:VCT_PLATINUM vct_platinumavc mipsmips32 vct micronas - vct:VCT_PLATINUMAVC vct_platinumavc_onenand mipsmips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 03/16] add cpu/mips64/config.mk
Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/config.mk | 39 +++ 1 file changed, 39 insertions(+) create mode 100644 arch/mips/cpu/mips64/config.mk diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 000..26f79e6 --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +PLATFORM_LDFLAGS += -m elf64ltsmip + -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [[Patch V2] mips: 04/16] add cpu/mips64/cpu.c
add icache and dcache probe here. but scache was not probed. For
I don't know how to determine it implemented or not.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips64/cpu.c | 133
1 file changed, 133 insertions(+)
create mode 100644 arch/mips/cpu/mips64/cpu.c
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 000..ea9c28a
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ * Zhi-zhou Zhang etou...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include command.h
+#include netdev.h
+#include asm/mipsregs.h
+#include asm/cacheops.h
+#include asm/reboot.h
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ .setpush\n \
+ .setnoreorder \n \
+ .setmips64\n\t \n \
+ cache %0, %1 \n \
+ .setpop \n \
+ : \
+ : i (op), R (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ fprintf(stderr, *** reset failed ***\n);
+ return 0;
+}
+
+static struct cache_desc icache, dcache;
+
+void cache_probe()
+{
+ int config, lsize;
+
+ config = read_c0_config1();
+ lsize = (config 19) 7;
+ if (lsize) { /* icache present */
+ icache.linesz = 2 lsize;
+ icache.sets = 32 (((config 22) + 1) 7);
+ icache.ways = 1 + ((config 16) 7);
+ icache.size = icache.sets *
+ icache.ways *
+ icache.linesz;
+ }
+
+ lsize = (config 10) 7;
+ if (lsize) { /* dcache present */
+ dcache.linesz = 2 lsize;
+ dcache.sets = 32 (((config 13) + 1) 7);
+ dcache.ways = 1 + ((config 7) 7);
+ dcache.size = dcache.sets *
+ dcache.ways *
+ dcache.linesz;
+ }
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long addr, aend;
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ addr = start_addr ~(icache.linesz - 1);
+ aend = (start_addr + size - 1) ~(icache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Invalidate_I, addr);
+ if (addr == aend)
+ break;
+ addr += icache.linesz;
+ }
+
+ addr = start_addr ~(dcache.linesz - 1);
+ aend = (start_addr + size - 1) ~(dcache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Invalidate_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
--
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[U-Boot] [[Patch V2] mips: 16/16] modify qemu-mips/config.mk
Though I defined CONFIG_SYS_TEXT_BASE in configs/qemu-mips64.h, but the value is still affected by this file. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- board/qemu-mips/config.mk |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk index 27cd34a..a1514a0 100644 --- a/board/qemu-mips/config.mk +++ b/board/qemu-mips/config.mk @@ -2,9 +2,10 @@ # Qemu -M mips system emulator # See http://fabrice.bellard.free.fr/qemu # - +ifeq $(CPU) mips # ROM version CONFIG_SYS_TEXT_BASE = 0xbfc0 # RAM version #CONFIG_SYS_TEXT_BASE = 0x80001000 +endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
