Re: [PATCH 2/2] pci: Add Rockchip dwc based PCIe controller driver【请注意，邮件由s...@google.com代发】

[Simon Glass]

Hi Shawn,

On Fri, 15 Jan 2021 at 02:15, Shawn Lin  wrote:
>
> Hi Simon
>
> Thanks you for  reviewing it.
>
> 在 2021/1/14 23:42, Simon Glass 写道:
> > Hi Shawn,
> >
> > On Thu, 14 Jan 2021 at 01:15, Shawn Lin  wrote:
> >>
>
> 8<--
>
> >> +
> >> +static int rockchip_pcie_init_port(struct udevice *dev)
> >> +{
> >> +   int ret;
> >> +   u32 val;
> >> +   struct rk_pcie *priv = dev_get_priv(dev);
> >> +
> >> +   /* Set power and maybe external ref clk input */
> >> +   if (priv->vpcie3v3) {
> >> +   ret = regulator_set_value(priv->vpcie3v3, 330);
> >
> > Is there an autoset option for this so this info can go in the device
> > tree instead?
>
> I think we should control this by driver as other PCIe drivers did, as
> we can't guarantee all kernel dtbs doing the right thing and 3v3 power
> is very important for both of devices and PHY block.

That's OK. Note that U-Boot uses its own devicetree so you can make
sure it is correct in a separate patch if you like.

Regards,
Simon

Re: [PATCH 2/2] pci: Add Rockchip dwc based PCIe controller driver【请注意，邮件由s...@google.com代发】

[Shawn Lin]

Hi Simon

Thanks you for  reviewing it.

在 2021/1/14 23:42, Simon Glass 写道:

Hi Shawn,

On Thu, 14 Jan 2021 at 01:15, Shawn Lin  wrote:




8<--


+
+static int rockchip_pcie_init_port(struct udevice *dev)
+{
+   int ret;
+   u32 val;
+   struct rk_pcie *priv = dev_get_priv(dev);
+
+   /* Set power and maybe external ref clk input */
+   if (priv->vpcie3v3) {
+   ret = regulator_set_value(priv->vpcie3v3, 330);


Is there an autoset option for this so this info can go in the device
tree instead?


I think we should control this by driver as other PCIe drivers did, as
we can't guarantee all kernel dtbs doing the right thing and 3v3 power
is very important for both of devices and PHY block.




+   if (ret) {
+   dev_err(priv->dev, "failed to enable vpcie3v3 
(ret=%d)\n",
+   ret);
+   return ret;






Regards,
Simon