Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
Hi, On Wed, 1 Mar 2023 at 01:25, Eugen Hristev wrote: > > On 2/14/23 00:27, Chris Morgan wrote: > > From: Chris Morgan > > > > Add support for the newer GPIO controller used by the rk356x series, > > as well as the pinctrl device for the rk356x series. The GPIOv2 > > controller has a write enable bit for some registers which differs > > from the older versions of the GPIO controller. > > > > Signed-off-by: Peter Geis > > Signed-off-by: Chris Morgan > > Hi Chris, > > In the file below you have added > > > + * Jianqun Xu, Software Engineering, . > > as copyright owner, maybe add him as co-author of this patch ? Or what > was his contribution ? > > > > --- > > arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++ > > drivers/gpio/rk_gpio.c| 49 +- > > drivers/pinctrl/rockchip/Makefile | 1 + > > drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++ > > .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +- > > 5 files changed, 540 insertions(+), 13 deletions(-) > > create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c > > > > diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h > > b/arch/arm/include/asm/arch-rockchip/gpio.h > > index 1aaec5faec..15f5de321b 100644 > > --- a/arch/arm/include/asm/arch-rockchip/gpio.h > > +++ b/arch/arm/include/asm/arch-rockchip/gpio.h > > @@ -6,6 +6,7 @@ > > #ifndef _ASM_ARCH_GPIO_H > > #define _ASM_ARCH_GPIO_H > > > > +#if !defined(CONFIG_ROCKCHIP_RK3568) > > Can't we figure out from the compatible which struct layout to use ? > Using conditionally compile code makes things difficult to read after > some time. Yes, we must not add arch-specific CONFIG things to drivers. Handle it at runtime instead, i.e. the driver should handle both. Regards, SImon
Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
On 2/14/23 00:27, Chris Morgan wrote:
From: Chris Morgan
Add support for the newer GPIO controller used by the rk356x series,
as well as the pinctrl device for the rk356x series. The GPIOv2
controller has a write enable bit for some registers which differs
from the older versions of the GPIO controller.
Signed-off-by: Peter Geis
Signed-off-by: Chris Morgan
Hi Chris,
In the file below you have added
> + * Jianqun Xu, Software Engineering, .
as copyright owner, maybe add him as co-author of this patch ? Or what
was his contribution ?
---
arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
drivers/gpio/rk_gpio.c| 49 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
5 files changed, 540 insertions(+), 13 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h
b/arch/arm/include/asm/arch-rockchip/gpio.h
index 1aaec5faec..15f5de321b 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#if !defined(CONFIG_ROCKCHIP_RK3568)
Can't we figure out from the compatible which struct layout to use ?
Using conditionally compile code makes things difficult to read after
some time.
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
u32 reserved1[(0x60 - 0x54) / 4];
u32 ls_sync;
};
+
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l;/* ADDRESS OFFSET: 0x */
+ u32 swport_dr_h;/* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2];/* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 98a79b5f4d..e2653be058 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2023 Rockchip Electronics
* Peter, Software Engineering, .
+ * Jianqun Xu, Software Engineering, .
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -23,6 +26,35 @@ enum {
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+/*
+ * Newer Rockchip devices have additional registers that must be
+ * accounted for.
+ */
+#if defined(CONFIG_ROCKCHIP_RK3568)
+#define GPIO_VER 2
Why don't you use the gpio versioning from here:
https://git.kernel.org/pu
Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
On Mon, Feb 13, 2023 at 2:30 PM Chris Morgan wrote:
>
> From: Chris Morgan
>
> Add support for the newer GPIO controller used by the rk356x series,
> as well as the pinctrl device for the rk356x series. The GPIOv2
> controller has a write enable bit for some registers which differs
> from the older versions of the GPIO controller.
>
> Signed-off-by: Peter Geis
> Signed-off-by: Chris Morgan
With pinctrl part from
https://patchwork.ozlabs.org/project/uboot/patch/20230217115845.75303-11-ja...@amarulasolutions.com/
Tested-by: Vasily Khoruzhick
> ---
> arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
> drivers/gpio/rk_gpio.c| 49 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++
> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
> 5 files changed, 540 insertions(+), 13 deletions(-)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h
> b/arch/arm/include/asm/arch-rockchip/gpio.h
> index 1aaec5faec..15f5de321b 100644
> --- a/arch/arm/include/asm/arch-rockchip/gpio.h
> +++ b/arch/arm/include/asm/arch-rockchip/gpio.h
> @@ -6,6 +6,7 @@
> #ifndef _ASM_ARCH_GPIO_H
> #define _ASM_ARCH_GPIO_H
>
> +#if !defined(CONFIG_ROCKCHIP_RK3568)
> struct rockchip_gpio_regs {
> u32 swport_dr;
> u32 swport_ddr;
> @@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
> u32 reserved1[(0x60 - 0x54) / 4];
> u32 ls_sync;
> };
> +
> check_member(rockchip_gpio_regs, ls_sync, 0x60);
> +#else
> +struct rockchip_gpio_regs {
> + u32 swport_dr_l;/* ADDRESS OFFSET: 0x */
> + u32 swport_dr_h;/* ADDRESS OFFSET: 0x0004 */
> + u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
> + u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
> + u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
> + u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
> + u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
> + u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
> + u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
> + u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
> + u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
> + u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
> + u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
> + u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
> + u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
> + u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
> + u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
> + u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
> + u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
> + u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
> + u32 int_status; /* ADDRESS OFFSET: 0x0050 */
> + u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
> + u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
> + u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
> + u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
> + u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
> + u32 reserved0068[2];/* ADDRESS OFFSET: 0x0068 */
> + u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
> + u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
> + u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
> +};
> +
> +check_member(rockchip_gpio_regs, ver_id, 0x0078);
> +#endif
>
> enum gpio_pu_pd {
> GPIO_PULL_NORMAL = 0,
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 98a79b5f4d..e2653be058 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -2,12 +2,15 @@
> /*
> * (C) Copyright 2015 Google, Inc
> *
> - * (C) Copyright 2008-2014 Rockchip Electronics
> + * (C) Copyright 2008-2023 Rockchip Electronics
> * Peter, Software Engineering, .
> + * Jianqun Xu, Software Engineering, .
> */
>
> #include
> #include
> +#include
> +#include
> #include
> #include
> #include
> @@ -23,6 +26,35 @@ enum {
>
> #define OFFSET_TO_BIT(bit) (1UL << (bit))
>
> +/*
> + * Newer Rockchip devices have additional registers that must be
> + * accounted for.
> + */
> +#if defined(CONFIG_ROCKCHIP_RK3568)
> +#define GPIO_VER 2
> +#define REG_L(R) (R##_l)
> +#define REG_H(R) (R##_h)
> +#define
Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
Hi Chris,
For this patch, I have pick below patch instead:
https://patchwork.ozlabs.org/project/uboot/patch/20230217115845.75303-11-ja...@amarulasolutions.com/
For those change other than pinctrl-rk3568.c, please send a new
patch is still available.
Thanks,
- Kever
On 2023/2/14 06:27, Chris Morgan wrote:
From: Chris Morgan
Add support for the newer GPIO controller used by the rk356x series,
as well as the pinctrl device for the rk356x series. The GPIOv2
controller has a write enable bit for some registers which differs
from the older versions of the GPIO controller.
Signed-off-by: Peter Geis
Signed-off-by: Chris Morgan
---
arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
drivers/gpio/rk_gpio.c| 49 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
5 files changed, 540 insertions(+), 13 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h
b/arch/arm/include/asm/arch-rockchip/gpio.h
index 1aaec5faec..15f5de321b 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#if !defined(CONFIG_ROCKCHIP_RK3568)
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
u32 reserved1[(0x60 - 0x54) / 4];
u32 ls_sync;
};
+
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l;/* ADDRESS OFFSET: 0x */
+ u32 swport_dr_h;/* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2];/* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 98a79b5f4d..e2653be058 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2023 Rockchip Electronics
* Peter, Software Engineering, .
+ * Jianqun Xu, Software Engineering, .
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -23,6 +26,35 @@ enum {
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+/*
+ * Newer Rockchip devices have additional registers that must be
+ * accounted for.
+ */
+#if defined(CONFIG_ROCKCHIP_RK3568)
+#define GPIO_VER 2
+#define REG_L(R) (R##_l)
+#define REG_H(R) (R##_h)
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0x) | \
+
Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
On 2023/2/14 06:27, Chris Morgan wrote:
From: Chris Morgan
Add support for the newer GPIO controller used by the rk356x series,
as well as the pinctrl device for the rk356x series. The GPIOv2
controller has a write enable bit for some registers which differs
from the older versions of the GPIO controller.
Signed-off-by: Peter Geis
Signed-off-by: Chris Morgan
With FUKAUMI Naoki's comment apply:
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
drivers/gpio/rk_gpio.c| 49 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
5 files changed, 540 insertions(+), 13 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h
b/arch/arm/include/asm/arch-rockchip/gpio.h
index 1aaec5faec..15f5de321b 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#if !defined(CONFIG_ROCKCHIP_RK3568)
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
u32 reserved1[(0x60 - 0x54) / 4];
u32 ls_sync;
};
+
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l;/* ADDRESS OFFSET: 0x */
+ u32 swport_dr_h;/* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2];/* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 98a79b5f4d..e2653be058 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2023 Rockchip Electronics
* Peter, Software Engineering, .
+ * Jianqun Xu, Software Engineering, .
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -23,6 +26,35 @@ enum {
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+/*
+ * Newer Rockchip devices have additional registers that must be
+ * accounted for.
+ */
+#if defined(CONFIG_ROCKCHIP_RK3568)
+#define GPIO_VER 2
+#define REG_L(R) (R##_l)
+#define REG_H(R) (R##_h)
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0x) | \
+ ((readl(REG_H(REG)) & 0x) << 16))
+#define WRITE_REG(REG, VAL)\
+{\
+ writel(((VAL) & 0x) | 0x, REG_L(REG)); \
+ writelVAL) & 0x) >> 16) | 0x
Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
hi,
On 2/14/23 07:27, Chris Morgan wrote:
From: Chris Morgan
Add support for the newer GPIO controller used by the rk356x series,
as well as the pinctrl device for the rk356x series. The GPIOv2
controller has a write enable bit for some registers which differs
from the older versions of the GPIO controller.
Signed-off-by: Peter Geis
Signed-off-by: Chris Morgan
---
arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
drivers/gpio/rk_gpio.c| 49 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
5 files changed, 540 insertions(+), 13 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h
b/arch/arm/include/asm/arch-rockchip/gpio.h
index 1aaec5faec..15f5de321b 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#if !defined(CONFIG_ROCKCHIP_RK3568)
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
u32 reserved1[(0x60 - 0x54) / 4];
u32 ls_sync;
};
+
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l;/* ADDRESS OFFSET: 0x */
+ u32 swport_dr_h;/* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2];/* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 98a79b5f4d..e2653be058 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2023 Rockchip Electronics
* Peter, Software Engineering, .
+ * Jianqun Xu, Software Engineering, .
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -23,6 +26,35 @@ enum {
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+/*
+ * Newer Rockchip devices have additional registers that must be
+ * accounted for.
+ */
+#if defined(CONFIG_ROCKCHIP_RK3568)
+#define GPIO_VER 2
+#define REG_L(R) (R##_l)
+#define REG_H(R) (R##_h)
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0x) | \
+ ((readl(REG_H(REG)) & 0x) << 16))
+#define WRITE_REG(REG, VAL)\
+{\
+ writel(((VAL) & 0x) | 0x, REG_L(REG)); \
+ writelVAL) & 0x) >> 16) | 0x, REG_H(REG));\
+}
+#define CLRBITS_LE32(REG, MASK)WRITE_REG(REG, READ
[PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
From: Chris Morgan
Add support for the newer GPIO controller used by the rk356x series,
as well as the pinctrl device for the rk356x series. The GPIOv2
controller has a write enable bit for some registers which differs
from the older versions of the GPIO controller.
Signed-off-by: Peter Geis
Signed-off-by: Chris Morgan
---
arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
drivers/gpio/rk_gpio.c| 49 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
5 files changed, 540 insertions(+), 13 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h
b/arch/arm/include/asm/arch-rockchip/gpio.h
index 1aaec5faec..15f5de321b 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#if !defined(CONFIG_ROCKCHIP_RK3568)
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
u32 reserved1[(0x60 - 0x54) / 4];
u32 ls_sync;
};
+
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l;/* ADDRESS OFFSET: 0x */
+ u32 swport_dr_h;/* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2];/* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 98a79b5f4d..e2653be058 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2023 Rockchip Electronics
* Peter, Software Engineering, .
+ * Jianqun Xu, Software Engineering, .
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -23,6 +26,35 @@ enum {
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+/*
+ * Newer Rockchip devices have additional registers that must be
+ * accounted for.
+ */
+#if defined(CONFIG_ROCKCHIP_RK3568)
+#define GPIO_VER 2
+#define REG_L(R) (R##_l)
+#define REG_H(R) (R##_h)
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0x) | \
+ ((readl(REG_H(REG)) & 0x) << 16))
+#define WRITE_REG(REG, VAL)\
+{\
+ writel(((VAL) & 0x) | 0x, REG_L(REG)); \
+ writelVAL) & 0x) >> 16) | 0x, REG_H(REG));\
+}
+#define CLRBITS_LE32(REG, MASK)WRITE_REG(REG, READ_REG(REG) & ~(MASK))
+#define SETBITS_LE32(REG, MASK)WRITE_REG(REG
