Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On 2023/1/24 8:28, Heinrich Schuchardt wrote: > > > On 1/18/23 09:11, Yanhong Wang wrote: >> This series of patches base on the latest branch/master, and add support >> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for >> this to be achieved, the respective DT nodes have been added, and the >> required defconfigs have been added to the boards' defconfig. What is more, >> the basic required DM drivers have been added, such as reset, clock, pinctrl, >> uart, ram etc. >> >> Note that the register base address of reset controller is same with the >> clock controller. Therefore, there is no device tree node alone for reset >> driver. It binds device node in the clock driver. >> >> The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which >> equip with JH7110 SoC and works normally. >> >> For more information and support, you can visit RVspace wiki[1]. > > Hello Yanhong, > > Which version of OpenSBI is needed for this series to work? > > Could you, please, provide a file in doc/board/starfive/ describing how to > build and install U-Boot on the board. > > Is tool create_sbl from https://github.com/starfive-tech/Tools still > required? Can the source code for that tool be made available? Ideally this > would be integrated into binman. > > This is what I have in my notes: > > cd Tools && \ > ./create_sbl $(uboot_wrkdir)/spl/u-boot-spl.bin 0x01010101 > Thanks. Yes, u-boot-spl.bin also need to be converted by the create_sbl tool. The source code of the tool has been available. View details [1] I will add doc/board/starfive/visionfive2.rst to describe how to build and install u-boot on the board in the next version. [1] https://github.com/starfive-tech/Tools/tree/master/spl_tool > Best regards > > Heinrich > >> >> [1] https://wiki.rvspace.org/ >> >> Changes in v2: >> - Renamed file 'jh7110-regs.h' to 'regs.h'. >> - Reworded the clear L2 LIM memory code in C. >> - Removed flash init call in 'spl_soc_init' function. >> - Reworded the clock driver. >> - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. >> - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to >> 'starfive_visionfive2-u-boot.dtsi'. >> >> Previous versions: >> v1 - >> https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ >> >> Jianlong Huang (1): >> dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions >> >> Kuan Lim Lee (1): >> pinctrl: starfive: Add StarFive JH7110 driver >> >> Yanhong Wang (15): >> riscv: cpu: jh7110: Add support for jh7110 SoC >> cache: starfive: Add StarFive JH7110 support >> dt-bindings: reset: Add StarFive JH7110 reset definitions >> reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC >> dt-bindings: clock: Add StarFive JH7110 clock definitions >> clk: starfive: Add StarFive JH7110 clock driver >> ram: starfive: add ddr driver >> board: starfive: add StarFive VisionFive v2 board support >> riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC >> board: starfive: Add Kconfig for StarFive VisionFive v2 Board >> board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig >> riscv: dts: jh7110: Add initial StarFive JH7110 device tree >> riscv: dts: jh7110: Add initial u-boot device tree >> riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device >> tree >> configs: starfive: add starfive_visionfive2_defconfig >> >> arch/riscv/Kconfig | 5 + >> arch/riscv/cpu/jh7110/Kconfig | 28 + >> arch/riscv/cpu/jh7110/Makefile | 10 + >> arch/riscv/cpu/jh7110/cpu.c | 23 + >> arch/riscv/cpu/jh7110/dram.c | 38 + >> arch/riscv/cpu/jh7110/spl.c | 64 + >> arch/riscv/dts/Makefile | 2 +- >> arch/riscv/dts/jh7110-u-boot.dtsi | 72 + >> arch/riscv/dts/jh7110.dtsi | 497 + >> .../dts/starfive_visionfive2-u-boot.dtsi | 84 + >> arch/riscv/dts/starfive_visionfive2.dts | 234 ++ >> arch/riscv/include/asm/arch-jh7110/regs.h | 19 + >> arch/riscv/include/asm/arch-jh7110/spl.h | 12 + >> board/starfive/visionfive2/Kconfig | 53 + >> board/starfive/visionfive2/MAINTAINERS | 7 + >> board/starfive/visionfive2/Makefile | 7 + >> board/starfive/visionfive2/spl.c | 118 + >> .../visionfive2/starfive_visionfive2.c | 38 + >> configs/starfive_visionfive2_defconfig | 72 + >> drivers/cache/cache-sifive-ccache.c | 1 + >> drivers/clk/Kconfig | 1 + >> drivers/clk/Makefile | 1 + >> drivers/clk/starfive/Kconfig | 17 + >> drivers/clk/starfive/Makefile | 4 + >> drivers/clk/starfive/clk-jh7110-pll.c | 293 +++ >>
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On 2023/1/22 5:56, Sean Anderson wrote: > On 1/21/23 16:36, Conor Dooley wrote: >> On Wed, Jan 18, 2023 at 04:11:15PM +0800, Yanhong Wang wrote: >>> This series of patches base on the latest branch/master, and add support >>> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for >>> this to be achieved, the respective DT nodes have been added, and the >>> required defconfigs have been added to the boards' defconfig. What is more, >>> the basic required DM drivers have been added, such as reset, clock, >>> pinctrl, >>> uart, ram etc. >>> >>> Note that the register base address of reset controller is same with the >>> clock controller. Therefore, there is no device tree node alone for reset >>> driver. It binds device node in the clock driver. >>> >>> The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which >>> equip with JH7110 SoC and works normally. >>> >>> For more information and support, you can visit RVspace wiki[1]. >>> >>> [1] https://wiki.rvspace.org/ >>> >>> Changes in v2: >>> - Renamed file 'jh7110-regs.h' to 'regs.h'. >>> - Reworded the clear L2 LIM memory code in C. >>> - Removed flash init call in 'spl_soc_init' function. >>> - Reworded the clock driver. >>> - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. >>> - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to >>> 'starfive_visionfive2-u-boot.dtsi'. >>> >>> Previous versions: >>> v1 - >>> https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ >>> >>> Jianlong Huang (1): >>> dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions >>> >>> Kuan Lim Lee (1): >>> pinctrl: starfive: Add StarFive JH7110 driver >>> >>> Yanhong Wang (15): >>> riscv: cpu: jh7110: Add support for jh7110 SoC >>> cache: starfive: Add StarFive JH7110 support >>> dt-bindings: reset: Add StarFive JH7110 reset definitions >>> reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC >>> dt-bindings: clock: Add StarFive JH7110 clock definitions >>> clk: starfive: Add StarFive JH7110 clock driver >>> ram: starfive: add ddr driver >>> board: starfive: add StarFive VisionFive v2 board support >>> riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC >>> board: starfive: Add Kconfig for StarFive VisionFive v2 Board >>> board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig >>> riscv: dts: jh7110: Add initial StarFive JH7110 device tree >>> riscv: dts: jh7110: Add initial u-boot device tree >>> riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device >>> tree >>> configs: starfive: add starfive_visionfive2_defconfig >> >> Apologies if I have missed it somewhere - but where is patch 12? >> I don't see it on lore.kernel.org nor in my inbox :( >> >> Thanks, >> Conor. >> > > https://lore.kernel.org/all/20230118082907.31629-1-yanhong.w...@starfivetech.com/ > > Not sure why it isn't with the rest of the series. > It was reported send fail when sending patch 12, so it was sent separately later > --Sean
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On Sun, Jan 22, 2023 at 06:42:04PM +, Conor Dooley wrote: > On Sat, Jan 21, 2023 at 10:05:47PM +, Conor Dooley wrote: > > > > Apologies if I have missed it somewhere - but where is patch 12? > > > > I don't see it on lore.kernel.org nor in my inbox :( > > > > > https://lore.kernel.org/all/20230118082907.31629-1-yanhong.w...@starfivetech.com/ > > > > Oh, thanks! Hopefully I can provide a tested-by so... > > Well it gets to console etc and there's not really much more than that > to really test until some of the peripheral support patches arrive. > Ethernet in particular would be great ;). So for non-SPL: > Tested-by: Conor Dooley > > I can't test the SPL though unfortunately, as the program required to > "package" it has no source code AFAICT and doesn't run on my system. StarFive released the source for this yesterday [1] and I was able to successfully test the SPL too. Happy upgrade my qualified tested-by to one for the whole series: Tested-by: Conor Dooley This patchset is far more stable than the SPL shipped with the board, which I suspect has issues with "training"/initialisation of the DDR. U-Boot proper was boot looping during either tftp or bootm loados more than 90% of the time with the SPL the vendor ships but seems to be stable with this version? It is with fingers crossed at the very least. Cheers, Conor. 1 - https://github.com/starfive-tech/Tools/tree/master/spl_tool > > > Not sure why it isn't with the rest of the series. > > > > Ehh, well it seems to be missing an In-Reply-To header, so perhaps it > > was missing from the directory or w/e they ran send-email from & only > > sent at a later date. > > > > FWIW Yanhong, git send-email allows you to set that header so that > > things do get threaded properly. AFAIU it's --in-reply-to= > > > > Happy New Year, > > Conor. > > > > signature.asc Description: PGP signature
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On Mon, Feb 6, 2023 at 3:39 PM Jan Kiszka wrote: > > On 18.01.23 09:11, Yanhong Wang wrote: > > This series of patches base on the latest branch/master, and add support > > for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for > > this to be achieved, the respective DT nodes have been added, and the > > required defconfigs have been added to the boards' defconfig. What is more, > > the basic required DM drivers have been added, such as reset, clock, > > pinctrl, > > uart, ram etc. > > > > Note that the register base address of reset controller is same with the > > clock controller. Therefore, there is no device tree node alone for reset > > driver. It binds device node in the clock driver. > > > > The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which > > equip with JH7110 SoC and works normally. > > > > For more information and support, you can visit RVspace wiki[1]. > > > > [1] https://wiki.rvspace.org/ > > I'm missing a doc/board/starfive/visionfive2.rst in this, similar to > what we did with doc/board/siemens/iot2050.rst (and many others as well). > > I would also suggest adding binman support so that a flash.bin (or > however you call it) is generated that contains the completely ingrated > firmware, consisting of U-Boot SPL, OpenSBI and U-Boot proper. Would > avoid having to model the details downstream in Yocto, Isar, etc. > Indeed, I see Simon requested in another thread asking binman update for SiFive boards. Adding binman support would be nice! Regards, Bin
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On 18.01.23 09:11, Yanhong Wang wrote: > This series of patches base on the latest branch/master, and add support > for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for > this to be achieved, the respective DT nodes have been added, and the > required defconfigs have been added to the boards' defconfig. What is more, > the basic required DM drivers have been added, such as reset, clock, pinctrl, > uart, ram etc. > > Note that the register base address of reset controller is same with the > clock controller. Therefore, there is no device tree node alone for reset > driver. It binds device node in the clock driver. > > The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which > equip with JH7110 SoC and works normally. > > For more information and support, you can visit RVspace wiki[1]. > > [1] https://wiki.rvspace.org/ I'm missing a doc/board/starfive/visionfive2.rst in this, similar to what we did with doc/board/siemens/iot2050.rst (and many others as well). I would also suggest adding binman support so that a flash.bin (or however you call it) is generated that contains the completely ingrated firmware, consisting of U-Boot SPL, OpenSBI and U-Boot proper. Would avoid having to model the details downstream in Yocto, Isar, etc. Jan -- Siemens AG, Technology Competence Center Embedded Linux
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On Jan 18 2023, Yanhong Wang wrote: > This series of patches base on the latest branch/master, and add support > for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for > this to be achieved, the respective DT nodes have been added, and the > required defconfigs have been added to the boards' defconfig. What is more, > the basic required DM drivers have been added, such as reset, clock, pinctrl, > uart, ram etc. > > Note that the register base address of reset controller is same with the > clock controller. Therefore, there is no device tree node alone for reset > driver. It binds device node in the clock driver. > > The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which > equip with JH7110 SoC and works normally. I tried to put that on an SD card for testing and boot from it, but the SPL cannot read it, thus fails to load U-Boot proper. U-Boot SPL 2023.01-00735-gc8fc99adce (Jan 24 2023 - 15:11:27 +0100) DDR version: dc2e84f0. Trying to boot from MMC2 spl: partition error SPL: failed to boot from all boot devices -- Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different."
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On 1/18/23 09:11, Yanhong Wang wrote: This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. Hello Yanhong, Which version of OpenSBI is needed for this series to work? Could you, please, provide a file in doc/board/starfive/ describing how to build and install U-Boot on the board. Is tool create_sbl from https://github.com/starfive-tech/Tools still required? Can the source code for that tool be made available? Ideally this would be integrated into binman. This is what I have in my notes: cd Tools && \ ./create_sbl $(uboot_wrkdir)/spl/u-boot-spl.bin 0x01010101 Best regards Heinrich [1] https://wiki.rvspace.org/ Changes in v2: - Renamed file 'jh7110-regs.h' to 'regs.h'. - Reworded the clear L2 LIM memory code in C. - Removed flash init call in 'spl_soc_init' function. - Reworded the clock driver. - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to 'starfive_visionfive2-u-boot.dtsi'. Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add starfive_visionfive2_defconfig arch/riscv/Kconfig|5 + arch/riscv/cpu/jh7110/Kconfig | 28 + arch/riscv/cpu/jh7110/Makefile| 10 + arch/riscv/cpu/jh7110/cpu.c | 23 + arch/riscv/cpu/jh7110/dram.c | 38 + arch/riscv/cpu/jh7110/spl.c | 64 + arch/riscv/dts/Makefile |2 +- arch/riscv/dts/jh7110-u-boot.dtsi | 72 + arch/riscv/dts/jh7110.dtsi| 497 + .../dts/starfive_visionfive2-u-boot.dtsi | 84 + arch/riscv/dts/starfive_visionfive2.dts | 234 ++ arch/riscv/include/asm/arch-jh7110/regs.h | 19 + arch/riscv/include/asm/arch-jh7110/spl.h | 12 + board/starfive/visionfive2/Kconfig| 53 + board/starfive/visionfive2/MAINTAINERS|7 + board/starfive/visionfive2/Makefile |7 + board/starfive/visionfive2/spl.c | 118 + .../visionfive2/starfive_visionfive2.c| 38 + configs/starfive_visionfive2_defconfig| 72 + drivers/cache/cache-sifive-ccache.c |1 + drivers/clk/Kconfig |1 + drivers/clk/Makefile |1 + drivers/clk/starfive/Kconfig | 17 + drivers/clk/starfive/Makefile |4 + drivers/clk/starfive/clk-jh7110-pll.c | 293 +++ drivers/clk/starfive/clk-jh7110.c | 559 + drivers/clk/starfive/clk.h| 60 + drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/starfive/Kconfig | 16 + drivers/pinctrl/starfive/Makefile |6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 + drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 drivers/pinctrl/starfive/pinctrl-starfive.c | 428 drivers/pinctrl/starfive/pinctrl-starfive.h | 55 + drivers/ram/Kconfig |1 + drivers/ram/Makefile
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On Sat, Jan 21, 2023 at 10:05:47PM +, Conor Dooley wrote: > > > Apologies if I have missed it somewhere - but where is patch 12? > > > I don't see it on lore.kernel.org nor in my inbox :( > > > https://lore.kernel.org/all/20230118082907.31629-1-yanhong.w...@starfivetech.com/ > > Oh, thanks! Hopefully I can provide a tested-by so... Well it gets to console etc and there's not really much more than that to really test until some of the peripheral support patches arrive. Ethernet in particular would be great ;). So for non-SPL: Tested-by: Conor Dooley I can't test the SPL though unfortunately, as the program required to "package" it has no source code AFAICT and doesn't run on my system. Thanks, Conor. > > Not sure why it isn't with the rest of the series. > > Ehh, well it seems to be missing an In-Reply-To header, so perhaps it > was missing from the directory or w/e they ran send-email from & only > sent at a later date. > > FWIW Yanhong, git send-email allows you to set that header so that > things do get threaded properly. AFAIU it's --in-reply-to= > > Happy New Year, > Conor. > signature.asc Description: PGP signature
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
> > Apologies if I have missed it somewhere - but where is patch 12? > > I don't see it on lore.kernel.org nor in my inbox :( > https://lore.kernel.org/all/20230118082907.31629-1-yanhong.w...@starfivetech.com/ Oh, thanks! Hopefully I can provide a tested-by so... > Not sure why it isn't with the rest of the series. Ehh, well it seems to be missing an In-Reply-To header, so perhaps it was missing from the directory or w/e they ran send-email from & only sent at a later date. FWIW Yanhong, git send-email allows you to set that header so that things do get threaded properly. AFAIU it's --in-reply-to= Happy New Year, Conor. signature.asc Description: PGP signature
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On 1/21/23 16:36, Conor Dooley wrote: On Wed, Jan 18, 2023 at 04:11:15PM +0800, Yanhong Wang wrote: This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ Changes in v2: - Renamed file 'jh7110-regs.h' to 'regs.h'. - Reworded the clear L2 LIM memory code in C. - Removed flash init call in 'spl_soc_init' function. - Reworded the clock driver. - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to 'starfive_visionfive2-u-boot.dtsi'. Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add starfive_visionfive2_defconfig Apologies if I have missed it somewhere - but where is patch 12? I don't see it on lore.kernel.org nor in my inbox :( Thanks, Conor. https://lore.kernel.org/all/20230118082907.31629-1-yanhong.w...@starfivetech.com/ Not sure why it isn't with the rest of the series. --Sean
Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
On Wed, Jan 18, 2023 at 04:11:15PM +0800, Yanhong Wang wrote: > This series of patches base on the latest branch/master, and add support > for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for > this to be achieved, the respective DT nodes have been added, and the > required defconfigs have been added to the boards' defconfig. What is more, > the basic required DM drivers have been added, such as reset, clock, pinctrl, > uart, ram etc. > > Note that the register base address of reset controller is same with the > clock controller. Therefore, there is no device tree node alone for reset > driver. It binds device node in the clock driver. > > The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which > equip with JH7110 SoC and works normally. > > For more information and support, you can visit RVspace wiki[1]. > > [1] https://wiki.rvspace.org/ > > Changes in v2: > - Renamed file 'jh7110-regs.h' to 'regs.h'. > - Reworded the clear L2 LIM memory code in C. > - Removed flash init call in 'spl_soc_init' function. > - Reworded the clock driver. > - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. > - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to > 'starfive_visionfive2-u-boot.dtsi'. > > Previous versions: > v1 - > https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ > > Jianlong Huang (1): > dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions > > Kuan Lim Lee (1): > pinctrl: starfive: Add StarFive JH7110 driver > > Yanhong Wang (15): > riscv: cpu: jh7110: Add support for jh7110 SoC > cache: starfive: Add StarFive JH7110 support > dt-bindings: reset: Add StarFive JH7110 reset definitions > reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC > dt-bindings: clock: Add StarFive JH7110 clock definitions > clk: starfive: Add StarFive JH7110 clock driver > ram: starfive: add ddr driver > board: starfive: add StarFive VisionFive v2 board support > riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC > board: starfive: Add Kconfig for StarFive VisionFive v2 Board > board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig > riscv: dts: jh7110: Add initial StarFive JH7110 device tree > riscv: dts: jh7110: Add initial u-boot device tree > riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device > tree > configs: starfive: add starfive_visionfive2_defconfig Apologies if I have missed it somewhere - but where is patch 12? I don't see it on lore.kernel.org nor in my inbox :( Thanks, Conor. signature.asc Description: PGP signature
[PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ Changes in v2: - Renamed file 'jh7110-regs.h' to 'regs.h'. - Reworded the clear L2 LIM memory code in C. - Removed flash init call in 'spl_soc_init' function. - Reworded the clock driver. - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to 'starfive_visionfive2-u-boot.dtsi'. Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add starfive_visionfive2_defconfig arch/riscv/Kconfig|5 + arch/riscv/cpu/jh7110/Kconfig | 28 + arch/riscv/cpu/jh7110/Makefile| 10 + arch/riscv/cpu/jh7110/cpu.c | 23 + arch/riscv/cpu/jh7110/dram.c | 38 + arch/riscv/cpu/jh7110/spl.c | 64 + arch/riscv/dts/Makefile |2 +- arch/riscv/dts/jh7110-u-boot.dtsi | 72 + arch/riscv/dts/jh7110.dtsi| 497 + .../dts/starfive_visionfive2-u-boot.dtsi | 84 + arch/riscv/dts/starfive_visionfive2.dts | 234 ++ arch/riscv/include/asm/arch-jh7110/regs.h | 19 + arch/riscv/include/asm/arch-jh7110/spl.h | 12 + board/starfive/visionfive2/Kconfig| 53 + board/starfive/visionfive2/MAINTAINERS|7 + board/starfive/visionfive2/Makefile |7 + board/starfive/visionfive2/spl.c | 118 + .../visionfive2/starfive_visionfive2.c| 38 + configs/starfive_visionfive2_defconfig| 72 + drivers/cache/cache-sifive-ccache.c |1 + drivers/clk/Kconfig |1 + drivers/clk/Makefile |1 + drivers/clk/starfive/Kconfig | 17 + drivers/clk/starfive/Makefile |4 + drivers/clk/starfive/clk-jh7110-pll.c | 293 +++ drivers/clk/starfive/clk-jh7110.c | 559 + drivers/clk/starfive/clk.h| 60 + drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/starfive/Kconfig | 16 + drivers/pinctrl/starfive/Makefile |6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 + drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 drivers/pinctrl/starfive/pinctrl-starfive.c | 428 drivers/pinctrl/starfive/pinctrl-starfive.h | 55 + drivers/ram/Kconfig |1 + drivers/ram/Makefile |4 +- drivers/ram/starfive/Kconfig |5 + drivers/ram/starfive/Makefile | 11 + drivers/ram/starfive/ddrcsr_boot.c| 339 +++ drivers/ram/starfive/ddrphy_start.c | 279 +++ drivers/ram/starfive/ddrphy_train.c | 383 drivers/ram/starfive/ddrphy_utils.c | 1955 + drivers/ram/starfive/starfive_ddr.c | 161 ++ drivers/ram/starfive/starfive_ddr.h | 65 + drivers/reset/Kconfig | 16 + drivers/reset/Makefile|
