Re: [PATCH v2 1/2] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S
Hi Jonas,
On Mon, May 29, 2023 at 11:45 PM Jonas Karlman wrote:
>
> Hi,
>
> On 2023-05-29 06:59, Tianling Shen wrote:
> > FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
> >
> > Board Specifications
> > - Rockchip RK3568
> > - 2 or 4GB LPDDR4X
> > - 8GB or 16GB eMMC, SD card slot
> > - GbE LAN (Native)
> > - 2x 2.5G LAN (PCIe)
> > - M.2 Connector
> > - HDMI 2.0, MIPI DSI/CSI
> > - 2xUSB 3.0 Host
> > - USB Type C PD, 5V/9V/12V
> > - GPIO: 12-pin 0.5mm FPC connector
> >
> > The device tree is taken from kernel v6.4-rc1.
> >
> > Signed-off-by: Tianling Shen
> > ---
> >
> > No changes in v2.
> >
> > ---
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++
> > arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +
> > arch/arm/dts/rk3568-nanopi-r5s.dtsi| 590 +
> > board/rockchip/evb_rk3568/MAINTAINERS | 8 +
> > configs/nanopi-r5s-rk3568_defconfig| 90
> > 6 files changed, 858 insertions(+)
> > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
> > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi
> > create mode 100644 configs/nanopi-r5s-rk3568_defconfig
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 480269fa60..e2eda3ffcb 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
> > rk3566-anbernic-rgxx3.dtb \
> > rk3566-radxa-cm3-io.dtb \
> > rk3568-evb.dtb \
> > + rk3568-nanopi-r5s.dtb \
> > rk3568-rock-3a.dtb
> >
> > dtb-$(CONFIG_ROCKCHIP_RK3588) += \
> > diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> > b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> > new file mode 100644
> > index 00..b37ad1e72d
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> > @@ -0,0 +1,33 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +/*
> > + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
> > + * (http://www.friendlyelec.com)
> > + *
> > + * Copyright (c) 2023 Tianling Shen
> > + */
> > +
> > +#include "rk356x-u-boot.dtsi"
> > +
> > +/ {
> > + chosen {
> > + stdout-path =
> > + u-boot,spl-boot-order = "same-as-spl", ,
> > + };
> > +};
> > +
> > + {
> > + cap-mmc-highspeed;
> > + mmc-hs200-1_8v;
> > +};
>
> Because this is a rk3568 you can probably also add:
>
> mmc-ddr-1_8v;
> mmc-hs400-1_8v;
> mmc-hs400-enhanced-strobe;
>
> and a pinctrl with emmc_datastrobe according to schematic:
>
> pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
>
> > +
> > + {
> > + bus-width = <4>;
> > + bootph-pre-ram;
> > + u-boot,spl-fifo-mode;
> > +};
>
> The sdmmc0 node is not needed:
> - bus-width is set in linux dts
> - bootph-pre-ram is set in rk356x-u-boot.dtsi
> - u-boot,spl-fifo-mode is not needed on rk356x
>
> > +
> > + {
> > + clock-frequency = <2400>;
> > + bootph-pre-ram;
>
> Recommended to be bootph-all, in case TPL support gets added in future.
>
Thank you so much for all of these explanations and suggestions!
I will test them later today and send v3.
Thanks,
Tianling.
> > + status = "okay";
> > +};
>
> [snip]
>
> > diff --git a/board/rockchip/evb_rk3568/MAINTAINERS
> > b/board/rockchip/evb_rk3568/MAINTAINERS
> > index 6b2e7c7575..9222682461 100644
> > --- a/board/rockchip/evb_rk3568/MAINTAINERS
> > +++ b/board/rockchip/evb_rk3568/MAINTAINERS
> > @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig
> > F: arch/arm/dts/rk3568-evb-boot.dtsi
> > F: arch/arm/dts/rk3568-evb.dts
> >
> > +NANOPI-R5S
> > +M: Tianling Shen
> > +S: Maintained
> > +F: configs/nanopi-r5s-rk3568_defconfig
> > +F: arch/arm/dts/rk3568-nanopi-r5s.dts
> > +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi
> > +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> > +
> > RADXA-CM3
> > M: Jagan Teki
> > S: Maintained
> > diff --git a/configs/nanopi-r5s-rk3568_defconfig
> > b/configs/nanopi-r5s-rk3568_defconfig
> > new file mode 100644
> > index 00..041fa6d84f
> > --- /dev/null
> > +++ b/configs/nanopi-r5s-rk3568_defconfig
> > @@ -0,0 +1,90 @@
> > +CONFIG_ARM=y
> > +CONFIG_SKIP_LOWLEVEL_INIT=y
> > +CONFIG_COUNTER_FREQUENCY=2400
> > +CONFIG_ARCH_ROCKCHIP=y
> > +CONFIG_TEXT_BASE=0x00a0
> > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > +CONFIG_NR_DRAM_BANKS=2
> > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
> > +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
> > +CONFIG_ROCKCHIP_RK3568=y
> > +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
> > +CONFIG_SPL_SERIAL=y
> > +CONFIG_SPL_STACK_R_ADDR=0x60
> > +CONFIG_TARGET_EVB_RK3568=y
> > +CONFIG_SPL_STACK=0x40
> > +CONFIG_DEBUG_UART_BASE=0xFE66
> > +CONFIG_DEBUG_UART_CLOCK=2400
> > +CONFIG_SYS_LOAD_ADDR=0xc00800
> > +CONFIG_DEBUG_UART=y
Re: [PATCH v2 1/2] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S
Hi,
On 2023-05-29 06:59, Tianling Shen wrote:
> FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
>
> Board Specifications
> - Rockchip RK3568
> - 2 or 4GB LPDDR4X
> - 8GB or 16GB eMMC, SD card slot
> - GbE LAN (Native)
> - 2x 2.5G LAN (PCIe)
> - M.2 Connector
> - HDMI 2.0, MIPI DSI/CSI
> - 2xUSB 3.0 Host
> - USB Type C PD, 5V/9V/12V
> - GPIO: 12-pin 0.5mm FPC connector
>
> The device tree is taken from kernel v6.4-rc1.
>
> Signed-off-by: Tianling Shen
> ---
>
> No changes in v2.
>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++
> arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +
> arch/arm/dts/rk3568-nanopi-r5s.dtsi| 590 +
> board/rockchip/evb_rk3568/MAINTAINERS | 8 +
> configs/nanopi-r5s-rk3568_defconfig| 90
> 6 files changed, 858 insertions(+)
> create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
> create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi
> create mode 100644 configs/nanopi-r5s-rk3568_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 480269fa60..e2eda3ffcb 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
> rk3566-anbernic-rgxx3.dtb \
> rk3566-radxa-cm3-io.dtb \
> rk3568-evb.dtb \
> + rk3568-nanopi-r5s.dtb \
> rk3568-rock-3a.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RK3588) += \
> diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> new file mode 100644
> index 00..b37ad1e72d
> --- /dev/null
> +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
> + * (http://www.friendlyelec.com)
> + *
> + * Copyright (c) 2023 Tianling Shen
> + */
> +
> +#include "rk356x-u-boot.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path =
> + u-boot,spl-boot-order = "same-as-spl", ,
> + };
> +};
> +
> + {
> + cap-mmc-highspeed;
> + mmc-hs200-1_8v;
> +};
Because this is a rk3568 you can probably also add:
mmc-ddr-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
and a pinctrl with emmc_datastrobe according to schematic:
pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
> +
> + {
> + bus-width = <4>;
> + bootph-pre-ram;
> + u-boot,spl-fifo-mode;
> +};
The sdmmc0 node is not needed:
- bus-width is set in linux dts
- bootph-pre-ram is set in rk356x-u-boot.dtsi
- u-boot,spl-fifo-mode is not needed on rk356x
> +
> + {
> + clock-frequency = <2400>;
> + bootph-pre-ram;
Recommended to be bootph-all, in case TPL support gets added in future.
> + status = "okay";
> +};
[snip]
> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS
> b/board/rockchip/evb_rk3568/MAINTAINERS
> index 6b2e7c7575..9222682461 100644
> --- a/board/rockchip/evb_rk3568/MAINTAINERS
> +++ b/board/rockchip/evb_rk3568/MAINTAINERS
> @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig
> F: arch/arm/dts/rk3568-evb-boot.dtsi
> F: arch/arm/dts/rk3568-evb.dts
>
> +NANOPI-R5S
> +M: Tianling Shen
> +S: Maintained
> +F: configs/nanopi-r5s-rk3568_defconfig
> +F: arch/arm/dts/rk3568-nanopi-r5s.dts
> +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi
> +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
> +
> RADXA-CM3
> M: Jagan Teki
> S: Maintained
> diff --git a/configs/nanopi-r5s-rk3568_defconfig
> b/configs/nanopi-r5s-rk3568_defconfig
> new file mode 100644
> index 00..041fa6d84f
> --- /dev/null
> +++ b/configs/nanopi-r5s-rk3568_defconfig
> @@ -0,0 +1,90 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=2400
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_TEXT_BASE=0x00a0
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
> +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
> +CONFIG_ROCKCHIP_RK3568=y
> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL_STACK_R_ADDR=0x60
> +CONFIG_TARGET_EVB_RK3568=y
> +CONFIG_SPL_STACK=0x40
> +CONFIG_DEBUG_UART_BASE=0xFE66
> +CONFIG_DEBUG_UART_CLOCK=2400
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_MAX_SIZE=0x4
> +CONFIG_SPL_PAD_TO=0x7f8000
> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> +CONFIG_SPL_BSS_START_ADDR=0x400
> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> +CONFIG_SPL_STACK_R=y
>
Re: [PATCH v2 1/2] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S
On 2023/5/29 12:59, Tianling Shen wrote:
FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
Board Specifications
- Rockchip RK3568
- 2 or 4GB LPDDR4X
- 8GB or 16GB eMMC, SD card slot
- GbE LAN (Native)
- 2x 2.5G LAN (PCIe)
- M.2 Connector
- HDMI 2.0, MIPI DSI/CSI
- 2xUSB 3.0 Host
- USB Type C PD, 5V/9V/12V
- GPIO: 12-pin 0.5mm FPC connector
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen
Reviewed-by: Kever Yang
Thanks,
- Kever
---
No changes in v2.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++
arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +
arch/arm/dts/rk3568-nanopi-r5s.dtsi| 590 +
board/rockchip/evb_rk3568/MAINTAINERS | 8 +
configs/nanopi-r5s-rk3568_defconfig| 90
6 files changed, 858 insertions(+)
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi
create mode 100644 configs/nanopi-r5s-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..e2eda3ffcb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+ rk3568-nanopi-r5s.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
new file mode 100644
index 00..b37ad1e72d
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+ {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+ {
+ bus-width = <4>;
+ bootph-pre-ram;
+ u-boot,spl-fifo-mode;
+};
+
+ {
+ clock-frequency = <2400>;
+ bootph-pre-ram;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts
b/arch/arm/dts/rk3568-nanopi-r5s.dts
new file mode 100644
index 00..b6ad8328c7
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R5S";
+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 =
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led_pin>, <_led_pin>, <_led_pin>,
<_led_pin>;
+
+ led-lan1 {
+ color = ;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = < RK_PD6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-lan2 {
+ color = ;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = < RK_PD7 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_led: led-power {
+ color = ;
+ function = LED_FUNCTION_POWER;
+ linux,default-trigger = "heartbeat";
+ gpios = < RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ color = ;
+ function = LED_FUNCTION_WAN;
+ gpios = < RK_PC1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+ {
+ assigned-clocks = < SCLK_GMAC0_RX_TX>, < SCLK_GMAC0>;
+ assigned-clock-parents = < SCLK_GMAC0_RGMII_SPEED>, <
CLK_MAC0_2TOP>;
+ assigned-clock-rates = <0>, <12500>;
+ clock_in_out = "output";
+ phy-handle = <_phy0>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <_miim
+_tx_bus2
+_rx_bus2
+_rgmii_clk
+_rgmii_bus>;
+ snps,reset-gpio = < RK_PC5 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 15ms, 50ms for rtl8211f */
+ snps,reset-delays-us = <0 15000 5>;
+ tx_delay = <0x3c>;
+ rx_delay = <0x2f>;
+ status = "okay";
+};
+
+ {
+ rgmii_phy0: ethernet-phy@1 {
+ compatible =
[PATCH v2 1/2] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S
FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
Board Specifications
- Rockchip RK3568
- 2 or 4GB LPDDR4X
- 8GB or 16GB eMMC, SD card slot
- GbE LAN (Native)
- 2x 2.5G LAN (PCIe)
- M.2 Connector
- HDMI 2.0, MIPI DSI/CSI
- 2xUSB 3.0 Host
- USB Type C PD, 5V/9V/12V
- GPIO: 12-pin 0.5mm FPC connector
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen
---
No changes in v2.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++
arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +
arch/arm/dts/rk3568-nanopi-r5s.dtsi| 590 +
board/rockchip/evb_rk3568/MAINTAINERS | 8 +
configs/nanopi-r5s-rk3568_defconfig| 90
6 files changed, 858 insertions(+)
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi
create mode 100644 configs/nanopi-r5s-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..e2eda3ffcb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+ rk3568-nanopi-r5s.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
new file mode 100644
index 00..b37ad1e72d
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+ {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+ {
+ bus-width = <4>;
+ bootph-pre-ram;
+ u-boot,spl-fifo-mode;
+};
+
+ {
+ clock-frequency = <2400>;
+ bootph-pre-ram;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts
b/arch/arm/dts/rk3568-nanopi-r5s.dts
new file mode 100644
index 00..b6ad8328c7
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R5S";
+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 =
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led_pin>, <_led_pin>, <_led_pin>,
<_led_pin>;
+
+ led-lan1 {
+ color = ;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = < RK_PD6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-lan2 {
+ color = ;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = < RK_PD7 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_led: led-power {
+ color = ;
+ function = LED_FUNCTION_POWER;
+ linux,default-trigger = "heartbeat";
+ gpios = < RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ color = ;
+ function = LED_FUNCTION_WAN;
+ gpios = < RK_PC1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+ {
+ assigned-clocks = < SCLK_GMAC0_RX_TX>, < SCLK_GMAC0>;
+ assigned-clock-parents = < SCLK_GMAC0_RGMII_SPEED>, <
CLK_MAC0_2TOP>;
+ assigned-clock-rates = <0>, <12500>;
+ clock_in_out = "output";
+ phy-handle = <_phy0>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <_miim
+_tx_bus2
+_rx_bus2
+_rgmii_clk
+_rgmii_bus>;
+ snps,reset-gpio = < RK_PC5 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 15ms, 50ms for rtl8211f */
+ snps,reset-delays-us = <0 15000 5>;
+ tx_delay = <0x3c>;
+ rx_delay = <0x2f>;
+ status = "okay";
+};
+
+ {
+ rgmii_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ pinctrl-0 = <_phy0_reset_pin>;
+
