Re: [PATCH v5 3/5] riscv: lib: implement enable_caches for sifive cache

[Rick Chen]

> From: Zong Li 
> Sent: Wednesday, September 01, 2021 3:02 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊) 
> ; bmeng...@gmail.com; sean...@gmail.com; 
> green@sifive.com; paul.walms...@sifive.com; s...@chromium.org; 
> u-boot@lists.denx.de
> Cc: Zong Li 
> Subject: [PATCH v5 3/5] riscv: lib: implement enable_caches for sifive cache
>
> The enable_caches is a generic hook for architecture-implemented, we define 
> this function to enable composable cache of sifive platforms.
>
> In sifive_cache, it invokes the generic cache_enable interface of cache 
> uclass to execute the relative implementation in SiFive ccache driver.
>
> Signed-off-by: Zong Li 
> ---
>  arch/riscv/Kconfig|  5 +
>  arch/riscv/lib/Makefile   |  1 +
>  arch/riscv/lib/sifive_cache.c | 27 +++
>  3 files changed, 33 insertions(+)

Reviewed-by: Rick Chen 

[PATCH v5 3/5] riscv: lib: implement enable_caches for sifive cache

[Zong Li]

The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li 
---
 arch/riscv/Kconfig|  5 +
 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/sifive_cache.c | 27 +++
 3 files changed, 33 insertions(+)
 create mode 100644 arch/riscv/lib/sifive_cache.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3dffa6..ec651fe0a4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+   bool
+   help
+ This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index c4cc41434b..06020fcc2a 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
new file mode 100644
index 00..28154878fc
--- /dev/null
+++ b/arch/riscv/lib/sifive_cache.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+void enable_caches(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   /* Enable ways of ccache */
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret) {
+   log_debug("Cannot enable cache ways");
+   } else {
+   ret = cache_enable(dev);
+   if (ret)
+   log_debug("ccache enable failed");
+   }
+}
-- 
2.32.0