Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-19 Thread Marek Vasut
On 12/19/2016 11:34 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote:
>> On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:

 On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
>
>
> On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
>>
>>
>> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
>>>
>>>
>>>
>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:



 On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>
>
>
>
> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>>
>>
>>
>>
>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>
>>>
>>>
>>>
>>>
>>> From: Tien Fong Chee 
>>>
>>> These changes to ensure Arria10 SPL build success.
>> Please reword the commit message, mention you're
>> removing
>> the
>> Arria10
>> bits. Still, this does not even apply on mainline, on
>> top
>> of
>> what
>> does
>> this apply ?
>>
> I disabled some features temporary, so SPL build can
> pass
> and
> print
> out
> working. I will enable these features back in upcoming
> patches.
> This is
> base on 01-arria10 branch.
 But this patch seems to only enable stuff ... ?

>>> Enable the spl. Disable SPI flash temporary, for preventing
>>> build
>>> failed, but this will be enabled back with upcoming patches
>>> for
>>> supporting SPI flash.
>> What's the problem with SPI flash ? I thought it's the same
>> block
>> as
>> in
>> C/A 5 ?
>>
> Some compilation error, but i haven't checked it out what
> errors
> causing the build failed. My plan is to have SPL and print out
> working,
> then following boot from SDMMC, FPGA configuration, DDR up.
> Once
> booting from SDMMC working, i will work to boot from QSPI and
> NAND
> too.
 MW is now closed, so you can focus on fixing the CQSPI too, it
 shouldn't
 be too hard.

>>> What is MW?
>>>
>> Merge Window
> 
> just for comfirmation, are you means rebase to master of u-boot-
> socfpga.git or denx master? I think former,right?
> 
You can use either now, u-boot-socfpga has no patches queued and
u-boot.git is more up-to-date .

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-19 Thread Chee, Tien Fong
On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote:
> On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
> > > 
> > > On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > From: Tien Fong Chee 
> > > > > > > > > > 
> > > > > > > > > > These changes to ensure Arria10 SPL build success.
> > > > > > > > > Please reword the commit message, mention you're
> > > > > > > > > removing
> > > > > > > > > the
> > > > > > > > > Arria10
> > > > > > > > > bits. Still, this does not even apply on mainline, on
> > > > > > > > > top
> > > > > > > > > of
> > > > > > > > > what
> > > > > > > > > does
> > > > > > > > > this apply ?
> > > > > > > > > 
> > > > > > > > I disabled some features temporary, so SPL build can
> > > > > > > > pass
> > > > > > > > and
> > > > > > > > print
> > > > > > > > out
> > > > > > > > working. I will enable these features back in upcoming
> > > > > > > > patches.
> > > > > > > > This is
> > > > > > > > base on 01-arria10 branch.
> > > > > > > But this patch seems to only enable stuff ... ?
> > > > > > > 
> > > > > > Enable the spl. Disable SPI flash temporary, for preventing
> > > > > > build
> > > > > > failed, but this will be enabled back with upcoming patches
> > > > > > for
> > > > > > supporting SPI flash.
> > > > > What's the problem with SPI flash ? I thought it's the same
> > > > > block
> > > > > as
> > > > > in
> > > > > C/A 5 ?
> > > > > 
> > > > Some compilation error, but i haven't checked it out what
> > > > errors
> > > > causing the build failed. My plan is to have SPL and print out
> > > > working,
> > > > then following boot from SDMMC, FPGA configuration, DDR up.
> > > > Once
> > > > booting from SDMMC working, i will work to boot from QSPI and
> > > > NAND
> > > > too.
> > > MW is now closed, so you can focus on fixing the CQSPI too, it
> > > shouldn't
> > > be too hard.
> > > 
> > What is MW?
> > 
> Merge Window

just for comfirmation, are you means rebase to master of u-boot-
socfpga.git or denx master? I think former,right?
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-19 Thread Marek Vasut
On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
>> On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
>>>
>>> On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:

 On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
>
>
> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>>
>>
>> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>>>
>>>
>>>
>>> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:



 On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>
>
>
>
> From: Tien Fong Chee 
>
> These changes to ensure Arria10 SPL build success.
 Please reword the commit message, mention you're removing
 the
 Arria10
 bits. Still, this does not even apply on mainline, on top
 of
 what
 does
 this apply ?

>>> I disabled some features temporary, so SPL build can pass
>>> and
>>> print
>>> out
>>> working. I will enable these features back in upcoming
>>> patches.
>>> This is
>>> base on 01-arria10 branch.
>> But this patch seems to only enable stuff ... ?
>>
> Enable the spl. Disable SPI flash temporary, for preventing
> build
> failed, but this will be enabled back with upcoming patches for
> supporting SPI flash.
 What's the problem with SPI flash ? I thought it's the same block
 as
 in
 C/A 5 ?

>>> Some compilation error, but i haven't checked it out what errors
>>> causing the build failed. My plan is to have SPL and print out
>>> working,
>>> then following boot from SDMMC, FPGA configuration, DDR up. Once
>>> booting from SDMMC working, i will work to boot from QSPI and NAND
>>> too.
>> MW is now closed, so you can focus on fixing the CQSPI too, it
>> shouldn't
>> be too hard.
>>
> What is MW?
> 
Merge Window

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-19 Thread Chee, Tien Fong
On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
> On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
> > 
> > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
> > > 
> > > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > From: Tien Fong Chee 
> > > > > > > > 
> > > > > > > > These changes to ensure Arria10 SPL build success.
> > > > > > > Please reword the commit message, mention you're removing
> > > > > > > the
> > > > > > > Arria10
> > > > > > > bits. Still, this does not even apply on mainline, on top
> > > > > > > of
> > > > > > > what
> > > > > > > does
> > > > > > > this apply ?
> > > > > > > 
> > > > > > I disabled some features temporary, so SPL build can pass
> > > > > > and
> > > > > > print
> > > > > > out
> > > > > > working. I will enable these features back in upcoming
> > > > > > patches.
> > > > > > This is
> > > > > > base on 01-arria10 branch.
> > > > > But this patch seems to only enable stuff ... ?
> > > > > 
> > > > Enable the spl. Disable SPI flash temporary, for preventing
> > > > build
> > > > failed, but this will be enabled back with upcoming patches for
> > > > supporting SPI flash.
> > > What's the problem with SPI flash ? I thought it's the same block
> > > as
> > > in
> > > C/A 5 ?
> > > 
> > Some compilation error, but i haven't checked it out what errors
> > causing the build failed. My plan is to have SPL and print out
> > working,
> > then following boot from SDMMC, FPGA configuration, DDR up. Once
> > booting from SDMMC working, i will work to boot from QSPI and NAND
> > too.
> MW is now closed, so you can focus on fixing the CQSPI too, it
> shouldn't
> be too hard.
> 
What is MW?
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-19 Thread Marek Vasut
On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
> On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
>> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
>>>
>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:

 On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>
>
> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>>
>>
>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>
>>>
>>>
>>> From: Tien Fong Chee 
>>>
>>> These changes to ensure Arria10 SPL build success.
>> Please reword the commit message, mention you're removing the
>> Arria10
>> bits. Still, this does not even apply on mainline, on top of
>> what
>> does
>> this apply ?
>>
> I disabled some features temporary, so SPL build can pass and
> print
> out
> working. I will enable these features back in upcoming patches.
> This is
> base on 01-arria10 branch.
 But this patch seems to only enable stuff ... ?

>>> Enable the spl. Disable SPI flash temporary, for preventing build
>>> failed, but this will be enabled back with upcoming patches for
>>> supporting SPI flash.
>> What's the problem with SPI flash ? I thought it's the same block as
>> in
>> C/A 5 ?
>>
> Some compilation error, but i haven't checked it out what errors
> causing the build failed. My plan is to have SPL and print out working,
> then following boot from SDMMC, FPGA configuration, DDR up. Once
> booting from SDMMC working, i will work to boot from QSPI and NAND
> too.

MW is now closed, so you can focus on fixing the CQSPI too, it shouldn't
be too hard.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-18 Thread Chee, Tien Fong
On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> > 
> > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > 
> > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > These changes to ensure Arria10 SPL build success.
> > > > > Please reword the commit message, mention you're removing the
> > > > > Arria10
> > > > > bits. Still, this does not even apply on mainline, on top of
> > > > > what
> > > > > does
> > > > > this apply ?
> > > > > 
> > > > I disabled some features temporary, so SPL build can pass and
> > > > print
> > > > out
> > > > working. I will enable these features back in upcoming patches.
> > > > This is
> > > > base on 01-arria10 branch.
> > > But this patch seems to only enable stuff ... ?
> > > 
> > Enable the spl. Disable SPI flash temporary, for preventing build
> > failed, but this will be enabled back with upcoming patches for
> > supporting SPI flash.
> What's the problem with SPI flash ? I thought it's the same block as
> in
> C/A 5 ?
> 
Some compilation error, but i haven't checked it out what errors
causing the build failed. My plan is to have SPL and print out working,
then following boot from SDMMC, FPGA configuration, DDR up. Once
booting from SDMMC working, i will work to boot from QSPI and NAND
too.
> 
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-09 Thread Marek Vasut
On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:

 On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>
>
> From: Tien Fong Chee 
>
> These changes to ensure Arria10 SPL build success.
 Please reword the commit message, mention you're removing the
 Arria10
 bits. Still, this does not even apply on mainline, on top of what
 does
 this apply ?

>>> I disabled some features temporary, so SPL build can pass and print
>>> out
>>> working. I will enable these features back in upcoming patches.
>>> This is
>>> base on 01-arria10 branch.
>> But this patch seems to only enable stuff ... ?
>>
> Enable the spl. Disable SPI flash temporary, for preventing build
> failed, but this will be enabled back with upcoming patches for
> supporting SPI flash.

What's the problem with SPI flash ? I thought it's the same block as in
C/A 5 ?


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-09 Thread Chee, Tien Fong
On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > These changes to ensure Arria10 SPL build success.
> > > Please reword the commit message, mention you're removing the
> > > Arria10
> > > bits. Still, this does not even apply on mainline, on top of what
> > > does
> > > this apply ?
> > > 
> > I disabled some features temporary, so SPL build can pass and print
> > out
> > working. I will enable these features back in upcoming patches.
> > This is
> > base on 01-arria10 branch.
> But this patch seems to only enable stuff ... ?
> 
Enable the spl. Disable SPI flash temporary, for preventing build
failed, but this will be enabled back with upcoming patches for
supporting SPI flash.
> > 
> > > 
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > Cc: Marek Vasut 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Chin Liang See 
> > > > Cc: Tien Fong 
> > > > ---
> > > >  arch/arm/Kconfig |8 
> > > >  1 files changed, 4 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index 220bb19..05ce8b8 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
> > > >  config ARCH_SOCFPGA
> > > >     bool "Altera SOCFPGA family"
> > > >     select CPU_V7
> > > > -   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
> > > > +   select SUPPORT_SPL
> > > >     select OF_CONTROL
> > > > -   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
> > > > +   select SPL_OF_CONTROL
> > > >     select DM
> > > > -   select DM_SPI_FLASH
> > > > -   select DM_SPI
> > > > +   select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
> > > > +   select DM_SPI if !TARGET_SOCFPGA_ARRIA10
> > > >  
> > > >  config TARGET_CM_T43
> > > >     bool "Support cm_t43"
> > > > 
> 
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-07 Thread Marek Vasut
On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> These changes to ensure Arria10 SPL build success.
>> Please reword the commit message, mention you're removing the Arria10
>> bits. Still, this does not even apply on mainline, on top of what
>> does
>> this apply ?
>>
> I disabled some features temporary, so SPL build can pass and print out
> working. I will enable these features back in upcoming patches. This is
> base on 01-arria10 branch.

But this patch seems to only enable stuff ... ?

>>> Signed-off-by: Tien Fong Chee 
>>> Cc: Marek Vasut 
>>> Cc: Dinh Nguyen 
>>> Cc: Chin Liang See 
>>> Cc: Tien Fong 
>>> ---
>>>  arch/arm/Kconfig |8 
>>>  1 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>> index 220bb19..05ce8b8 100644
>>> --- a/arch/arm/Kconfig
>>> +++ b/arch/arm/Kconfig
>>> @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
>>>  config ARCH_SOCFPGA
>>> bool "Altera SOCFPGA family"
>>> select CPU_V7
>>> -   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
>>> +   select SUPPORT_SPL
>>> select OF_CONTROL
>>> -   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
>>> +   select SPL_OF_CONTROL
>>> select DM
>>> -   select DM_SPI_FLASH
>>> -   select DM_SPI
>>> +   select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
>>> +   select DM_SPI if !TARGET_SOCFPGA_ARRIA10
>>>  
>>>  config TARGET_CM_T43
>>> bool "Support cm_t43"
>>>


-- 
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Marek Vasut
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-07 Thread Chee, Tien Fong
On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > These changes to ensure Arria10 SPL build success.
> Please reword the commit message, mention you're removing the Arria10
> bits. Still, this does not even apply on mainline, on top of what
> does
> this apply ?
> 
I disabled some features temporary, so SPL build can pass and print out
working. I will enable these features back in upcoming patches. This is
base on 01-arria10 branch.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Chin Liang See 
> > Cc: Tien Fong 
> > ---
> >  arch/arm/Kconfig |8 
> >  1 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 220bb19..05ce8b8 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
> >  config ARCH_SOCFPGA
> >     bool "Altera SOCFPGA family"
> >     select CPU_V7
> > -   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
> > +   select SUPPORT_SPL
> >     select OF_CONTROL
> > -   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
> > +   select SPL_OF_CONTROL
> >     select DM
> > -   select DM_SPI_FLASH
> > -   select DM_SPI
> > +   select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
> > +   select DM_SPI if !TARGET_SOCFPGA_ARRIA10
> >  
> >  config TARGET_CM_T43
> >     bool "Support cm_t43"
> > 
> 
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Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-06 Thread Marek Vasut
On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> These changes to ensure Arria10 SPL build success.

Please reword the commit message, mention you're removing the Arria10
bits. Still, this does not even apply on mainline, on top of what does
this apply ?

> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/Kconfig |8 
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 220bb19..05ce8b8 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
>  config ARCH_SOCFPGA
>   bool "Altera SOCFPGA family"
>   select CPU_V7
> - select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
> + select SUPPORT_SPL
>   select OF_CONTROL
> - select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
> + select SPL_OF_CONTROL
>   select DM
> - select DM_SPI_FLASH
> - select DM_SPI
> + select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
> + select DM_SPI if !TARGET_SOCFPGA_ARRIA10
>  
>  config TARGET_CM_T43
>   bool "Support cm_t43"
> 


-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

2016-12-06 Thread Chee Tien Fong
From: Tien Fong Chee 

These changes to ensure Arria10 SPL build success.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig |8 
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 220bb19..05ce8b8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+   select SUPPORT_SPL
select OF_CONTROL
-   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+   select SPL_OF_CONTROL
select DM
-   select DM_SPI_FLASH
-   select DM_SPI
+   select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
+   select DM_SPI if !TARGET_SOCFPGA_ARRIA10
 
 config TARGET_CM_T43
bool "Support cm_t43"
-- 
1.7.7.4

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