Re: [U-Boot] [PATCH 1/2] mmc: Add Amlogic Meson driver

[Andreas Färber]

Am 13.05.2016 um 15:53 schrieb Carlo Caione:
> [...] but since it is really unlikely that we will
> ever see a U-Boot port for the Meson8b I stuck with that.

Why do you consider that so unlikely? Please don't make such assumptions
for design decisions.

Regards,
Andreas

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Re: [U-Boot] [PATCH 1/2] mmc: Add Amlogic Meson driver

[Kevin Hilman]

Carlo Caione  writes:

> On Fri, May 13, 2016 at 3:46 PM, Kevin Hilman  wrote:
>> Carlo Caione  writes:
>>
>>> From: Carlo Caione 
>>>
>>> This is a port / rewrite of the Amlogic driver shipped whithin the
>>> Amlogic SDK for the Meson GXBaby (S905) SoC.
>>>
>>> Signed-off-by: Carlo Caione 
>>
>> [...]
>>
>>> +static const struct udevice_id meson_mmc_match[] = {
>>> + { .compatible = "amlogic,meson-mmc" },
>>> + { /* sentinel */ }
>>
>> IIUC, this controller is different between meson8* and gxbb.  If that's
>> the case, this compatible should probably be more specific.
>
> Yes, this is a point I raised also on lkml when I submitted the MMC
> driver for the Meson8b.
> Since the registers mapping is different I assume that this is the
> case. Just to be sure, given that you are the only one with a
> datasheet for the GXBB, can you confirm that?

I took a quick look and just compared the register layouts between s805
and s905 and indeed they are quite different.

Kevin

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Re: [U-Boot] [PATCH 1/2] mmc: Add Amlogic Meson driver

[Kevin Hilman]

Carlo Caione  writes:

> From: Carlo Caione 
>
> This is a port / rewrite of the Amlogic driver shipped whithin the
> Amlogic SDK for the Meson GXBaby (S905) SoC.
>
> Signed-off-by: Carlo Caione 

[...]

> +static const struct udevice_id meson_mmc_match[] = {
> + { .compatible = "amlogic,meson-mmc" },
> + { /* sentinel */ }

IIUC, this controller is different between meson8* and gxbb.  If that's
the case, this compatible should probably be more specific.

Kevin
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Re: [U-Boot] [PATCH 1/2] mmc: Add Amlogic Meson driver

[Carlo Caione]

On Fri, May 13, 2016 at 3:46 PM, Kevin Hilman  wrote:
> Carlo Caione  writes:
>
>> From: Carlo Caione 
>>
>> This is a port / rewrite of the Amlogic driver shipped whithin the
>> Amlogic SDK for the Meson GXBaby (S905) SoC.
>>
>> Signed-off-by: Carlo Caione 
>
> [...]
>
>> +static const struct udevice_id meson_mmc_match[] = {
>> + { .compatible = "amlogic,meson-mmc" },
>> + { /* sentinel */ }
>
> IIUC, this controller is different between meson8* and gxbb.  If that's
> the case, this compatible should probably be more specific.

Yes, this is a point I raised also on lkml when I submitted the MMC
driver for the Meson8b.
Since the registers mapping is different I assume that this is the
case. Just to be sure, given that you are the only one with a
datasheet for the GXBB, can you confirm that?

Actually for the same reason I was in doubt if CONFIG_MMC_MESON was a
right naming choice here, but since it is really unlikely that we will
ever see a U-Boot port for the Meson8b I stuck with that.

Cheers,

-- 
Carlo Caione
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[U-Boot] [PATCH 1/2] mmc: Add Amlogic Meson driver

[Carlo Caione]

From: Carlo Caione 

This is a port / rewrite of the Amlogic driver shipped whithin the
Amlogic SDK for the Meson GXBaby (S905) SoC.

Signed-off-by: Carlo Caione 
---
 arch/arm/include/asm/arch-meson/sd_emmc.h | 109 +++
 drivers/mmc/Makefile  |   1 +
 drivers/mmc/meson_mmc.c   | 305 ++
 3 files changed, 415 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-meson/sd_emmc.h
 create mode 100644 drivers/mmc/meson_mmc.c

diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h 
b/arch/arm/include/asm/arch-meson/sd_emmc.h
new file mode 100644
index 000..6781dca
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2016 Carlo Caione 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include 
+
+#define SDIO_PORT_A0
+#define SDIO_PORT_B1
+#define SDIO_PORT_C2
+
+#define SD_EMMC_BASE_A 0xd007
+#define SD_EMMC_BASE_B 0xd0072000
+#define SD_EMMC_BASE_C 0xd0074000
+
+#define SD_IRQ_ALL 0x3fff
+
+#define SD_EMMC_CLKSRC_24M 2400
+#define SD_EMMC_CLKSRC_DIV210
+
+#define CLK_DIV0
+#define CLK_SRC6
+#define CLK_CO_PHASE   8
+#define CLK_ALWAYS_ON  24
+
+#define ADDR_USE_PING_BUF  BIT(1)
+
+#define SD_EMMC_RXD_ERROR  BIT(0)
+#define SD_EMMC_TXD_ERROR  BIT(1)
+#define SD_EMMC_DESC_ERROR BIT(2)
+#define SD_EMMC_RESP_CRC_ERROR BIT(3)
+#define SD_EMMC_RESP_TIMEOUT_ERROR BIT(4)
+#define SD_EMMC_DESC_TIMEOUT_ERROR BIT(5)
+
+#define CFG_BUS_WIDTH  0
+#define CFG_BUS_WIDTH_MASK (0x3 << 0)
+#define CFG_BL_LEN 4
+#define CFG_BL_LEN_MASK(0xf << 4)
+#define CFG_RESP_TIMEOUT   8
+#define CFG_RESP_TIMEOUT_MASK  (0xf << 8)
+#define CFG_RC_CC  12
+#define CFG_RC_CC_MASK (0xf << 12)
+
+#define STATUS_RXD_ERR_MASK0xff
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERRBIT(9)
+#define STATUS_RESP_ERRBIT(10)
+#define STATUS_RESP_TIMEOUTBIT(11)
+#define STATUS_DESC_TIMEOUTBIT(12)
+#define STATUS_END_OF_CHAINBIT(13)
+
+#define CMD_CFG_LENGTH_MASK0x1ff
+#define CMD_CFG_CMD_INDEX  24
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1BBIT(10)
+#define CMD_CFG_END_OF_CHAIN   BIT(11)
+#define CMD_CFG_NO_RESPBIT(16)
+#define CMD_CFG_DATA_IOBIT(18)
+#define CMD_CFG_DATA_WRBIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128   BIT(21)
+#define CMD_CFG_OWNER  BIT(31)
+
+struct meson_mmc_regs {
+   uint32_t gclock;
+   uint32_t gdelay;
+   uint32_t gadjust;
+   uint32_t reserved_0c;
+   uint32_t gcalout;
+   uint32_t reserved_14[11];
+   uint32_t gstart;
+   uint32_t gcfg;
+   uint32_t gstatus;
+   uint32_t girq_en;
+   uint32_t gcmd_cfg;
+   uint32_t gcmd_arg;
+   uint32_t gcmd_dat;
+   uint32_t gcmd_rsp0;
+   uint32_t gcmd_rsp1;
+   uint32_t gcmd_rsp2;
+   uint32_t gcmd_rsp3;
+   uint32_t reserved_6c;
+   uint32_t gcurr_cfg;
+   uint32_t gcurr_arg;
+   uint32_t gcurr_dat;
+   uint32_t gcurr_rsp;
+   uint32_t gnext_cfg;
+   uint32_t gnext_arg;
+   uint32_t gnext_dat;
+   uint32_t gnext_rsp;
+   uint32_t grxd;
+   uint32_t gtxd;
+   uint32_t reserved_98[90];
+   uint32_t gdesc[128];
+   uint32_t gping[128];
+   uint32_t gpong[128];
+};
+
+struct meson_mmc_platdata {
+   struct mmc_config cfg;
+   struct meson_mmc_regs *sd_emmc_reg;
+   char *w_buf;
+};
+
+#endif
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 585aaf3..08ac9ba 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
 obj-$(CONFIG_GENERIC_MMC) += mmc.o
 obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_MMC_MESON) += meson_mmc.o
 obj-$(CONFIG_MMC_SPI) += mmc_spi.o
 obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
 obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o
diff --git a/drivers/mmc/meson_mmc.c b/drivers/mmc/meson_mmc.c
new file mode 100644
index 000..af224ec
--- /dev/null
+++ b/drivers/mmc/meson_mmc.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2016 Carlo Caione 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include