Re: [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-23 Thread Stefan Roese 

On 22.06.2017 11:13, m...@marvell.com wrote:

From: Ken Ma 

If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.

Signed-off-by: Ken Ma 
Cc: Stefan Roese 
Cc: Kostya Porotchkin 
Cc: Gregory CLEMENT 
Cc: Nadav Haklai 
Cc: Wilson Ding 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-22 Thread Stefan Roese 
Hi Ken,

On 22.06.2017 11:13, m...@marvell.com wrote:
> From: Ken Ma 
> 
> If north bridge selection register bit1 is clear, pins [10:8] are for
> SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
> GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
> and CTSn, so bit1 should be added to uart2 group and it must be set
> for both "gpio" and "uart" functions of uart2 group.
> 
> Signed-off-by: Ken Ma 
> Cc: Stefan Roese 
> Cc: Kostya Porotchkin 
> Cc: Gregory CLEMENT 
> Cc: Nadav Haklai 
> Cc: Wilson Ding 

Thanks for the the patches. One remark though about the patch
submission process:

You should mark version of your patches and list the changes (patch
history) in the patch as described here:

http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

This makes the review process much easier, as the reviewer does not need
to review the whole patch again, but only need to look for the new
changes in new version.

You don't need to do it for these patches, but please do it the
next time.

For this patch:

Reviewed-by: Stefan Roese 

Thanks,
Stefan
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[U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-22 Thread make 
From: Ken Ma 

If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.

Signed-off-by: Ken Ma 
Cc: Stefan Roese 
Cc: Kostya Porotchkin 
Cc: Gregory CLEMENT 
Cc: Nadav Haklai 
Cc: Wilson Ding 
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 3bb4c43..2ac66ec 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -159,8 +159,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] 
= {
PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
-   PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19),
- BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"),
+   PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
+ BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
+ 18, 2, "gpio", "uart"),
PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
-- 
1.9.1

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[U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-21 Thread make 
From: Ken Ma 

If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.

Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Michal Simek 
Cc: Kostya Porotchkin 
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 3bb4c43..2ac66ec 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -159,8 +159,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] 
= {
PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
-   PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19),
- BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"),
+   PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
+ BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
+ 18, 2, "gpio", "uart"),
PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
-- 
1.9.1

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