Based on the original version by Marc Zyngier. It adds a psci_cpu_off
implementation for the A20 SoC. The mechanism works by first preparing
the calling CPU to go offline (disable and flush cache, disable SMP),
then requesting CPU 0 to pull the plug. The request is sent as FIQ on
SGI15.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/sunxi/psci.S | 170
1 file changed, 170 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index a84807d..0aa4007 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -18,6 +18,7 @@
*/
#include config.h
+#include asm/gic.h
#include asm/psci.h
#include asm/arch/cpu.h
@@ -38,6 +39,8 @@
#defineONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
#defineTEN_MS (10 * ONE_MS)
+#defineGICD_BASE 0x1c81000
+#defineGICC_BASE 0x1c82000
.macro timer_wait reg, ticks
@ Program CNTP_TVAL
@@ -61,7 +64,27 @@
.globl psci_arch_init
psci_arch_init:
+ movwr4, #(GICD_BASE 0x)
+ movtr4, #(GICD_BASE 16)
+
+ ldr r5, [r4, #GICD_IGROUPRn]
+ bic r5, r5, #(1 15) @ SGI15 as Group-0
+ str r5, [r4, #GICD_IGROUPRn]
+
+ mov r5, #0 @ Set SGI15 priority to 0
+ strbr5, [r4, #(GICD_IPRIORITYRn + 15)]
+
+ add r4, r4, #0x1000 @ GICC address
+
+ mov r5, #0xff
+ str r5, [r4, #GICC_PMR] @ Be cool with non-secure
+
+ ldr r5, [r4, #GICC_CTLR]
+ orr r5, r5, #(1 3) @ Switch FIQEn on
+ str r5, [r4, #GICC_CTLR]
+
mrc p15, 0, r5, c1, c1, 0 @ Read SCR
+ orr r5, r5, #4 @ Enable FIQ in monitor mode
bic r5, r5, #1 @ Secure mode
mcr p15, 0, r5, c1, c1, 0 @ Write SCR
isb
@@ -79,6 +102,77 @@ psci_arch_init:
bx lr
+.globl psci_fiq_enter
+psci_fiq_enter:
+ push{r0-r12}
+
+ @ Switch to secure
+ mrc p15, 0, r7, c1, c1, 0
+ bic r8, r7, #1
+ mcr p15, 0, r8, c1, c1, 0
+ isb
+
+ movwr8, #(GICC_BASE 0x)
+ movtr8, #(GICC_BASE 16)
+ ldr r9, [r8, #GICC_IAR]
+ movwr10, #0x3ff
+ movtr10, #0
+ cmp r9, r10
+ beq out
+ movwr10, #0x3fe
+ cmp r9, r10
+ beq out
+ str r9, [r8, #GICC_EOIR]
+ dsb
+
+ @ Compute CPU number
+ lsr r9, r9, #10
+ and r9, r9, #0xf
+
+ movwr8, #(SUN7I_CPUCFG_BASE 0x)
+ movtr8, #(SUN7I_CPUCFG_BASE 16)
+
+ @ Wait for the core to enter WFI
+ lsl r11, r9, #6 @ x64
+ add r11, r11, r8
+
+1: ldr r10, [r11, #0x48]
+ tst r10, #(1 2)
+ bne 2f
+ timer_wait r10, ONE_MS
+ b 1b
+
+ @ Reset CPU
+2: mov r10, #0
+ str r10, [r11, #0x40]
+
+ @ Lock CPU
+ mov r10, #1
+ lsl r9, r10, r9 @ r9 is now CPU mask
+ ldr r10, [r8, #0x1e4]
+ bic r10, r10, r9
+ str r10, [r8, #0x1e4]
+
+ @ Set power gating
+ ldr r10, [r8, #0x1b4]
+ orr r10, r10, #1
+ str r10, [r8, #0x1b4]
+ timer_wait r10, ONE_MS
+
+ @ Activate power clamp
+ mov r10, #1
+1: str r10, [r8, #0x1b0]
+ lsl r10, r10, #1
+ orr r10, r10, #1
+ tst r10, #0x100
+ beq 1b
+
+ @ Restore security level
+out: mcr p15, 0, r7, c1, c1, 0
+
+ pop {r0-r12}
+ subspc, lr, #4
+
@ r1 = target CPU
@ r2 = target PC
.globl psci_cpu_on
@@ -144,6 +238,53 @@ psci_cpu_on:
_target_pc:
.word 0
+/* Imported from Linux kernel */
+v7_flush_dcache_all:
+ dmb @ ensure ordering with previous
memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ andsr3, r0, #0x700 @ extract loc from clidr
+ mov r3, r3, lsr #23 @ left align loc bit field
+ beq finished@ if loc is 0, then no need to
clean
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1@ work out 3x current cache
level
+ mov r1, r0, lsr r2 @ extract cache type bits from
clidr
+ and r1, r1, #7 @ mask of the bits for current
cache only
+ cmp r1, #2 @ see what cache we have at
this level
+ blt skip@ skip if no cache, or just
i-cache
+ mrs r9, cpsr@ make cssrcsidr read atomic
+ mcr p15,
