Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
On Wed, Nov 13, 2013 at 12:50:50PM -0500, Vaibhav Bedia wrote: > Hi Sekhar :) > > On Wed, Nov 13, 2013 at 11:08 AM, Sekhar Nori wrote: > > Hi Vaibhav, > > > > On 11/13/2013 7:38 PM, Vaibhav Bedia wrote: > >> On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla wrote: > >> [...] > >>> I checked with hardware folks. There is no register or some way to tell > >>> if VTT is present. It is not added in EEPROM also and I have no answer > >>> why it > >>> is not added in EEPROM..:( > >>> It is specific to boards using DDR3. So its good to have it in board > >>> files as I did it here > >>> instead of adding this check in emif file. > >> > >> That EEPROM is clearly not getting used the way i think it should be :\ > >> I would have made a lot of noise to get details like this added there. > > > > The EEPROM was designed as a way to differentiate between different TI > > EVMs, not as a generic way to differentiate between various possible > > board hook-ups. Even if we did define it that way, why would all boards > > using AM437x have an onboard EEPROM? > > > > We could request this information be placed in EEPROM and see if > > hardware folks oblige, but I don't see how that's going to be used > > beyond TI EVMs. > > > > I understand the intent of customers to get rid of all the components > they can to lower the cost. But if one just thinks about this a bit more, > the current solution does a half-hearted attempt to differentiate the boards > variants. It doesn't really capture the differences that are there and that > is leading to hard coding to a certain extent. > > From AM335x boards we should now have a decent idea of what > things change across boards that go into production. I don't think it > makes sense to throw away all that knowledge and go ahead > assuming we will never make a change. The request for change is just > to future proof the current code and have the EEPROM actually help us > do our jobs. Why? Because life's too short to keep worrying about why a > board rev that a you pick up from a neighbor's desk doesn't boot, hooking > up the JTAG to trace the DDR setup code, figure out what needs to change > in the boot-loader, add in the appropriate check and then get to the task > at hand ;) In theory, one could also learn from the customers that did keep the EEPROM about what additional information they programmed in. I think however, the most likely outcome here is that we'll be able to only rely on the board name (and rev) part of the EEPROM being populated and the board code should be clear and well commented about non-obvious things such as design choice A means B is required. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
On Wed, Nov 13, 2013 at 09:08:29AM -0500, Vaibhav Bedia wrote: > On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla wrote: > [...] > > I checked with hardware folks. There is no register or some way to tell > > if VTT is present. It is not added in EEPROM also and I have no answer why > > it > > is not added in EEPROM..:( > > It is specific to boards using DDR3. So its good to have it in board files > > as I did it here > > instead of adding this check in emif file. > > That EEPROM is clearly not getting used the way i think it should be :\ > I would have made a lot of noise to get details like this added there. > > You should at least check for the GP EVM (if possible) and then enable > VTT. Doing this unconditionally is bound to cause problems later on. > I would also put in a big comment over there so that folks who design > their own board with DDR3 don't miss this fact. I agree, the code should be doing a check for what board we're on and enabling VTT, and a good comment about what's going on here. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
Hi Sekhar :) On Wed, Nov 13, 2013 at 11:08 AM, Sekhar Nori wrote: > Hi Vaibhav, > > On 11/13/2013 7:38 PM, Vaibhav Bedia wrote: >> On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla wrote: >> [...] >>> I checked with hardware folks. There is no register or some way to tell >>> if VTT is present. It is not added in EEPROM also and I have no answer why >>> it >>> is not added in EEPROM..:( >>> It is specific to boards using DDR3. So its good to have it in board files >>> as I did it here >>> instead of adding this check in emif file. >> >> That EEPROM is clearly not getting used the way i think it should be :\ >> I would have made a lot of noise to get details like this added there. > > The EEPROM was designed as a way to differentiate between different TI > EVMs, not as a generic way to differentiate between various possible > board hook-ups. Even if we did define it that way, why would all boards > using AM437x have an onboard EEPROM? > > We could request this information be placed in EEPROM and see if > hardware folks oblige, but I don't see how that's going to be used > beyond TI EVMs. > I understand the intent of customers to get rid of all the components they can to lower the cost. But if one just thinks about this a bit more, the current solution does a half-hearted attempt to differentiate the boards variants. It doesn't really capture the differences that are there and that is leading to hard coding to a certain extent. >From AM335x boards we should now have a decent idea of what things change across boards that go into production. I don't think it makes sense to throw away all that knowledge and go ahead assuming we will never make a change. The request for change is just to future proof the current code and have the EEPROM actually help us do our jobs. Why? Because life's too short to keep worrying about why a board rev that a you pick up from a neighbor's desk doesn't boot, hooking up the JTAG to trace the DDR setup code, figure out what needs to change in the boot-loader, add in the appropriate check and then get to the task at hand ;) Regards, Vaibhav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
Hi Vaibhav, On 11/13/2013 7:38 PM, Vaibhav Bedia wrote: > On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla wrote: > [...] >> I checked with hardware folks. There is no register or some way to tell >> if VTT is present. It is not added in EEPROM also and I have no answer why it >> is not added in EEPROM..:( >> It is specific to boards using DDR3. So its good to have it in board files >> as I did it here >> instead of adding this check in emif file. > > That EEPROM is clearly not getting used the way i think it should be :\ > I would have made a lot of noise to get details like this added there. The EEPROM was designed as a way to differentiate between different TI EVMs, not as a generic way to differentiate between various possible board hook-ups. Even if we did define it that way, why would all boards using AM437x have an onboard EEPROM? We could request this information be placed in EEPROM and see if hardware folks oblige, but I don't see how that's going to be used beyond TI EVMs. Thanks, Sekhar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla wrote: [...] > I checked with hardware folks. There is no register or some way to tell > if VTT is present. It is not added in EEPROM also and I have no answer why it > is not added in EEPROM..:( > It is specific to boards using DDR3. So its good to have it in board files as > I did it here > instead of adding this check in emif file. That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there. You should at least check for the GP EVM (if possible) and then enable VTT. Doing this unconditionally is bound to cause problems later on. I would also put in a big comment over there so that folks who design their own board with DDR3 don't miss this fact. Regards, Vaibhav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
Hi Vaibhav,
On Wednesday 06 November 2013 07:24 PM, Lokesh Vutla wrote:
> On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote:
>> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>>> GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
>>> Adding details for the same.
>>> Below is the brief description of DDR3 init sequence(SW leveling):
>>> -> Enable VTT regulator
>>> -> Configure VTP
>>> -> Configure DDR IO settings
>>> -> Disable initialization and refreshes until EMIF registers are programmed.
>>> -> Program Timing registers
>>> -> Program leveling registers
>>> -> Program PHY control and Temp alert and ZQ config registers.
>>
>> Temp alert? Is that really relevant here?
> Yes, Need to configure all the emif registers before accessing SDRAM.
>>
>>> -> Enable initialization and refreshes and configure SDRAM CONFIG register
>>>
>>> Signed-off-by: Lokesh Vutla
>>> ---
>>> arch/arm/cpu/armv7/am33xx/emif4d5.c |8 ++-
>>> arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++-
>>> board/ti/am43xx/board.c | 89
>>> ++-
>>> 3 files changed, 101 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c
>>> b/arch/arm/cpu/armv7/am33xx/emif4d5.c
>>> index eea1fa3..8bac0f2 100644
>>> --- a/arch/arm/cpu/armv7/am33xx/emif4d5.c
>>> +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c
>>> @@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
>>>
>>> void do_sdram_init(const struct ctrl_ioregs *ioregs,
>>>const struct emif_regs *regs,
>>> - const u32 *ext_phy_ctrl_const_regs)
>>> + const u32 *ext_phy_ctrl_const_regs, u32 sdram_type)
>>> {
>>> struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>>>
>>> @@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs,
>>> writel(regs->sdram_config, &emif->emif_sdram_config);
>>> writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
>>>
>>> - configure_mr(EMIF1_BASE, 0);
>>> - configure_mr(EMIF1_BASE, 1);
>>> + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {
>>> + configure_mr(EMIF1_BASE, 0);
>>> + configure_mr(EMIF1_BASE, 1);
>>> + }
>>> }
>>> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> index 1880415..796e9df 100644
>>> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> @@ -134,6 +134,14 @@
>>> #define LPDDR2_DATA2_IOCTRL_VALUE 0x2294
>>> #define LPDDR2_DATA3_IOCTRL_VALUE 0x2294
>>>
>>> +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x
>>> +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x
>>> +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
>>> +#define DDR3_DATA0_IOCTRL_VALUE 0x84
>>> +#define DDR3_DATA1_IOCTRL_VALUE 0x84
>>> +#define DDR3_DATA2_IOCTRL_VALUE 0x84
>>> +#define DDR3_DATA3_IOCTRL_VALUE 0x84
>>> +
>>> /**
>>> * Configure DMM
>>> */
>>> @@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
>>>
>>> void do_sdram_init(const struct ctrl_ioregs *ioregs,
>>>const struct emif_regs *emif_regs,
>>> - const u32 *ext_phy_ctrl_const_regs);
>>> + const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);
>>> #endif /* _DDR_DEFS_H */
>>> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
>>> index 83d184d..a943b45 100644
>>> --- a/board/ti/am43xx/board.c
>>> +++ b/board/ti/am43xx/board.c
>>> @@ -140,6 +140,57 @@ const u32
>>> ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
>>> 0x08102040
>>> };
>>>
>>> +const struct ctrl_ioregs ioregs_ddr3 = {
>>> + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
>>> + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
>>> + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
>>> + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
>>> + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
>>> + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
>>> + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
>>> + .emif_sdram_config_ext = 0x0043,
>>> +};
>>> +
>>> +const struct emif_regs ddr3_emif_regs_400Mhz = {
>>> + .sdram_config = 0x638413B2,
>>> + .ref_ctrl = 0x0C30,
>>> + .sdram_tim1 = 0xEAAAD4DB,
>>> + .sdram_tim2 = 0x266B7FDA,
>>> + .sdram_tim3 = 0x107F8678,
>>> + .read_idle_ctrl = 0x0005,
>>> + .zq_config = 0x50074BE4,
>>> + .temp_alert_config = 0x0,
>>> + .emif_ddr_phy_ctlr_1= 0x0E084007,
>>> + .emif_ddr_ext_phy_ctrl_1= 0x08020080,
>>> + .emif_ddr_ext_phy_ctrl_2= 0x00400040,
>>> + .emif_ddr_ext_phy_ct
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
On Wed, Nov 6, 2013 at 8:54 AM, Lokesh Vutla wrote: > On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote: >> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote: >>> GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C). >>> Adding details for the same. >>> Below is the brief description of DDR3 init sequence(SW leveling): >>> -> Enable VTT regulator >>> -> Configure VTP >>> -> Configure DDR IO settings >>> -> Disable initialization and refreshes until EMIF registers are programmed. >>> -> Program Timing registers >>> -> Program leveling registers >>> -> Program PHY control and Temp alert and ZQ config registers. >> >> Temp alert? Is that really relevant here? > Yes, Need to configure all the emif registers before accessing SDRAM. Ok. What's done on an AM437x system when the temp goes beyond a threshold? Regards, Vaibhav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote:
> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>> GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
>> Adding details for the same.
>> Below is the brief description of DDR3 init sequence(SW leveling):
>> -> Enable VTT regulator
>> -> Configure VTP
>> -> Configure DDR IO settings
>> -> Disable initialization and refreshes until EMIF registers are programmed.
>> -> Program Timing registers
>> -> Program leveling registers
>> -> Program PHY control and Temp alert and ZQ config registers.
>
> Temp alert? Is that really relevant here?
Yes, Need to configure all the emif registers before accessing SDRAM.
>
>> -> Enable initialization and refreshes and configure SDRAM CONFIG register
>>
>> Signed-off-by: Lokesh Vutla
>> ---
>> arch/arm/cpu/armv7/am33xx/emif4d5.c |8 ++-
>> arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++-
>> board/ti/am43xx/board.c | 89
>> ++-
>> 3 files changed, 101 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c
>> b/arch/arm/cpu/armv7/am33xx/emif4d5.c
>> index eea1fa3..8bac0f2 100644
>> --- a/arch/arm/cpu/armv7/am33xx/emif4d5.c
>> +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c
>> @@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
>>
>> void do_sdram_init(const struct ctrl_ioregs *ioregs,
>>const struct emif_regs *regs,
>> - const u32 *ext_phy_ctrl_const_regs)
>> + const u32 *ext_phy_ctrl_const_regs, u32 sdram_type)
>> {
>> struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>>
>> @@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs,
>> writel(regs->sdram_config, &emif->emif_sdram_config);
>> writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
>>
>> - configure_mr(EMIF1_BASE, 0);
>> - configure_mr(EMIF1_BASE, 1);
>> + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {
>> + configure_mr(EMIF1_BASE, 0);
>> + configure_mr(EMIF1_BASE, 1);
>> + }
>> }
>> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>> b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>> index 1880415..796e9df 100644
>> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>> @@ -134,6 +134,14 @@
>> #define LPDDR2_DATA2_IOCTRL_VALUE 0x2294
>> #define LPDDR2_DATA3_IOCTRL_VALUE 0x2294
>>
>> +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x
>> +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x
>> +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
>> +#define DDR3_DATA0_IOCTRL_VALUE 0x84
>> +#define DDR3_DATA1_IOCTRL_VALUE 0x84
>> +#define DDR3_DATA2_IOCTRL_VALUE 0x84
>> +#define DDR3_DATA3_IOCTRL_VALUE 0x84
>> +
>> /**
>> * Configure DMM
>> */
>> @@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
>>
>> void do_sdram_init(const struct ctrl_ioregs *ioregs,
>>const struct emif_regs *emif_regs,
>> - const u32 *ext_phy_ctrl_const_regs);
>> + const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);
>> #endif /* _DDR_DEFS_H */
>> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
>> index 83d184d..a943b45 100644
>> --- a/board/ti/am43xx/board.c
>> +++ b/board/ti/am43xx/board.c
>> @@ -140,6 +140,57 @@ const u32
>> ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
>> 0x08102040
>> };
>>
>> +const struct ctrl_ioregs ioregs_ddr3 = {
>> + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
>> + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
>> + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
>> + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
>> + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
>> + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
>> + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
>> + .emif_sdram_config_ext = 0x0043,
>> +};
>> +
>> +const struct emif_regs ddr3_emif_regs_400Mhz = {
>> + .sdram_config = 0x638413B2,
>> + .ref_ctrl = 0x0C30,
>> + .sdram_tim1 = 0xEAAAD4DB,
>> + .sdram_tim2 = 0x266B7FDA,
>> + .sdram_tim3 = 0x107F8678,
>> + .read_idle_ctrl = 0x0005,
>> + .zq_config = 0x50074BE4,
>> + .temp_alert_config = 0x0,
>> + .emif_ddr_phy_ctlr_1= 0x0E084007,
>> + .emif_ddr_ext_phy_ctrl_1= 0x08020080,
>> + .emif_ddr_ext_phy_ctrl_2= 0x00400040,
>> + .emif_ddr_ext_phy_ctrl_3= 0x00400040,
>> + .emif_ddr_ext_phy_ctrl_4= 0x00400040,
>> + .emif_ddr_ext_phy_ctrl_5= 0x00400040
>> +};
>> +
>> +const u32 ext_phy_ctrl_const
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
> Adding details for the same.
> Below is the brief description of DDR3 init sequence(SW leveling):
> -> Enable VTT regulator
> -> Configure VTP
> -> Configure DDR IO settings
> -> Disable initialization and refreshes until EMIF registers are programmed.
> -> Program Timing registers
> -> Program leveling registers
> -> Program PHY control and Temp alert and ZQ config registers.
Temp alert? Is that really relevant here?
> -> Enable initialization and refreshes and configure SDRAM CONFIG register
>
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/cpu/armv7/am33xx/emif4d5.c |8 ++-
> arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++-
> board/ti/am43xx/board.c | 89
> ++-
> 3 files changed, 101 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c
> b/arch/arm/cpu/armv7/am33xx/emif4d5.c
> index eea1fa3..8bac0f2 100644
> --- a/arch/arm/cpu/armv7/am33xx/emif4d5.c
> +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c
> @@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
>
> void do_sdram_init(const struct ctrl_ioregs *ioregs,
>const struct emif_regs *regs,
> - const u32 *ext_phy_ctrl_const_regs)
> + const u32 *ext_phy_ctrl_const_regs, u32 sdram_type)
> {
> struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>
> @@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs,
> writel(regs->sdram_config, &emif->emif_sdram_config);
> writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
>
> - configure_mr(EMIF1_BASE, 0);
> - configure_mr(EMIF1_BASE, 1);
> + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {
> + configure_mr(EMIF1_BASE, 0);
> + configure_mr(EMIF1_BASE, 1);
> + }
> }
> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> index 1880415..796e9df 100644
> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> @@ -134,6 +134,14 @@
> #define LPDDR2_DATA2_IOCTRL_VALUE 0x2294
> #define LPDDR2_DATA3_IOCTRL_VALUE 0x2294
>
> +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x
> +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x
> +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
> +#define DDR3_DATA0_IOCTRL_VALUE 0x84
> +#define DDR3_DATA1_IOCTRL_VALUE 0x84
> +#define DDR3_DATA2_IOCTRL_VALUE 0x84
> +#define DDR3_DATA3_IOCTRL_VALUE 0x84
> +
> /**
> * Configure DMM
> */
> @@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
>
> void do_sdram_init(const struct ctrl_ioregs *ioregs,
>const struct emif_regs *emif_regs,
> - const u32 *ext_phy_ctrl_const_regs);
> + const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);
> #endif /* _DDR_DEFS_H */
> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
> index 83d184d..a943b45 100644
> --- a/board/ti/am43xx/board.c
> +++ b/board/ti/am43xx/board.c
> @@ -140,6 +140,57 @@ const u32
> ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
> 0x08102040
> };
>
> +const struct ctrl_ioregs ioregs_ddr3 = {
> + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
> + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
> + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
> + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
> + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
> + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
> + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
> + .emif_sdram_config_ext = 0x0043,
> +};
> +
> +const struct emif_regs ddr3_emif_regs_400Mhz = {
> + .sdram_config = 0x638413B2,
> + .ref_ctrl = 0x0C30,
> + .sdram_tim1 = 0xEAAAD4DB,
> + .sdram_tim2 = 0x266B7FDA,
> + .sdram_tim3 = 0x107F8678,
> + .read_idle_ctrl = 0x0005,
> + .zq_config = 0x50074BE4,
> + .temp_alert_config = 0x0,
> + .emif_ddr_phy_ctlr_1= 0x0E084007,
> + .emif_ddr_ext_phy_ctrl_1= 0x08020080,
> + .emif_ddr_ext_phy_ctrl_2= 0x00400040,
> + .emif_ddr_ext_phy_ctrl_3= 0x00400040,
> + .emif_ddr_ext_phy_ctrl_4= 0x00400040,
> + .emif_ddr_ext_phy_ctrl_5= 0x00400040
> +};
> +
> +const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
> + 0x00400040,
> + 0x00350035,
> + 0x00350035,
> + 0x00350035,
> + 0x00350035,
> + 0x00350035,
> + 0x,
> + 0x,
> + 0x,
> +
[U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/am33xx/emif4d5.c |8 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++-
board/ti/am43xx/board.c | 89 ++-
3 files changed, 101 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c
b/arch/arm/cpu/armv7/am33xx/emif4d5.c
index eea1fa3..8bac0f2 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4d5.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c
@@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
void do_sdram_init(const struct ctrl_ioregs *ioregs,
const struct emif_regs *regs,
- const u32 *ext_phy_ctrl_const_regs)
+ const u32 *ext_phy_ctrl_const_regs, u32 sdram_type)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
@@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs,
writel(regs->sdram_config, &emif->emif_sdram_config);
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
- configure_mr(EMIF1_BASE, 0);
- configure_mr(EMIF1_BASE, 1);
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {
+ configure_mr(EMIF1_BASE, 0);
+ configure_mr(EMIF1_BASE, 1);
+ }
}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 1880415..796e9df 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -134,6 +134,14 @@
#define LPDDR2_DATA2_IOCTRL_VALUE 0x2294
#define LPDDR2_DATA3_IOCTRL_VALUE 0x2294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x
+#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x
+#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
+#define DDR3_DATA0_IOCTRL_VALUE 0x84
+#define DDR3_DATA1_IOCTRL_VALUE 0x84
+#define DDR3_DATA2_IOCTRL_VALUE 0x84
+#define DDR3_DATA3_IOCTRL_VALUE 0x84
+
/**
* Configure DMM
*/
@@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
void do_sdram_init(const struct ctrl_ioregs *ioregs,
const struct emif_regs *emif_regs,
- const u32 *ext_phy_ctrl_const_regs);
+ const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);
#endif /* _DDR_DEFS_H */
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 83d184d..a943b45 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -140,6 +140,57 @@ const u32
ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x08102040
};
+const struct ctrl_ioregs ioregs_ddr3 = {
+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x0043,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x0C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x0005,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1= 0x0E084007,
+ .emif_ddr_ext_phy_ctrl_1= 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2= 0x00400040,
+ .emif_ddr_ext_phy_ctrl_3= 0x00400040,
+ .emif_ddr_ext_phy_ctrl_4= 0x00400040,
+ .emif_ddr_ext_phy_ctrl_5= 0x00400040
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x00400040,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x0,
+ 0x0,
+ 0x4000,
+ 0x08102040
+};
+
const struct dpll_params *get_dpll_ddr_params(void)
{
if (board_is_eposevm())
@@ -189,10 +240,44 @@ void set_
