GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
---
arch/arm/cpu/armv7/am33xx/emif4d5.c | 8 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++-
board/ti/am43xx/board.c | 89 ++++++++++++++++++++++++++-
3 files changed, 101 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c
b/arch/arm/cpu/armv7/am33xx/emif4d5.c
index eea1fa3..8bac0f2 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4d5.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c
@@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
void do_sdram_init(const struct ctrl_ioregs *ioregs,
const struct emif_regs *regs,
- const u32 *ext_phy_ctrl_const_regs)
+ const u32 *ext_phy_ctrl_const_regs, u32 sdram_type)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
@@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs,
writel(regs->sdram_config, &emif->emif_sdram_config);
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
- configure_mr(EMIF1_BASE, 0);
- configure_mr(EMIF1_BASE, 1);
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {
+ configure_mr(EMIF1_BASE, 0);
+ configure_mr(EMIF1_BASE, 1);
+ }
}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 1880415..796e9df 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -134,6 +134,14 @@
#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
+#define DDR3_DATA0_IOCTRL_VALUE 0x84
+#define DDR3_DATA1_IOCTRL_VALUE 0x84
+#define DDR3_DATA2_IOCTRL_VALUE 0x84
+#define DDR3_DATA3_IOCTRL_VALUE 0x84
+
/**
* Configure DMM
*/
@@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
void do_sdram_init(const struct ctrl_ioregs *ioregs,
const struct emif_regs *emif_regs,
- const u32 *ext_phy_ctrl_const_regs);
+ const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);
#endif /* _DDR_DEFS_H */
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 83d184d..a943b45 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -140,6 +140,57 @@ const u32
ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x08102040
};
+const struct ctrl_ioregs ioregs_ddr3 = {
+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x0043,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E084007,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00400040
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x00400040,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
const struct dpll_params *get_dpll_ddr_params(void)
{
if (board_is_eposevm())
@@ -189,10 +240,44 @@ void set_mux_conf_regs(void)
enable_board_pin_mux();
}
+static void enable_vtt_regulator(void)
+{
+ u32 temp;
+
+ /*GPIO_VTTEN - GPIO0_21 PINMUX Setup*/
+ writel(0x20009, CTRL_BASE + 0x0A60);
+
+ writel(0x40002, PRCM_BASE + 0x2B68);
+
+ /* Poll if module is functional */
+ while ((readl(PRCM_BASE + 0x2B68) & 0x30000) != 0x0)
+ ;
+
+ while ((readl(PRCM_BASE + 0x2B00) & 0x100) != 0x100)
+ ;
+
+ /* enable module */
+ writel(0x0, GPIO0_BASE + 0x0130);
+
+ /*enable output for GPIO0_21*/
+ writel((1 << 22), GPIO0_BASE + 0x0194);
+ temp = readl(GPIO0_BASE + 0x0134);
+ temp = temp & ~(1 << 22);
+ writel(temp, GPIO0_BASE + 0x0134);
+}
+
void sdram_init(void)
{
- do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,
- ext_phy_ctrl_const_base_lpddr2);
+ if (board_is_eposevm()) {
+ do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,
+ ext_phy_ctrl_const_base_lpddr2,
+ EMIF_SDRAM_TYPE_LPDDR2);
+ } else {
+ enable_vtt_regulator();
+ do_sdram_init(&ioregs_ddr3, &ddr3_emif_regs_400Mhz,
+ ext_phy_ctrl_const_base_ddr3,
+ EMIF_SDRAM_TYPE_DDR3);
+ }
}
#endif
--
1.7.9.5
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