Re: [U-Boot] [PATCH 17/39] x86: Add chromebook_link board
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/Kconfig | 23 +
arch/x86/cpu/coreboot/coreboot.c | 8 ++
arch/x86/cpu/cpu.c | 32 --
arch/x86/cpu/ivybridge/Kconfig | 157
+
arch/x86/cpu/ivybridge/Makefile| 9 ++
arch/x86/cpu/ivybridge/car.S | 20
arch/x86/cpu/ivybridge/cpu.c | 41
arch/x86/cpu/ivybridge/sdram.c | 20
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/include/asm/arch-ivybridge/gpio.h | 10 ++
arch/x86/include/asm/processor.h | 12 +++
board/google/chromebook_link/Kconfig | 15 +++
board/google/chromebook_link/MAINTAINERS | 6 ++
board/google/chromebook_link/Makefile | 15 +++
board/google/chromebook_link/link.c| 17
configs/chromebook_link_defconfig | 10 ++
include/configs/chromebook_link.h | 53 ++
18 files changed, 443 insertions(+), 7 deletions(-)
create mode 100644 arch/x86/cpu/ivybridge/Kconfig
create mode 100644 arch/x86/cpu/ivybridge/Makefile
create mode 100644 arch/x86/cpu/ivybridge/car.S
create mode 100644 arch/x86/cpu/ivybridge/cpu.c
create mode 100644 arch/x86/cpu/ivybridge/sdram.c
create mode 12 arch/x86/dts/chromebook_link.dts
create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
create mode 100644 board/google/chromebook_link/Kconfig
create mode 100644 board/google/chromebook_link/MAINTAINERS
create mode 100644 board/google/chromebook_link/Makefile
create mode 100644 board/google/chromebook_link/link.c
create mode 100644 configs/chromebook_link_defconfig
create mode 100644 include/configs/chromebook_link.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0dba8ac..07ff149 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -12,9 +12,32 @@ choice
config TARGET_COREBOOT
bool Support coreboot
+ help
+ This target is used for running U-Boot on top of Coreboot. In
+ this case Coreboot does the early inititalisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as a fallback payload from Coreboot, in
+ Coreboot terminology. This method was used for the Chromebook
+ Pixel when launched.
+
+config TARGET_CHROMEBOOK_LINK
+ bool Support Chromebook link
+ help
+ This is the Chromebook Pixel released in 2013. It uses an Intel
+ i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+ SDRAM. It has a Panther Point peripheral controller hub, PCIe
Intel official name is 'platform controller hub'.
+ WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+ reader, microphone and speakers, display port and 32GB SATA
+ solid state drive. There is a Chrome OS EC connected on LPC,
+ and it provides a 2560x1700 high resolution touch-enabled LCD
+ display.
endchoice
+source arch/x86/cpu/ivybridge/Kconfig
+
source board/chromebook-x86/coreboot/Kconfig
Not related to this patch, but do you consider renaming
'board/chromebook-x86/' to something like 'board/generic-x86/' since
this build of U-Boot is supposed to run as a payload from coreboot on
every board that coreboot supports in theory.
+source board/google/chromebook_link/Kconfig
+
endmenu
diff --git a/arch/x86/cpu/coreboot/coreboot.c
b/arch/x86/cpu/coreboot/coreboot.c
index c430ab1..257faa1 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -13,6 +13,7 @@
#include ns16550.h
#include asm/msr.h
#include asm/cache.h
+#include asm/cpu.h
#include asm/io.h
#include asm/arch-coreboot/tables.h
#include asm/arch-coreboot/sysinfo.h
@@ -127,3 +128,10 @@ void panic_puts(const char *str)
while (*str)
NS16550_putc(port, *str++);
}
+
+int print_cpuinfo(void)
+{
+ printf(CPU: %s\n, cpu_has_64bit() ? x86_64 : x86);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6441dde..61c198e 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -334,13 +334,6 @@ int cpu_has_64bit(void)
has_long_mode();
}
-int print_cpuinfo(void)
-{
- printf(CPU: %s\n, cpu_has_64bit() ? x86_64 : x86);
-
- return 0;
-}
-
Re: [U-Boot] [PATCH 17/39] x86: Add chromebook_link board
Hi Bin, On 7 November 2014 03:18, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass s...@chromium.org --- arch/x86/Kconfig | 23 + arch/x86/cpu/coreboot/coreboot.c | 8 ++ arch/x86/cpu/cpu.c | 32 -- arch/x86/cpu/ivybridge/Kconfig | 157 + arch/x86/cpu/ivybridge/Makefile| 9 ++ arch/x86/cpu/ivybridge/car.S | 20 arch/x86/cpu/ivybridge/cpu.c | 41 arch/x86/cpu/ivybridge/sdram.c | 20 arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/include/asm/arch-ivybridge/gpio.h | 10 ++ arch/x86/include/asm/processor.h | 12 +++ board/google/chromebook_link/Kconfig | 15 +++ board/google/chromebook_link/MAINTAINERS | 6 ++ board/google/chromebook_link/Makefile | 15 +++ board/google/chromebook_link/link.c| 17 configs/chromebook_link_defconfig | 10 ++ include/configs/chromebook_link.h | 53 ++ 18 files changed, 443 insertions(+), 7 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/Kconfig create mode 100644 arch/x86/cpu/ivybridge/Makefile create mode 100644 arch/x86/cpu/ivybridge/car.S create mode 100644 arch/x86/cpu/ivybridge/cpu.c create mode 100644 arch/x86/cpu/ivybridge/sdram.c create mode 12 arch/x86/dts/chromebook_link.dts create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h create mode 100644 board/google/chromebook_link/Kconfig create mode 100644 board/google/chromebook_link/MAINTAINERS create mode 100644 board/google/chromebook_link/Makefile create mode 100644 board/google/chromebook_link/link.c create mode 100644 configs/chromebook_link_defconfig create mode 100644 include/configs/chromebook_link.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0dba8ac..07ff149 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -12,9 +12,32 @@ choice config TARGET_COREBOOT bool Support coreboot + help + This target is used for running U-Boot on top of Coreboot. In + this case Coreboot does the early inititalisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a fallback payload from Coreboot, in + Coreboot terminology. This method was used for the Chromebook + Pixel when launched. + +config TARGET_CHROMEBOOK_LINK + bool Support Chromebook link + help + This is the Chromebook Pixel released in 2013. It uses an Intel + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of + SDRAM. It has a Panther Point peripheral controller hub, PCIe Intel official name is 'platform controller hub'. OK I'll update this. + WiFi and Bluetooth. It also includes a 720p webcam, USB SD + reader, microphone and speakers, display port and 32GB SATA + solid state drive. There is a Chrome OS EC connected on LPC, + and it provides a 2560x1700 high resolution touch-enabled LCD + display. endchoice +source arch/x86/cpu/ivybridge/Kconfig + source board/chromebook-x86/coreboot/Kconfig Not related to this patch, but do you consider renaming 'board/chromebook-x86/' to something like 'board/generic-x86/' since this build of U-Boot is supposed to run as a payload from coreboot on every board that coreboot supports in theory. Possibly, although it isn't really generic. Probably we should just use the name coreboot consistently. Actually I think I had this discussion with the original author but he wasn't having it... [snip] Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 17/39] x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/Kconfig | 23 +
arch/x86/cpu/coreboot/coreboot.c | 8 ++
arch/x86/cpu/cpu.c | 32 --
arch/x86/cpu/ivybridge/Kconfig | 157 +
arch/x86/cpu/ivybridge/Makefile| 9 ++
arch/x86/cpu/ivybridge/car.S | 20
arch/x86/cpu/ivybridge/cpu.c | 41
arch/x86/cpu/ivybridge/sdram.c | 20
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/include/asm/arch-ivybridge/gpio.h | 10 ++
arch/x86/include/asm/processor.h | 12 +++
board/google/chromebook_link/Kconfig | 15 +++
board/google/chromebook_link/MAINTAINERS | 6 ++
board/google/chromebook_link/Makefile | 15 +++
board/google/chromebook_link/link.c| 17
configs/chromebook_link_defconfig | 10 ++
include/configs/chromebook_link.h | 53 ++
18 files changed, 443 insertions(+), 7 deletions(-)
create mode 100644 arch/x86/cpu/ivybridge/Kconfig
create mode 100644 arch/x86/cpu/ivybridge/Makefile
create mode 100644 arch/x86/cpu/ivybridge/car.S
create mode 100644 arch/x86/cpu/ivybridge/cpu.c
create mode 100644 arch/x86/cpu/ivybridge/sdram.c
create mode 12 arch/x86/dts/chromebook_link.dts
create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
create mode 100644 board/google/chromebook_link/Kconfig
create mode 100644 board/google/chromebook_link/MAINTAINERS
create mode 100644 board/google/chromebook_link/Makefile
create mode 100644 board/google/chromebook_link/link.c
create mode 100644 configs/chromebook_link_defconfig
create mode 100644 include/configs/chromebook_link.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0dba8ac..07ff149 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -12,9 +12,32 @@ choice
config TARGET_COREBOOT
bool Support coreboot
+ help
+ This target is used for running U-Boot on top of Coreboot. In
+ this case Coreboot does the early inititalisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as a fallback payload from Coreboot, in
+ Coreboot terminology. This method was used for the Chromebook
+ Pixel when launched.
+
+config TARGET_CHROMEBOOK_LINK
+ bool Support Chromebook link
+ help
+ This is the Chromebook Pixel released in 2013. It uses an Intel
+ i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+ SDRAM. It has a Panther Point peripheral controller hub, PCIe
+ WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+ reader, microphone and speakers, display port and 32GB SATA
+ solid state drive. There is a Chrome OS EC connected on LPC,
+ and it provides a 2560x1700 high resolution touch-enabled LCD
+ display.
endchoice
+source arch/x86/cpu/ivybridge/Kconfig
+
source board/chromebook-x86/coreboot/Kconfig
+source board/google/chromebook_link/Kconfig
+
endmenu
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c430ab1..257faa1 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -13,6 +13,7 @@
#include ns16550.h
#include asm/msr.h
#include asm/cache.h
+#include asm/cpu.h
#include asm/io.h
#include asm/arch-coreboot/tables.h
#include asm/arch-coreboot/sysinfo.h
@@ -127,3 +128,10 @@ void panic_puts(const char *str)
while (*str)
NS16550_putc(port, *str++);
}
+
+int print_cpuinfo(void)
+{
+ printf(CPU: %s\n, cpu_has_64bit() ? x86_64 : x86);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6441dde..61c198e 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -334,13 +334,6 @@ int cpu_has_64bit(void)
has_long_mode();
}
-int print_cpuinfo(void)
-{
- printf(CPU: %s\n, cpu_has_64bit() ? x86_64 : x86);
-
- return 0;
-}
-
#define PAGETABLE_SIZE (6 * 4096)
/**
@@ -382,3 +375,28 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)
return -EFAULT;
}
+
+char *cpu_get_name(char *name)
+{
+ unsigned int *name_as_ints = (unsigned int *)name;
+ struct cpuid_result regs;
+ char *ptr;
+ int i;
+
+ /* This bit adds up to 48 bytes */
+ for (i = 0; i 3; i++) {
+ regs = cpuid(0x8002 + i);
+ name_as_ints[i * 4 + 0] =
