This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <s...@chromium.org>
---
arch/x86/Kconfig | 23 +++++
arch/x86/cpu/coreboot/coreboot.c | 8 ++
arch/x86/cpu/cpu.c | 32 ++++--
arch/x86/cpu/ivybridge/Kconfig | 157 +++++++++++++++++++++++++++++
arch/x86/cpu/ivybridge/Makefile | 9 ++
arch/x86/cpu/ivybridge/car.S | 20 ++++
arch/x86/cpu/ivybridge/cpu.c | 41 ++++++++
arch/x86/cpu/ivybridge/sdram.c | 20 ++++
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/include/asm/arch-ivybridge/gpio.h | 10 ++
arch/x86/include/asm/processor.h | 12 +++
board/google/chromebook_link/Kconfig | 15 +++
board/google/chromebook_link/MAINTAINERS | 6 ++
board/google/chromebook_link/Makefile | 15 +++
board/google/chromebook_link/link.c | 17 ++++
configs/chromebook_link_defconfig | 10 ++
include/configs/chromebook_link.h | 53 ++++++++++
18 files changed, 443 insertions(+), 7 deletions(-)
create mode 100644 arch/x86/cpu/ivybridge/Kconfig
create mode 100644 arch/x86/cpu/ivybridge/Makefile
create mode 100644 arch/x86/cpu/ivybridge/car.S
create mode 100644 arch/x86/cpu/ivybridge/cpu.c
create mode 100644 arch/x86/cpu/ivybridge/sdram.c
create mode 120000 arch/x86/dts/chromebook_link.dts
create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
create mode 100644 board/google/chromebook_link/Kconfig
create mode 100644 board/google/chromebook_link/MAINTAINERS
create mode 100644 board/google/chromebook_link/Makefile
create mode 100644 board/google/chromebook_link/link.c
create mode 100644 configs/chromebook_link_defconfig
create mode 100644 include/configs/chromebook_link.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0dba8ac..07ff149 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -12,9 +12,32 @@ choice
config TARGET_COREBOOT
bool "Support coreboot"
+ help
+ This target is used for running U-Boot on top of Coreboot. In
+ this case Coreboot does the early inititalisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as a fallback payload from Coreboot, in
+ Coreboot terminology. This method was used for the Chromebook
+ Pixel when launched.
+
+config TARGET_CHROMEBOOK_LINK
+ bool "Support Chromebook link"
+ help
+ This is the Chromebook Pixel released in 2013. It uses an Intel
+ i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+ SDRAM. It has a Panther Point peripheral controller hub, PCIe
+ WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+ reader, microphone and speakers, display port and 32GB SATA
+ solid state drive. There is a Chrome OS EC connected on LPC,
+ and it provides a 2560x1700 high resolution touch-enabled LCD
+ display.
endchoice
+source "arch/x86/cpu/ivybridge/Kconfig"
+
source "board/chromebook-x86/coreboot/Kconfig"
+source "board/google/chromebook_link/Kconfig"
+
endmenu
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c430ab1..257faa1 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -13,6 +13,7 @@
#include <ns16550.h>
#include <asm/msr.h>
#include <asm/cache.h>
+#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/arch-coreboot/tables.h>
#include <asm/arch-coreboot/sysinfo.h>
@@ -127,3 +128,10 @@ void panic_puts(const char *str)
while (*str)
NS16550_putc(port, *str++);
}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+
+ return 0;
+}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6441dde..61c198e 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -334,13 +334,6 @@ int cpu_has_64bit(void)
has_long_mode();
}
-int print_cpuinfo(void)
-{
- printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
-
- return 0;
-}
-
#define PAGETABLE_SIZE (6 * 4096)
/**
@@ -382,3 +375,28 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)
return -EFAULT;
}
+
+char *cpu_get_name(char *name)
+{
+ unsigned int *name_as_ints = (unsigned int *)name;
+ struct cpuid_result regs;
+ char *ptr;
+ int i;
+
+ /* This bit adds up to 48 bytes */
+ for (i = 0; i < 3; i++) {
+ regs = cpuid(0x80000002 + i);
+ name_as_ints[i * 4 + 0] = regs.eax;
+ name_as_ints[i * 4 + 1] = regs.ebx;
+ name_as_ints[i * 4 + 2] = regs.ecx;
+ name_as_ints[i * 4 + 3] = regs.edx;
+ }
+ name[CPU_MAX_NAME_LEN - 1] = '\0';
+
+ /* Skip leading spaces. */
+ ptr = name;
+ while (*ptr == ' ')
+ ptr++;
+
+ return ptr;
+}
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
new file mode 100644
index 0000000..030d813
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -0,0 +1,157 @@
+#
+# From Coreboot src/northbridge/intel/sandybridge/Kconfig
+#
+# Copyright (C) 2010 Google Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+
+config NORTHBRIDGE_INTEL_SANDYBRIDGE
+ bool
+ select CACHE_MRC_BIN
+ select CPU_INTEL_MODEL_206AX
+
+config NORTHBRIDGE_INTEL_IVYBRIDGE
+ bool
+ select CACHE_MRC_BIN
+ select CPU_INTEL_MODEL_306AX
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE
+
+config VGA_BIOS_ID
+ string
+ default "8086,0106"
+
+config CACHE_MRC_SIZE_KB
+ int
+ default 256
+
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x1ec000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x10000
+
+endif
+
+if NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config EXTERNAL_MRC_BLOB
+ bool
+ default n
+
+config CACHE_MRC_SIZE_KB
+ int
+ default 512
+
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x370000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xff7e0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x20000
+
+endif
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config HAVE_MRC
+ bool "Add a System Agent binary"
+ help
+ Select this option to add a System Agent binary to
+ the resulting U-Boot image. MRC stands for Memory Reference Code.
+ It is a binary blob which U-Boot uses to set up SDRAM.
+
+ Note: Without this binary U-Boot will not be able to set up its
+ SDRAM so will not boot.
+
+config DCACHE_RAM_MRC_VAR_SIZE
+ hex
+ default 0x4000
+ help
+ This is the amount of CAR (Cache as RAM) reserved for use by the
+ memory reference code. This should be set to 16KB (0x4000 hex)
+ so that MRC has enough space to run.
+
+config MRC_FILE
+ string "Intel System Agent path and filename"
+ depends on HAVE_MRC
+ default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
+ help
+ The path and filename of the file to use as System Agent
+ binary.
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select SMM_TSEG
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select SMP
+ select SSE2
+ select UDELAY_LAPIC
+ select CPU_MICROCODE_IN_CBFS
+ select TSC_SYNC_MFENCE
+
+config SMM_TSEG_SIZE
+ hex
+ default 0x800000
+
+config ENABLE_VMX
+ bool "Enable VMX for virtualization"
+ default n
+
+endif
+
+config CPU_INTEL_SOCKET_RPGA989
+ bool
+
+if CPU_INTEL_SOCKET_RPGA989
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select MMX
+ select SSE
+ select CACHE_AS_RAM
+
+config CACHE_MRC_BIN
+ bool
+ default n
+
+endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
new file mode 100644
index 0000000..dbcd4bd
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += car.o
+obj-y += cpu.o
+obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S
new file mode 100644
index 0000000..0480813
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/car.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminn...@gmail.com>
+ * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.mal...@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+
+ /* Note: ebp must not be touched in this code */
+.globl car_init
+car_init:
+ /* TODO: Add cache-as-RAM init here */
+ jmp car_init_ret
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
new file mode 100644
index 0000000..7e77be6
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.r...@gmail.com.
+ *
+ * Some portions from coreboot src/mainboard/google/link/romstage.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+ int ret;
+
+ timer_set_base(rdtsc());
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ char processor_name[CPU_MAX_NAME_LEN];
+ const char *name;
+
+ /* Print processor name */
+ name = cpu_get_name(processor_name);
+ printf("CPU: %s\n", name);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
new file mode 100644
index 0000000..5f9ae5e
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011
+ * Graeme Russ, <graeme.r...@gmail.com>
+ *
+ * Portions from Coreboot mainboard/google/link/romstage.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+
+int dram_init(void)
+{
+ /* TODO: Set up DRAM */
+
+ return 0;
+}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 48265ef..bb3b116 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,4 +1,5 @@
dtb-y += link.dtb \
+ chromebook_link.dtb \
alex.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
new file mode 120000
index 0000000..6f8c5cd
--- /dev/null
+++ b/arch/x86/dts/chromebook_link.dts
@@ -0,0 +1 @@
+link.dts
\ No newline at end of file
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h
b/arch/x86/include/asm/arch-ivybridge/gpio.h
new file mode 100644
index 0000000..4951a8c
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2014, Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 30d7d48..2c33723 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -149,6 +149,18 @@ static inline unsigned int cpuid_edx(unsigned int op)
: "ecx", "edi");
return edx;
}
+
+#define CPU_MAX_NAME_LEN 49
+
+/**
+ * cpu_get_name() - Get the name of the current cpu
+ *
+ * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
+ * @return pointer to name, which will likely be a few bytes after the start
+ * of @name
+ * \0 terminator
+ */
+char *cpu_get_name(char *name);
#endif /* __ASSEMBLY__ */
#endif
diff --git a/board/google/chromebook_link/Kconfig
b/board/google/chromebook_link/Kconfig
new file mode 100644
index 0000000..975d557
--- /dev/null
+++ b/board/google/chromebook_link/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CHROMEBOOK_LINK
+
+config SYS_BOARD
+ default "chromebook_link"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "ivybridge"
+
+config SYS_CONFIG_NAME
+ default "chromebook_link"
+
+endif
diff --git a/board/google/chromebook_link/MAINTAINERS
b/board/google/chromebook_link/MAINTAINERS
new file mode 100644
index 0000000..bc253a2
--- /dev/null
+++ b/board/google/chromebook_link/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK LINK BOARD
+M: Simon Glass <s...@chromium.org>
+S: Maintained
+F: board/google/chromebook_link/
+F: include/configs/chromebook_link.h
+F: configs/chromebook_link_defconfig
diff --git a/board/google/chromebook_link/Makefile
b/board/google/chromebook_link/Makefile
new file mode 100644
index 0000000..a133c2e
--- /dev/null
+++ b/board/google/chromebook_link/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.r...@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, dan...@omicron.se.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += link.o
diff --git a/board/google/chromebook_link/link.c
b/board/google/chromebook_link/link.c
new file mode 100644
index 0000000..ffa9d60
--- /dev/null
+++ b/board/google/chromebook_link/link.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+int arch_early_init_r(void)
+{
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ return 0;
+}
diff --git a/configs/chromebook_link_defconfig
b/configs/chromebook_link_defconfig
new file mode 100644
index 0000000..b83803e
--- /dev/null
+++ b/configs/chromebook_link_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_CHROMEBOOK_LINK=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
+CONFIG_HAVE_MRC=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
new file mode 100644
index 0000000..1d6f55b
--- /dev/null
+++ b/include/configs/chromebook_link.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.r...@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_CAR_ADDR 0xff7e0000
+#define CONFIG_SYS_CAR_SIZE (128 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_NR_DRAM_BANKS 8
+
+/*
+ * These common x86 features are not yet supported, but are added in
+ * follow-on patches in this series. Add undefs here to avoid every patch
+ * having to put things back into x86-common.h
+ */
+#undef CONFIG_INTEL_ICH6_GPIO
+#undef CONFIG_DM_GPIO
+#undef CONFIG_CMD_GPIO
+#undef CONFIG_CROS_EC
+#undef CONFIG_CROS_EC_LPC
+#undef CONFIG_CMD_CROS_EC
+#undef CONFIG_ARCH_EARLY_INIT_R
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+#undef CONFIG_SYS_EARLY_PCI_INIT
+#undef CONFIG_PCI
+#undef CONFIG_ICH_SPI
+#undef CONFIG_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SF
+#undef CONFIG_USB_EHCI
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_SCSI
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
+ "stdout=vga,serial\0" \
+ "stderr=vga,serial\0"
+
+#endif /* __CONFIG_H */
--
2.1.0.rc2.206.gedb03e5
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