Re: [U-Boot] [PATCH 21/39] x86: chromebook_link: Implement CAR support (cache as RAM)
Hi Bin, On 7 November 2014 07:07, Bin Meng wrote: > Hi Simon, > > On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote: >> Add support for CAR so that we have memory to use prior to DRAM init. >> On link there is a total of 128KB of CAR available, although some is >> used for the memory reference code. >> >> Signed-off-by: Simon Glass >> --- >> >> arch/x86/Kconfig | 16 >> arch/x86/cpu/ivybridge/car.S | 156 >> ++- >> arch/x86/cpu/ivybridge/cpu.c | 2 + >> arch/x86/include/asm/mtrr.h | 121 +++ >> arch/x86/include/asm/post.h | 13 ++- >> board/google/chromebook_link/Kconfig | 12 +++ >> 6 files changed, 318 insertions(+), 2 deletions(-) >> create mode 100644 arch/x86/include/asm/mtrr.h >> >> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig >> index d9ce129..73fe8b2 100644 >> --- a/arch/x86/Kconfig >> +++ b/arch/x86/Kconfig >> @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK >> >> endchoice >> >> +config RAMBASE >> + hex >> + default 0x10 >> + >> +config RAMTOP >> + hex >> + default 0x20 >> + >> +config XIP_ROM_SIZE >> + hex >> + default 0x1 >> + >> +config CPU_ADDR_BITS >> + int >> + default 36 >> + >> config ROM_SIZE >> hex >> default 0x80 >> diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S >> index 0480813..391f6df 100644 >> --- a/arch/x86/cpu/ivybridge/car.S >> +++ b/arch/x86/cpu/ivybridge/car.S >> @@ -12,9 +12,163 @@ >> */ >> >> #include >> +#include >> +#include >> +#include >> + >> +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) >> +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) > > Should these macros be all capital? Yes I'll fix that. I had in mind keeping it similar to where it came from, but there are lots of changes needed so it's not worth it. > >> +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE >> +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE >> + >> +/* Cache 4GB - MRC_SIZE_KB for MRC */ >> +#define CACHE_MRC_BYTES((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) >> +#define CACHE_MRC_BASE (0x - CACHE_MRC_BYTES) >> +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) >> + >> +#define CPU_PHYSMASK_HI(1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) >> + >> +#define NoEvictMod_MSR 0x2e0 > > Ditto. > >> /* Note: ebp must not be touched in this code */ > > I think mentioning ebp holds the value of BIST would help more? OK > >> .globl car_init >> car_init: >> - /* TODO: Add cache-as-RAM init here */ >> + post_code(POST_CAR_START) >> + >> + /* Send INIT IPI to all excluding ourself */ >> + movl$0x000C4500, %eax >> + movl$0xFEE00300, %esi >> + movl%eax, (%esi) >> + >> + /* All CPUs need to be in Wait for SIPI state */ >> +wait_for_sipi: >> + movl(%esi), %eax >> + bt $12, %eax >> + jc wait_for_sipi > > Is this a must to send INIT IPI before CAR initialization? I'll test it. [snip] Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 21/39] x86: chromebook_link: Implement CAR support (cache as RAM)
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote: > Add support for CAR so that we have memory to use prior to DRAM init. > On link there is a total of 128KB of CAR available, although some is > used for the memory reference code. > > Signed-off-by: Simon Glass > --- > > arch/x86/Kconfig | 16 > arch/x86/cpu/ivybridge/car.S | 156 > ++- > arch/x86/cpu/ivybridge/cpu.c | 2 + > arch/x86/include/asm/mtrr.h | 121 +++ > arch/x86/include/asm/post.h | 13 ++- > board/google/chromebook_link/Kconfig | 12 +++ > 6 files changed, 318 insertions(+), 2 deletions(-) > create mode 100644 arch/x86/include/asm/mtrr.h > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index d9ce129..73fe8b2 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK > > endchoice > > +config RAMBASE > + hex > + default 0x10 > + > +config RAMTOP > + hex > + default 0x20 > + > +config XIP_ROM_SIZE > + hex > + default 0x1 > + > +config CPU_ADDR_BITS > + int > + default 36 > + > config ROM_SIZE > hex > default 0x80 > diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S > index 0480813..391f6df 100644 > --- a/arch/x86/cpu/ivybridge/car.S > +++ b/arch/x86/cpu/ivybridge/car.S > @@ -12,9 +12,163 @@ > */ > > #include > +#include > +#include > +#include > + > +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) > +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) Should these macros be all capital? > +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE > +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE > + > +/* Cache 4GB - MRC_SIZE_KB for MRC */ > +#define CACHE_MRC_BYTES((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) > +#define CACHE_MRC_BASE (0x - CACHE_MRC_BYTES) > +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) > + > +#define CPU_PHYSMASK_HI(1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) > + > +#define NoEvictMod_MSR 0x2e0 Ditto. > /* Note: ebp must not be touched in this code */ I think mentioning ebp holds the value of BIST would help more? > .globl car_init > car_init: > - /* TODO: Add cache-as-RAM init here */ > + post_code(POST_CAR_START) > + > + /* Send INIT IPI to all excluding ourself */ > + movl$0x000C4500, %eax > + movl$0xFEE00300, %esi > + movl%eax, (%esi) > + > + /* All CPUs need to be in Wait for SIPI state */ > +wait_for_sipi: > + movl(%esi), %eax > + bt $12, %eax > + jc wait_for_sipi Is this a must to send INIT IPI before CAR initialization? > + post_code(POST_CAR_SIPI) > + /* Zero out all fixed range and variable range MTRRs */ > + movl$mtrr_table, %esi > + movl$((mtrr_table_end - mtrr_table) / 2), %edi > + xorl%eax, %eax > + xorl%edx, %edx > +clear_mtrrs: > + movw(%esi), %bx > + movzx %bx, %ecx > + wrmsr > + add $2, %esi > + dec %edi > + jnz clear_mtrrs > + > + post_code(POST_CAR_MTRR) > + /* Configure the default memory type to uncacheable */ > + movl$MTRRdefType_MSR, %ecx > + rdmsr > + andl$(~0x0cff), %eax > + wrmsr > + > + post_code(POST_CAR_UNCACHEABLE) > + /* Set Cache-as-RAM base address */ > + movl$(MTRRphysBase_MSR(0)), %ecx > + movl$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax > + xorl%edx, %edx > + wrmsr > + > + post_code(POST_CAR_BASE_ADDRESS) > + /* Set Cache-as-RAM mask */ > + movl$(MTRRphysMask_MSR(0)), %ecx > + movl$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax > + movl$CPU_PHYSMASK_HI, %edx > + wrmsr > + > + post_code(POST_CAR_MASK) > + > + /* Enable MTRR */ > + movl$MTRRdefType_MSR, %ecx > + rdmsr > + orl $MTRRdefTypeEn, %eax > + wrmsr > + > + /* Enable cache (CR0.CD = 0, CR0.NW = 0) */ > +movl %cr0, %eax > + andl$(~(X86_CR0_CD | X86_CR0_NW)), %eax > + invd > + movl%eax, %cr0 > + > + /* enable the 'no eviction' mode */ > + movl$NoEvictMod_MSR, %ecx > + rdmsr > + orl $1, %eax > + andl$~2, %eax > + wrmsr > + > + /* Clear the cache memory region. This will also fill up the cache */ > + movl$CACHE_AS_RAM_BASE, %esi > + movl%esi, %edi > + movl$(CACHE_AS_RAM_SIZE / 4), %ecx > + xorl%eax, %eax > + rep stosl > + > + /* enable the 'no eviction run' state */ > + movl$NoEvictMod_MSR, %ecx > + rdmsr > + orl $3, %eax > + wrmsr > + > + post_code(POST_CAR_FILL) > + /* Enable Cache-as-RAM mode by disabling cache */ > +
[U-Boot] [PATCH 21/39] x86: chromebook_link: Implement CAR support (cache as RAM)
Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 16 arch/x86/cpu/ivybridge/car.S | 156 ++- arch/x86/cpu/ivybridge/cpu.c | 2 + arch/x86/include/asm/mtrr.h | 121 +++ arch/x86/include/asm/post.h | 13 ++- board/google/chromebook_link/Kconfig | 12 +++ 6 files changed, 318 insertions(+), 2 deletions(-) create mode 100644 arch/x86/include/asm/mtrr.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d9ce129..73fe8b2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK endchoice +config RAMBASE + hex + default 0x10 + +config RAMTOP + hex + default 0x20 + +config XIP_ROM_SIZE + hex + default 0x1 + +config CPU_ADDR_BITS + int + default 36 + config ROM_SIZE hex default 0x80 diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S index 0480813..391f6df 100644 --- a/arch/x86/cpu/ivybridge/car.S +++ b/arch/x86/cpu/ivybridge/car.S @@ -12,9 +12,163 @@ */ #include +#include +#include +#include + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache 4GB - MRC_SIZE_KB for MRC */ +#define CACHE_MRC_BYTES((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0x - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) + +#define CPU_PHYSMASK_HI(1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) + +#define NoEvictMod_MSR 0x2e0 /* Note: ebp must not be touched in this code */ .globl car_init car_init: - /* TODO: Add cache-as-RAM init here */ + post_code(POST_CAR_START) + + /* Send INIT IPI to all excluding ourself */ + movl$0x000C4500, %eax + movl$0xFEE00300, %esi + movl%eax, (%esi) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl(%esi), %eax + bt $12, %eax + jc wait_for_sipi + + post_code(POST_CAR_SIPI) + /* Zero out all fixed range and variable range MTRRs */ + movl$mtrr_table, %esi + movl$((mtrr_table_end - mtrr_table) / 2), %edi + xorl%eax, %eax + xorl%edx, %edx +clear_mtrrs: + movw(%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + post_code(POST_CAR_MTRR) + /* Configure the default memory type to uncacheable */ + movl$MTRRdefType_MSR, %ecx + rdmsr + andl$(~0x0cff), %eax + wrmsr + + post_code(POST_CAR_UNCACHEABLE) + /* Set Cache-as-RAM base address */ + movl$(MTRRphysBase_MSR(0)), %ecx + movl$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl%edx, %edx + wrmsr + + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask */ + movl$(MTRRphysMask_MSR(0)), %ecx + movl$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl$CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(POST_CAR_MASK) + + /* Enable MTRR */ + movl$MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0) */ +movl %cr0, %eax + andl$(~(X86_CR0_CD | X86_CR0_NW)), %eax + invd + movl%eax, %cr0 + + /* enable the 'no eviction' mode */ + movl$NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + andl$~2, %eax + wrmsr + + /* Clear the cache memory region. This will also fill up the cache */ + movl$CACHE_AS_RAM_BASE, %esi + movl%esi, %edi + movl$(CACHE_AS_RAM_SIZE / 4), %ecx + xorl%eax, %eax + rep stosl + + /* enable the 'no eviction run' state */ + movl$NoEvictMod_MSR, %ecx + rdmsr + orl $3, %eax + wrmsr + + post_code(POST_CAR_FILL) + /* Enable Cache-as-RAM mode by disabling cache */ + movl%cr0, %eax + orl $X86_CR0_CD, %eax + movl%eax, %cr0 + + /* Enable cache for our code in Flash because we do XIP here */ + movl$MTRRphysBase_MSR(1), %ecx + xorl%edx, %edx + movl$car_init_ret, %eax + andl$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRPROT, %eax + wrmsr + + movl$MTRRphysMask_MSR(1), %ecx + movl$CPU_PHYSMASK_HI, %edx + movl$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax +
