Re: [U-Boot] [PATCH V3 2/2] net: add driver for Synopsys Ethernet QoS device

[Joe Hershberger]

Hi Stephen,

On Fri, Oct 21, 2016 at 3:46 PM, Stephen Warren  wrote:
> From: Stephen Warren 
>
> This driver supports the Synopsys Designware Ethernet QoS (Quality of
> Service) a/k/a eqos IP block, which is a different design than the HW
> supported by the existing designware.c driver. The IP supports many
> options for bus type, clocking/reset structure, and feature list. This
> driver currently supports the specific configuration used in NVIDIA's
> Tegra186 chip, but should be extensible to other combinations quite
> easily, as explained in the source.
>
> Signed-off-by: Stephen Warren 
> Reviewed-by: Simon Glass  # V1

Acked-by: Joe Hershberger 

I'll kick off a build test tonight.

-Joe
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Re: [U-Boot] [PATCH V3 2/2] net: add driver for Synopsys Ethernet QoS device

[Joe Hershberger]

On Mon, Oct 31, 2016 at 10:48 AM, Stephen Warren  wrote:
> On 10/21/2016 02:46 PM, Stephen Warren wrote:
>>
>> From: Stephen Warren 
>>
>> This driver supports the Synopsys Designware Ethernet QoS (Quality of
>> Service) a/k/a eqos IP block, which is a different design than the HW
>> supported by the existing designware.c driver. The IP supports many
>> options for bus type, clocking/reset structure, and feature list. This
>> driver currently supports the specific configuration used in NVIDIA's
>> Tegra186 chip, but should be extensible to other combinations quite
>> easily, as explained in the source.
>>
>> Signed-off-by: Stephen Warren 
>> Reviewed-by: Simon Glass  # V1
>> ---
>> v3:
>> * Use structs to describe register layout.
>> * Implement write_hwaddr(). This requires tracking whether registers are
>>   accessible and knowing for which configurations this matters.
>> * Add full description of Tegra186 HW block configuration.
>> * s/tegra/tegra186/ in symbol names.
>> * Use a single struct type for all descriptors, with field names that
>>   match the HW documentation.
>
>
> Joe, does this new version look good? I believe it addresses all your
> previous comments. Thanks.

Hi Stephen,

Apologies, I haven't gotten back to reviewing this... I'll try to get
to it today or tomorrow.

-Joe
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Re: [U-Boot] [PATCH V3 2/2] net: add driver for Synopsys Ethernet QoS device

[Stephen Warren]

On 10/21/2016 02:46 PM, Stephen Warren wrote:

From: Stephen Warren 

This driver supports the Synopsys Designware Ethernet QoS (Quality of
Service) a/k/a eqos IP block, which is a different design than the HW
supported by the existing designware.c driver. The IP supports many
options for bus type, clocking/reset structure, and feature list. This
driver currently supports the specific configuration used in NVIDIA's
Tegra186 chip, but should be extensible to other combinations quite
easily, as explained in the source.

Signed-off-by: Stephen Warren 
Reviewed-by: Simon Glass  # V1
---
v3:
* Use structs to describe register layout.
* Implement write_hwaddr(). This requires tracking whether registers are
  accessible and knowing for which configurations this matters.
* Add full description of Tegra186 HW block configuration.
* s/tegra/tegra186/ in symbol names.
* Use a single struct type for all descriptors, with field names that
  match the HW documentation.


Joe, does this new version look good? I believe it addresses all your 
previous comments. Thanks.

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[U-Boot] [PATCH V3 2/2] net: add driver for Synopsys Ethernet QoS device

[Stephen Warren]

From: Stephen Warren 

This driver supports the Synopsys Designware Ethernet QoS (Quality of
Service) a/k/a eqos IP block, which is a different design than the HW
supported by the existing designware.c driver. The IP supports many
options for bus type, clocking/reset structure, and feature list. This
driver currently supports the specific configuration used in NVIDIA's
Tegra186 chip, but should be extensible to other combinations quite
easily, as explained in the source.

Signed-off-by: Stephen Warren 
Reviewed-by: Simon Glass  # V1
---
v3:
* Use structs to describe register layout.
* Implement write_hwaddr(). This requires tracking whether registers are
  accessible and knowing for which configurations this matters.
* Add full description of Tegra186 HW block configuration.
* s/tegra/tegra186/ in symbol names.
* Use a single struct type for all descriptors, with field names that
  match the HW documentation.
v2:
* Add note about x86 IO coherency.
* Use wait_bit() where possible.
* Use a struct definition of the RX and TX descriptors.
---
 drivers/net/Kconfig   |   11 +
 drivers/net/Makefile  |1 +
 drivers/net/dwc_eth_qos.c | 1552 +
 3 files changed, 1564 insertions(+)
 create mode 100644 drivers/net/dwc_eth_qos.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 302c005aa132..d18295a28655 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -64,6 +64,17 @@ config ALTERA_TSE
  Please find details on the "Triple-Speed Ethernet MegaCore Function
  Resource Center" of Altera.
 
+config DWC_ETH_QOS
+   bool "Synopsys DWC Ethernet QOS device support"
+   depends on DM_ETH
+   select PHYLIB
+   help
+ This driver supports the Synopsys Designware Ethernet QOS (Quality
+ Of Service) IP block. The IP supports many options for bus type,
+ clocking/reset structure, and feature list. This driver currently
+ supports the specific configuration used in NVIDIA's Tegra186 chip,
+ but should be extensible to other combinations quite easily.
+
 config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
help
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a4485266d457..9a7bfc6d5b05 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
 obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
+obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
new file mode 100644
index ..81eeba2e051a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos.c
@@ -0,0 +1,1552 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Portions based on U-Boot's rtl8169.c.
+ */
+
+/*
+ * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
+ * Service) IP block. The IP supports multiple options for bus type, clocking/
+ * reset structure, and feature list.
+ *
+ * The driver is written such that generic core logic is kept separate from
+ * configuration-specific logic. Code that interacts with configuration-
+ * specific resources is split out into separate functions to avoid polluting
+ * common code. If/when this driver is enhanced to support multiple
+ * configurations, the core code should be adapted to call all configuration-
+ * specific functions through function pointers, with the definition of those
+ * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
+ * field.
+ *
+ * The following configurations are currently supported:
+ * tegra186:
+ *NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
+ *AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
+ *supports a single RGMII PHY. This configuration also has SW control over
+ *all clock and reset signals to the HW block.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Core registers */
+
+#define EQOS_MAC_REGS_BASE 0x000
+struct eqos_mac_regs {
+   uint32_t configuration; /* 0x000 */
+   uint32_t unused_004[(0x070 - 0x004) / 4];   /* 0x004 */
+   uint32_t q0_tx_flow_ctrl;   /* 0x070 */
+   uint32_t unused_070[(0x090 - 0x074) / 4];   /* 0x074 */
+   uint32_t rx_flow_ctrl;  /* 0x090 */
+   uint32_t unused_094;/* 0x094 */
+   uint32_t txq_prty_map0; /* 0x098 */
+   uint32_t unused_09c;/* 0x09c */
+   uint32_t rxq_ctrl0; /* 0x0a0 */
+   uint32_t unused_0a4;/* 0x0a4 */
+