Re: [U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

2018-04-27 Thread Marek Vasut 
On 04/27/2018 04:14 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 10:58 AM, Marek Vasut  wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Add SPL driver support for Stratix SoC
>>>
>>> Signed-off-by: Chin Liang See 
>>> Signed-off-by: Ley Foon Tan 
>>> ---
>>>  arch/arm/mach-socfpga/Makefile|4 +
>>>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +
>>>  arch/arm/mach-socfpga/spl_s10.c   |  205 
>>> +
>>>  3 files changed, 293 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
>>>
>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>> index b669d43..35b124a 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -40,6 +40,7 @@ obj-y   += system_manager_s10.o
>>>  obj-y+= wrap_pinmux_config_s10.o
>>>  obj-y+= wrap_pll_config_s10.o
>>>  endif
>>> +
>>>  ifdef CONFIG_SPL_BUILD
>>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>  obj-y+= spl_gen5.o
>>> @@ -51,6 +52,9 @@ endif
>>>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>>>  obj-y+= spl_a10.o
>>>  endif
>>> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>> +obj-y+= spl_s10.o
>>> +endif
>>>  endif
>>>
>>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
>>> b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>> new file mode 100644
>>> index 000..70aa9a6
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>> @@ -0,0 +1,84 @@
>>> +/* SPDX-License-Identifier: GPL-2.0
>>> + *
>>> + * Copyright (C) 2017-2018 Intel Corporation 
>>> + *
>>> + */
>>> +
>>> +#ifndef  _FIREWALL_S10_
>>> +#define  _FIREWALL_S10_
>>> +
>>> +struct socfpga_firwall_l4_per {
>>> + u32 nand;   /* 0x00 */
>>> + u32 nand_data;
>>> + u32 _pad_0x8;
>>> + u32 usb0;
>>> + u32 usb1;   /* 0x10 */
>>> + u32 _pad_0x14;
>>> + u32 _pad_0x18;
>>> + u32 spim0;
>>> + u32 spim1;  /* 0x20 */
>>> + u32 spis0;
>>> + u32 spis1;
>>> + u32 emac0;
>>> + u32 emac1;  /* 0x30 */
>>> + u32 emac2;
>>> + u32 _pad_0x38;
>>> + u32 _pad_0x3c;
>>> + u32 sdmmc;  /* 0x40 */
>>> + u32 gpio0;
>>> + u32 gpio1;
>>> + u32 _pad_0x4c;
>>> + u32 i2c0;   /* 0x50 */
>>> + u32 i2c1;
>>> + u32 i2c2;
>>> + u32 i2c3;
>>> + u32 i2c4;   /* 0x60 */
>>> + u32 timer0;
>>> + u32 timer1;
>>> + u32 uart0;
>>> + u32 uart1;  /* 0x70 */
>>> +};
>>> +
>>> +struct socfpga_firwall_l4_sys {
>>> + u32 _pad_0x00;  /* 0x00 */
>>> + u32 _pad_0x04;
>>> + u32 dma_ecc;
>>> + u32 emac0rx_ecc;
>>> + u32 emac0tx_ecc;/* 0x10 */
>>> + u32 emac1rx_ecc;
>>> + u32 emac1tx_ecc;
>>> + u32 emac2rx_ecc;
>>> + u32 emac2tx_ecc;/* 0x20 */
>>> + u32 _pad_0x24;
>>> + u32 _pad_0x28;
>>> + u32 nand_ecc;
>>> + u32 nand_read_ecc;  /* 0x30 */
>>> + u32 nand_write_ecc;
>>> + u32 ocram_ecc;
>>> + u32 _pad_0x3c;
>>> + u32 sdmmc_ecc;  /* 0x40 */
>>> + u32 usb0_ecc;
>>> + u32 usb1_ecc;
>>> + u32 clock_manager;
>>> + u32 _pad_0x50;  /* 0x50 */
>>> + u32 io_manager;
>>> + u32 reset_manager;
>>> + u32 system_manager;
>>> + u32 osc0_timer; /* 0x60 */
>>> + u32 osc1_timer;
>>> + u32 watchdog0;
>>> + u32 watchdog1;
>>> + u32 watchdog2;  /* 0x70 */
>>> + u32 watchdog3;
>>> +};
>>> +
>>> +#define FIREWALL_L4_DISABLE_ALL  (BIT(0) | BIT(24) | BIT(16))
>>> +#define FIREWALL_BRIDGE_DISABLE_ALL  (~0)
>>> +
>>> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR   0xf7004688
>>> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR0xf7018628
>>> +
>>> +#define CCU_ADMASK_P_MASK(BIT(0))
>>> +#define CCU_ADMASK_NS_MASK   (BIT(1))
>>
>> Drop outer parenthesis
> Noted.
>>
>>> +
>>> +#endif /* _FIREWALL_S10_ */
>>> diff --git a/arch/arm/mach-socfpga/spl_s10.c 
>>> b/arch/arm/mach-socfpga/spl_s10.c
>>> new file mode 100644
>>> index 000..3b3833d
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>>> @@ -0,0 +1,205 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2016-2018 Intel Corporation 
>>> + *
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +

Re: [U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

2018-04-26 Thread Ley Foon Tan 
On Thu, Apr 19, 2018 at 10:58 AM, Marek Vasut  wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add SPL driver support for Stratix SoC
>>
>> Signed-off-by: Chin Liang See 
>> Signed-off-by: Ley Foon Tan 
>> ---
>>  arch/arm/mach-socfpga/Makefile|4 +
>>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +
>>  arch/arm/mach-socfpga/spl_s10.c   |  205 
>> +
>>  3 files changed, 293 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index b669d43..35b124a 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -40,6 +40,7 @@ obj-y   += system_manager_s10.o
>>  obj-y+= wrap_pinmux_config_s10.o
>>  obj-y+= wrap_pll_config_s10.o
>>  endif
>> +
>>  ifdef CONFIG_SPL_BUILD
>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>  obj-y+= spl_gen5.o
>> @@ -51,6 +52,9 @@ endif
>>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>>  obj-y+= spl_a10.o
>>  endif
>> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>> +obj-y+= spl_s10.o
>> +endif
>>  endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
>> b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>> new file mode 100644
>> index 000..70aa9a6
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>> @@ -0,0 +1,84 @@
>> +/* SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Copyright (C) 2017-2018 Intel Corporation 
>> + *
>> + */
>> +
>> +#ifndef  _FIREWALL_S10_
>> +#define  _FIREWALL_S10_
>> +
>> +struct socfpga_firwall_l4_per {
>> + u32 nand;   /* 0x00 */
>> + u32 nand_data;
>> + u32 _pad_0x8;
>> + u32 usb0;
>> + u32 usb1;   /* 0x10 */
>> + u32 _pad_0x14;
>> + u32 _pad_0x18;
>> + u32 spim0;
>> + u32 spim1;  /* 0x20 */
>> + u32 spis0;
>> + u32 spis1;
>> + u32 emac0;
>> + u32 emac1;  /* 0x30 */
>> + u32 emac2;
>> + u32 _pad_0x38;
>> + u32 _pad_0x3c;
>> + u32 sdmmc;  /* 0x40 */
>> + u32 gpio0;
>> + u32 gpio1;
>> + u32 _pad_0x4c;
>> + u32 i2c0;   /* 0x50 */
>> + u32 i2c1;
>> + u32 i2c2;
>> + u32 i2c3;
>> + u32 i2c4;   /* 0x60 */
>> + u32 timer0;
>> + u32 timer1;
>> + u32 uart0;
>> + u32 uart1;  /* 0x70 */
>> +};
>> +
>> +struct socfpga_firwall_l4_sys {
>> + u32 _pad_0x00;  /* 0x00 */
>> + u32 _pad_0x04;
>> + u32 dma_ecc;
>> + u32 emac0rx_ecc;
>> + u32 emac0tx_ecc;/* 0x10 */
>> + u32 emac1rx_ecc;
>> + u32 emac1tx_ecc;
>> + u32 emac2rx_ecc;
>> + u32 emac2tx_ecc;/* 0x20 */
>> + u32 _pad_0x24;
>> + u32 _pad_0x28;
>> + u32 nand_ecc;
>> + u32 nand_read_ecc;  /* 0x30 */
>> + u32 nand_write_ecc;
>> + u32 ocram_ecc;
>> + u32 _pad_0x3c;
>> + u32 sdmmc_ecc;  /* 0x40 */
>> + u32 usb0_ecc;
>> + u32 usb1_ecc;
>> + u32 clock_manager;
>> + u32 _pad_0x50;  /* 0x50 */
>> + u32 io_manager;
>> + u32 reset_manager;
>> + u32 system_manager;
>> + u32 osc0_timer; /* 0x60 */
>> + u32 osc1_timer;
>> + u32 watchdog0;
>> + u32 watchdog1;
>> + u32 watchdog2;  /* 0x70 */
>> + u32 watchdog3;
>> +};
>> +
>> +#define FIREWALL_L4_DISABLE_ALL  (BIT(0) | BIT(24) | BIT(16))
>> +#define FIREWALL_BRIDGE_DISABLE_ALL  (~0)
>> +
>> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR   0xf7004688
>> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR0xf7018628
>> +
>> +#define CCU_ADMASK_P_MASK(BIT(0))
>> +#define CCU_ADMASK_NS_MASK   (BIT(1))
>
> Drop outer parenthesis
Noted.
>
>> +
>> +#endif /* _FIREWALL_S10_ */
>> diff --git a/arch/arm/mach-socfpga/spl_s10.c 
>> b/arch/arm/mach-socfpga/spl_s10.c
>> new file mode 100644
>> index 000..3b3833d
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>> @@ -0,0 +1,205 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016-2018 Intel Corporation 
>> + *
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
>> + (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
>> +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =

Re: [U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

2018-04-18 Thread Marek Vasut 
On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add SPL driver support for Stratix SoC
> 
> Signed-off-by: Chin Liang See 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/Makefile|4 +
>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +
>  arch/arm/mach-socfpga/spl_s10.c   |  205 
> +
>  3 files changed, 293 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b669d43..35b124a 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -40,6 +40,7 @@ obj-y   += system_manager_s10.o
>  obj-y+= wrap_pinmux_config_s10.o
>  obj-y+= wrap_pll_config_s10.o
>  endif
> +
>  ifdef CONFIG_SPL_BUILD
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>  obj-y+= spl_gen5.o
> @@ -51,6 +52,9 @@ endif
>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>  obj-y+= spl_a10.o
>  endif
> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
> +obj-y+= spl_s10.o
> +endif
>  endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
> b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
> new file mode 100644
> index 000..70aa9a6
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2017-2018 Intel Corporation 
> + *
> + */
> +
> +#ifndef  _FIREWALL_S10_
> +#define  _FIREWALL_S10_
> +
> +struct socfpga_firwall_l4_per {
> + u32 nand;   /* 0x00 */
> + u32 nand_data;
> + u32 _pad_0x8;
> + u32 usb0;
> + u32 usb1;   /* 0x10 */
> + u32 _pad_0x14;
> + u32 _pad_0x18;
> + u32 spim0;
> + u32 spim1;  /* 0x20 */
> + u32 spis0;
> + u32 spis1;
> + u32 emac0;
> + u32 emac1;  /* 0x30 */
> + u32 emac2;
> + u32 _pad_0x38;
> + u32 _pad_0x3c;
> + u32 sdmmc;  /* 0x40 */
> + u32 gpio0;
> + u32 gpio1;
> + u32 _pad_0x4c;
> + u32 i2c0;   /* 0x50 */
> + u32 i2c1;
> + u32 i2c2;
> + u32 i2c3;
> + u32 i2c4;   /* 0x60 */
> + u32 timer0;
> + u32 timer1;
> + u32 uart0;
> + u32 uart1;  /* 0x70 */
> +};
> +
> +struct socfpga_firwall_l4_sys {
> + u32 _pad_0x00;  /* 0x00 */
> + u32 _pad_0x04;
> + u32 dma_ecc;
> + u32 emac0rx_ecc;
> + u32 emac0tx_ecc;/* 0x10 */
> + u32 emac1rx_ecc;
> + u32 emac1tx_ecc;
> + u32 emac2rx_ecc;
> + u32 emac2tx_ecc;/* 0x20 */
> + u32 _pad_0x24;
> + u32 _pad_0x28;
> + u32 nand_ecc;
> + u32 nand_read_ecc;  /* 0x30 */
> + u32 nand_write_ecc;
> + u32 ocram_ecc;
> + u32 _pad_0x3c;
> + u32 sdmmc_ecc;  /* 0x40 */
> + u32 usb0_ecc;
> + u32 usb1_ecc;
> + u32 clock_manager;
> + u32 _pad_0x50;  /* 0x50 */
> + u32 io_manager;
> + u32 reset_manager;
> + u32 system_manager;
> + u32 osc0_timer; /* 0x60 */
> + u32 osc1_timer;
> + u32 watchdog0;
> + u32 watchdog1;
> + u32 watchdog2;  /* 0x70 */
> + u32 watchdog3;
> +};
> +
> +#define FIREWALL_L4_DISABLE_ALL  (BIT(0) | BIT(24) | BIT(16))
> +#define FIREWALL_BRIDGE_DISABLE_ALL  (~0)
> +
> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR   0xf7004688
> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR0xf7018628
> +
> +#define CCU_ADMASK_P_MASK(BIT(0))
> +#define CCU_ADMASK_NS_MASK   (BIT(1))

Drop outer parenthesis

> +
> +#endif /* _FIREWALL_S10_ */
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> new file mode 100644
> index 000..3b3833d
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -0,0 +1,205 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016-2018 Intel Corporation 
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
> + (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
> +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
> + (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
> +static struct socfpga_system_manager *sysmgr_regs =
> + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +u32 spl_boot_device(void)
> +{

[U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

2018-04-18 Thread Ley Foon Tan 
Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile|4 +
 arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +
 arch/arm/mach-socfpga/spl_s10.c   |  205 +
 3 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b669d43..35b124a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -40,6 +40,7 @@ obj-y += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += spl_gen5.o
@@ -51,6 +52,9 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y  += spl_a10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += spl_s10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
new file mode 100644
index 000..70aa9a6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation 
+ *
+ */
+
+#ifndef_FIREWALL_S10_
+#define_FIREWALL_S10_
+
+struct socfpga_firwall_l4_per {
+   u32 nand;   /* 0x00 */
+   u32 nand_data;
+   u32 _pad_0x8;
+   u32 usb0;
+   u32 usb1;   /* 0x10 */
+   u32 _pad_0x14;
+   u32 _pad_0x18;
+   u32 spim0;
+   u32 spim1;  /* 0x20 */
+   u32 spis0;
+   u32 spis1;
+   u32 emac0;
+   u32 emac1;  /* 0x30 */
+   u32 emac2;
+   u32 _pad_0x38;
+   u32 _pad_0x3c;
+   u32 sdmmc;  /* 0x40 */
+   u32 gpio0;
+   u32 gpio1;
+   u32 _pad_0x4c;
+   u32 i2c0;   /* 0x50 */
+   u32 i2c1;
+   u32 i2c2;
+   u32 i2c3;
+   u32 i2c4;   /* 0x60 */
+   u32 timer0;
+   u32 timer1;
+   u32 uart0;
+   u32 uart1;  /* 0x70 */
+};
+
+struct socfpga_firwall_l4_sys {
+   u32 _pad_0x00;  /* 0x00 */
+   u32 _pad_0x04;
+   u32 dma_ecc;
+   u32 emac0rx_ecc;
+   u32 emac0tx_ecc;/* 0x10 */
+   u32 emac1rx_ecc;
+   u32 emac1tx_ecc;
+   u32 emac2rx_ecc;
+   u32 emac2tx_ecc;/* 0x20 */
+   u32 _pad_0x24;
+   u32 _pad_0x28;
+   u32 nand_ecc;
+   u32 nand_read_ecc;  /* 0x30 */
+   u32 nand_write_ecc;
+   u32 ocram_ecc;
+   u32 _pad_0x3c;
+   u32 sdmmc_ecc;  /* 0x40 */
+   u32 usb0_ecc;
+   u32 usb1_ecc;
+   u32 clock_manager;
+   u32 _pad_0x50;  /* 0x50 */
+   u32 io_manager;
+   u32 reset_manager;
+   u32 system_manager;
+   u32 osc0_timer; /* 0x60 */
+   u32 osc1_timer;
+   u32 watchdog0;
+   u32 watchdog1;
+   u32 watchdog2;  /* 0x70 */
+   u32 watchdog3;
+};
+
+#define FIREWALL_L4_DISABLE_ALL(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_BRIDGE_DISABLE_ALL(~0)
+
+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7004688
+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR  0xf7018628
+
+#define CCU_ADMASK_P_MASK  (BIT(0))
+#define CCU_ADMASK_NS_MASK (BIT(1))
+
+#endif /* _FIREWALL_S10_ */
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
new file mode 100644
index 000..3b3833d
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
+   (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
+static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
+   (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
+static struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+   /* TODO: Get from SDM or handoff */
+   return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+   return MMCSD_MODE_FS;
+#else
+   return MMCSD_MOD