Re: [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
On Jum, 2016-12-30 at 06:14 -0600, Dinh Nguyen wrote:
>
> On 12/28/2016 12:34 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee
> >
> > This patch adding the Arria10 critical hardware initialization
> > before
> > enabling console print out in spl.
> >
> > Signed-off-by: Tien Fong Chee
> > Cc: Marek Vasut
> > Cc: Dinh Nguyen
> > Cc: Chin Liang See
> > Cc: Tien Fong
> > ---
> > Changes for V2
> > - Release UART from reset before enalbing console, and reverting
> > license
> > changes.
> > ---
> > arch/arm/mach-socfpga/spl.c | 84
> > +++--
> > 1 file changed, 82 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index fec4c7a..9e27f82 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright (C) 2012 Altera Corporation
> > + * Copyright (C) 2012-2016 Altera Corporation
> > *
> > * SPDX-License-Identifier:GPL-2.0+
> > */
> > @@ -19,22 +19,32 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> > +#include
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include
> > +#endif
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > static struct pl310_regs *const pl310 =
> > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > static struct scu_registers *scu_regs =
> > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > static struct nic301_registers *nic301_regs =
> > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > +#endif
> > +
> > +static const struct socfpga_system_manager *sysmgr_regs =
> > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > u32 spl_boot_device(void)
> > {
> > const u32 bsel = readl(&sysmgr_regs->bootinfo);
> >
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > switch (bsel & 0x7) {
> > case 0x1: /* FPGA (HPS2FPGA Bridge) */
> > return BOOT_DEVICE_RAM;
> > @@ -55,6 +65,24 @@ u32 spl_boot_device(void)
> > printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> > hang();
> > }
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > + switch ((bsel>>12) & 0x7) {
> Spaces around the '>>'.
>
> >
> > + case 0x1: /* FPGA (HPS2FPGA Bridge) */
> > + return BOOT_DEVICE_RAM;
> > + case 0x2: /* NAND Flash (1.8V) */
> > + case 0x3: /* NAND Flash (3.0V) */
> > + return BOOT_DEVICE_NAND;
> > + case 0x4: /* SD/MMC External Transceiver (1.8V) */
> > + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
> > + return BOOT_DEVICE_MMC1;
> > + case 0x6: /* QSPI Flash (1.8V) */
> > + case 0x7: /* QSPI Flash (3.0V) */
> > + return BOOT_DEVICE_SPI;
> > + default:
> > + printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> > + hang();
> > + }
> > +#endif
> > }
> You missed my comment from V1:
>
> You should just do a shift define here, so you don't have to add
> all
> this extra code here. Something like
>
> switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7)
>
Okay, noted.
>
> Dinh
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Re: [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
On 12/28/2016 12:34 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> This patch adding the Arria10 critical hardware initialization before
> enabling console print out in spl.
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> Changes for V2
> - Release UART from reset before enalbing console, and reverting license
> changes.
> ---
> arch/arm/mach-socfpga/spl.c | 84
> +++--
> 1 file changed, 82 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
> index fec4c7a..9e27f82 100644
> --- a/arch/arm/mach-socfpga/spl.c
> +++ b/arch/arm/mach-socfpga/spl.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2012 Altera Corporation
> + * Copyright (C) 2012-2016 Altera Corporation
> *
> * SPDX-License-Identifier: GPL-2.0+
> */
> @@ -19,22 +19,32 @@
> #include
> #include
> #include
> +#include
> +#include
> +#include
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include
> +#endif
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> static struct pl310_regs *const pl310 =
> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> static struct scu_registers *scu_regs =
> (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> static struct nic301_registers *nic301_regs =
> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> +#endif
> +
> +static const struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> u32 spl_boot_device(void)
> {
> const u32 bsel = readl(&sysmgr_regs->bootinfo);
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> switch (bsel & 0x7) {
> case 0x1: /* FPGA (HPS2FPGA Bridge) */
> return BOOT_DEVICE_RAM;
> @@ -55,6 +65,24 @@ u32 spl_boot_device(void)
> printf("Invalid boot device (bsel=%08x)!\n", bsel);
> hang();
> }
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> + switch ((bsel>>12) & 0x7) {
Spaces around the '>>'.
> + case 0x1: /* FPGA (HPS2FPGA Bridge) */
> + return BOOT_DEVICE_RAM;
> + case 0x2: /* NAND Flash (1.8V) */
> + case 0x3: /* NAND Flash (3.0V) */
> + return BOOT_DEVICE_NAND;
> + case 0x4: /* SD/MMC External Transceiver (1.8V) */
> + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
> + return BOOT_DEVICE_MMC1;
> + case 0x6: /* QSPI Flash (1.8V) */
> + case 0x7: /* QSPI Flash (3.0V) */
> + return BOOT_DEVICE_SPI;
> + default:
> + printf("Invalid boot device (bsel=%08x)!\n", bsel);
> + hang();
> + }
> +#endif
> }
You missed my comment from V1:
You should just do a shift define here, so you don't have to add
all
this extra code here. Something like
switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7)
Dinh
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[U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
From: Tien Fong Chee
This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
Changes for V2
- Release UART from reset before enalbing console, and reverting license
changes.
---
arch/arm/mach-socfpga/spl.c | 84 +++--
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..9e27f82 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2012-2016 Altera Corporation
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -19,22 +19,32 @@
#include
#include
#include
+#include
+#include
+#include
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include
+#endif
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
u32 spl_boot_device(void)
{
const u32 bsel = readl(&sysmgr_regs->bootinfo);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
switch (bsel & 0x7) {
case 0x1: /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
@@ -55,6 +65,24 @@ u32 spl_boot_device(void)
printf("Invalid boot device (bsel=%08x)!\n", bsel);
hang();
}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+ switch ((bsel>>12) & 0x7) {
+ case 0x1: /* FPGA (HPS2FPGA Bridge) */
+ return BOOT_DEVICE_RAM;
+ case 0x2: /* NAND Flash (1.8V) */
+ case 0x3: /* NAND Flash (3.0V) */
+ return BOOT_DEVICE_NAND;
+ case 0x4: /* SD/MMC External Transceiver (1.8V) */
+ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
+ return BOOT_DEVICE_MMC1;
+ case 0x6: /* QSPI Flash (1.8V) */
+ case 0x7: /* QSPI Flash (3.0V) */
+ return BOOT_DEVICE_SPI;
+ default:
+ printf("Invalid boot device (bsel=%08x)!\n", bsel);
+ hang();
+ }
+#endif
}
#ifdef CONFIG_SPL_MMC_SUPPORT
@@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device)
}
#endif
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static void socfpga_nic301_slave_ns(void)
{
writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -182,3 +211,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+ memset(__bss_start, 0, __bss_end - __bss_start);
+ /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+ cm_use_intosc();
+
+ watchdog_disable();
+
+ arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+ /* release osc1 watchdog timer 0 from reset */
+ reset_deassert_osc1wd0();
+
+ /* reconfigure and enable the watchdog */
+ hw_watchdog_init();
+ WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+ /* We need to access to FDT as this stage */
+ /* FDT is at end of image */
+ gd->fdt_blob = (void *)(__bss_end);
+ /* Check whether we have a valid FDT or not. */
+ if (fdtdec_prepare_fdt()) {
+ panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+ "doc/README.fdt-control");
+ }
+#endif /* CONFIG_OF_CONTROL */
+
+ /* Initialize the timer */
+ timer_init();
+
+ /* configuring the clock based on handoff */
+ cm_basic_init(gd->fdt_blob);
+ WATCHDOG_RESET();
+
+ config_dedicated_pins(gd->fdt_blob);
+ WATCHDOG_RESET();
+
+ /* Release UART from reset */
+ reset_deassert_uart();
+
+ /* enable console uart printing */
+ preloader_console_init();
+}
+#endif
--
2.2.2
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