Re: [U-Boot] [PATCH v9 37/49] rockchip: sdram: Use the rk_clr/setreg() interface

[Simon Glass]

On 21 January 2016 at 19:44, Simon Glass  wrote:
> Use this function in preference to the macro.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v9: None
> Changes in v2: None
>
>  arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)

Applied to u-boot-rockchip.
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[U-Boot] [PATCH v9 37/49] rockchip: sdram: Use the rk_clr/setreg() interface

[Simon Glass]

Use this function in preference to the macro.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 09017cc..5da04b9 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -400,7 +400,7 @@ static void set_bandwidth_ratio(const struct chan_info 
*chan, u32 channel,
 
if (n == 1) {
setbits_le32(>ppcfg, 1);
-   writel(RK_SETBITS(1 << (8 + channel)), >soc_con0);
+   rk_setreg(>soc_con0, 1 << (8 + channel));
setbits_le32(>ddrtiming, 1 << 31);
/* Data Byte disable*/
clrbits_le32(>datx8[2].dxgcr, 1);
@@ -410,7 +410,7 @@ static void set_bandwidth_ratio(const struct chan_info 
*chan, u32 channel,
setbits_le32(>datx8[3].dxdllcr, DXDLLCR_DLLDIS);
} else {
clrbits_le32(>ppcfg, 1);
-   writel(RK_CLRBITS(1 << (8 + channel)), >soc_con0);
+   rk_clrreg(>soc_con0, 1 << (8 + channel));
clrbits_le32(>ddrtiming, 1 << 31);
/* Data Byte enable*/
setbits_le32(>datx8[2].dxgcr, 1);
@@ -571,8 +571,7 @@ static void dram_all_config(const struct dram_info *dram,
dram_cfg_rbc(>chan[chan], chan, sdram_params);
}
writel(sys_reg, >pmu->sys_reg[2]);
-   writel(RK_CLRSETBITS(0x1F, sdram_params->base.stride),
-  >sgrf->soc_con2);
+   rk_clrsetreg(>sgrf->soc_con2, 0x1f, sdram_params->base.stride);
 }
 
 static int sdram_init(const struct dram_info *dram,
-- 
2.7.0.rc3.207.g0ac5344

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