RE: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform agilex5
> -Original Message-
> From: Chee, Tien Fong
> Sent: Wednesday, 28 June, 2023 5:14 PM
> To: Lim, Jit Loon ; u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Hea, Kok Kiang
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Tang, Sieu Mun
>
> Subject: RE: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new
> platform agilex5
>
> Hi Jit Loon,
>
> > -Original Message-
> > From: Lim, Jit Loon
> > Sent: Wednesday, 21 June, 2023 11:16 AM
> > To: u-boot@lists.denx.de
> > Cc: Jagan Teki ; Vignesh R
> > ; Vasut, Marek ; Simon
> > ; Chee, Tien Fong
> > ; Hea, Kok Kiang ;
> > Lokanathan, Raaj ; Maniyam, Dinesh
> > ; Ng, Boon Khai ;
> > Yuslaimi, Alif Zakuan ; Chong, Teik
> > Heng ; Zamri, Muhammad Hazim Izzat
> > ; Lim, Jit Loon
> > ; Tang, Sieu Mun
> > Subject: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new
> > platform
> > agilex5
> >
> > This is for new platform enablement for agilex5.
> > Add agilex5 dtsi and dts.
> > Update checkpatch error for stratix10.
>
> Why having checkpatch error for Stratix10?
> This should be in a separate patch.
>
> >
> > Signed-off-by: Jit Loon Lim
> > ---
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 +
> > arch/arm/dts/socfpga_agilex5.dtsi | 634 ++
> > .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131
> > arch/arm/dts/socfpga_agilex5_socdk.dts| 165 +
> > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 38 +-
> > arch/arm/dts/socfpga_soc64_u-boot.dtsi| 120
> > arch/arm/dts/socfpga_stratix10.dtsi | 0
> > .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0
> > arch/arm/dts/socfpga_stratix10_socdk.dts | 0
> > 10 files changed, 1534 insertions(+), 14 deletions(-) create mode
> > 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode
> > 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts
> > create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
> > mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi
> > mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-
> > boot.dtsi
> > mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> > 480269fa60..2e4bc556e1 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -456,6 +456,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) +=
> > thunderx-88xx.dtb
> >
> > dtb-$(CONFIG_ARCH_SOCFPGA) += \
> > socfpga_agilex_socdk.dtb\
> > + socfpga_agilex5_socdk.dtb \
> > socfpga_arria5_secu1.dtb\
> > socfpga_arria5_socdk.dtb\
> > socfpga_arria10_chameleonv3_270_2.dtb \
> > diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > new file mode 100644
> > index 00..6a1299901a
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > @@ -0,0 +1,459 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2019-2022 Intel Corporation */
> > +
> > +#include "socfpga_soc64_u-boot.dtsi"
> > +#include "socfpga_soc64_fit-u-boot.dtsi"
> > +
> > +/{
> > + memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + bootph-all;
> > + };
> > +
> > + soc {
> > + bootph-all;
> > +
> > + socfpga_secreg: socfpga-secreg {
> > + compatible = "intel,socfpga-secreg";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + bootph-all;
> > +
> > + /* DSU */
> > + i_ccu_caiu0@1c00 {
> > + reg = <0x1c00 0x1000>;
> > + intel,offset-settings =
> > + /* CAIUAMIG
RE: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform agilex5
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 21 June, 2023 11:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lokanathan, Raaj ; Maniyam, Dinesh
> ; Ng, Boon Khai ;
> Yuslaimi, Alif Zakuan ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform
> agilex5
>
> This is for new platform enablement for agilex5.
> Add agilex5 dtsi and dts.
> Update checkpatch error for stratix10.
Why having checkpatch error for Stratix10?
This should be in a separate patch.
>
> Signed-off-by: Jit Loon Lim
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 +
> arch/arm/dts/socfpga_agilex5.dtsi | 634 ++
> .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131
> arch/arm/dts/socfpga_agilex5_socdk.dts| 165 +
> arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 38 +-
> arch/arm/dts/socfpga_soc64_u-boot.dtsi| 120
> arch/arm/dts/socfpga_stratix10.dtsi | 0
> .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0
> arch/arm/dts/socfpga_stratix10_socdk.dts | 0
> 10 files changed, 1534 insertions(+), 14 deletions(-) create mode 100644
> arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644
> arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts
> create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
> mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi
> mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-
> boot.dtsi
> mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 480269fa60..2e4bc556e1 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -456,6 +456,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) +=
> thunderx-88xx.dtb
>
> dtb-$(CONFIG_ARCH_SOCFPGA) +=\
> socfpga_agilex_socdk.dtb\
> + socfpga_agilex5_socdk.dtb \
> socfpga_arria5_secu1.dtb\
> socfpga_arria5_socdk.dtb\
> socfpga_arria10_chameleonv3_270_2.dtb \
> diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> new file mode 100644
> index 00..6a1299901a
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> @@ -0,0 +1,459 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2019-2022 Intel Corporation */
> +
> +#include "socfpga_soc64_u-boot.dtsi"
> +#include "socfpga_soc64_fit-u-boot.dtsi"
> +
> +/{
> + memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + bootph-all;
> + };
> +
> + soc {
> + bootph-all;
> +
> + socfpga_secreg: socfpga-secreg {
> + compatible = "intel,socfpga-secreg";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bootph-all;
> +
> + /* DSU */
> + i_ccu_caiu0@1c00 {
> + reg = <0x1c00 0x1000>;
> + intel,offset-settings =
> + /* CAIUAMIGR */
> + <0x03c0 0x0003 0x001f>,
> + /* CAIUMIFSR */
> + <0x03c4 0x
> 0x07070777>,
> + /* DII1_MPFEREGS */
> + <0x0414 0x00018000 0x>,
> + <0x0418 0x 0x00ff>,
> + <0x0410 0xc0e00200 0xc1f03e1f>,
> + /* DII2_GICREGS */
> + <0x0424 0x0001d000 0x>,
> + <0x0428 0x 0x00ff>,
> + <0x0420 0xc0800400 0xc1f03e1f>,
> + /* NCAIU0_LWSOC2FPGA */
> + <0x0444 0x0002 0x>,
> + <0x0448 0x 0x00ff>,
> + <0x0440 0xc116 0xc1f03e1f>,
> + /* NCAIU0_SOC2FPGA_1G */
> + <0x0454 0x0004 0x>,
> + <0x0458 0x 0x00ff>,
> +
