Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
On Thu, Dec 07, 2023 at 04:22:42PM +0200, Roger Quadros wrote:
> Hi Tom,
>
> On 26/11/2023 19:35, Tom Rini wrote:
> > On Sat, Nov 25, 2023 at 01:16:05PM +0200, Roger Quadros wrote:
> >
> >> AM335x uses a special driver "am335x_spl_bch.c" as SPL
> >> NAND loader. This driver expects 1 sector at a time ECC
> >> and doesn't work well with multi-sector ECC that was implemented in
> >> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> >> correction")
> >>
> >> Switch back to 1 sector at a time read/ECC.
> >>
> >> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> >> correction")
> >> Signed-off-by: Roger Quadros
> >> ---
> >> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
> >> 1 file changed, 29 insertions(+), 66 deletions(-)
> >
> > I'm glad to see this fixed. My question is, can we abstract this
> > slightly as I assume there's a performance hit on the newer SoCs that
> > support more than one sector at a time for ECC and I assume it's just
> > am335x and related that don't support the feature. Thanks.
> >
>
> It looks like that the ELM driver (omap_elm.c) is not yet ready for
> multi-sector setup yet.
> I will need more time to test the multi-sector implementation.
Ah, thanks. Lets make that clearer in the commit message of the next
spin please.
--
Tom
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Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
On Fri, Dec 08, 2023 at 10:31:54AM +0200, Roger Quadros wrote:
> On 25/11/2023 13:16, Roger Quadros wrote:
> > AM335x uses a special driver "am335x_spl_bch.c" as SPL
> > NAND loader. This driver expects 1 sector at a time ECC
> > and doesn't work well with multi-sector ECC that was implemented in
> > commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> > correction")
> >
> > Switch back to 1 sector at a time read/ECC.
> >
> > Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> > correction")
> > Signed-off-by: Roger Quadros
>
> Azure pipeline build fails. Not because of this patch though.
> https://dev.azure.com/u-boot/u-boot/_build/results?buildId=7479=logs=c6c7c3ee-a125-5e20-d856-38cb989f4743=d274418e-7320-5c59-39b7-156cfcddae0b
Er? The failure is just above the end of the page (which the link opens
to for me) and is:
+drivers/mtd/nand/raw/omap_gpmc.c:356:12: error: 'omap_calculate_ecc_bch'
defined but not used [-Werror=unused-function]
+ 356 | static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
+ |^~
+cc1: all warnings being treated as errors
And is this patch :)
--
Tom
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Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
Hi Roger
On Sat, Nov 25, 2023 at 12:16 PM Roger Quadros wrote:
>
> AM335x uses a special driver "am335x_spl_bch.c" as SPL
> NAND loader. This driver expects 1 sector at a time ECC
> and doesn't work well with multi-sector ECC that was implemented in
> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
>
> Switch back to 1 sector at a time read/ECC.
>
> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
> Signed-off-by: Roger Quadros
> ---
> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
> 1 file changed, 29 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
> b/drivers/mtd/nand/raw/omap_gpmc.c
> index 1a5ed0de31..2d2d2c2b6d 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -293,7 +293,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> break;
> case OMAP_ECC_BCH8_CODE_HW:
> bch_type = 1;
> - nsectors = chip->ecc.steps;
> + nsectors = 1;
> if (mode == NAND_ECC_READ) {
> wr_mode = BCH_WRAPMODE_1;
> ecc_size0 = BCH8R_ECC_SIZE0;
> @@ -306,7 +306,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> break;
> case OMAP_ECC_BCH16_CODE_HW:
> bch_type = 0x2;
> - nsectors = chip->ecc.steps;
> + nsectors = 1;
> if (mode == NAND_ECC_READ) {
> wr_mode = 0x01;
> ecc_size0 = 52; /* ECC bits in nibbles per sector */
> @@ -345,17 +345,16 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> }
>
If the changes impact only one family can you just restrict it to those family?
Michael
> /**
> - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> * @mtd:MTD device structure
> * @dat:The pointer to data on which ecc is computed
> * @ecc_code: The ecc_code buffer
> - * @sector: The sector number (for a multi sector page)
> *
> * Support calculating of BCH4/8/16 ECC vectors for one sector
> * within a page. Sector number is in @sector.
> */
> -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> - u8 *ecc_code, int sector)
> +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> + u8 *ecc_code)
> {
> struct nand_chip *chip = mtd_to_nand(mtd);
> struct omap_nand_info *info = nand_get_controller_data(chip);
> @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
> const u8 *dat,
> case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> #endif
> case OMAP_ECC_BCH8_CODE_HW:
> - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
> + ptr = _cfg->bch_result_0_3[0].bch_result_x[3];
> val = readl(ptr);
> ecc_code[i++] = (val >> 0) & 0xFF;
> ptr--;
> @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct mtd_info
> *mtd, const u8 *dat,
>
> break;
> case OMAP_ECC_BCH16_CODE_HW:
> - val =
> readl(_cfg->bch_result_4_6[sector].bch_result_x[2]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[2]);
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> - val =
> readl(_cfg->bch_result_4_6[sector].bch_result_x[1]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[1]);
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> - val =
> readl(_cfg->bch_result_4_6[sector].bch_result_x[0]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[0]);
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> for (j = 3; j >= 0; j--) {
> - val =
> readl(_cfg->bch_result_0_3[sector].bch_result_x[j]
> + val =
> readl(_cfg->bch_result_0_3[0].bch_result_x[j]
> );
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> @@ -431,22 +430,6 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
> const u8 *dat,
> return 0;
> }
>
> -/**
> - * omap_calculate_ecc_bch - ECC generator for 1 sector
> - *
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
On 08/12/2023 10:41, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Fri, Dec 8, 2023 at 9:32 AM Roger Quadros wrote:
>>
>> On 25/11/2023 13:16, Roger Quadros wrote:
>>> AM335x uses a special driver "am335x_spl_bch.c" as SPL
>>> NAND loader. This driver expects 1 sector at a time ECC
>>> and doesn't work well with multi-sector ECC that was implemented in
>>> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
>>> correction")
>>>
>>> Switch back to 1 sector at a time read/ECC.
>>>
>>> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
>>> correction")
>>> Signed-off-by: Roger Quadros
>>
>> Azure pipeline build fails. Not because of this patch though.
>> https://dev.azure.com/u-boot/u-boot/_build/results?buildId=7479=logs=c6c7c3ee-a125-5e20-d856-38cb989f4743=d274418e-7320-5c59-39b7-156cfcddae0b
>>
>
> My comment below
>
>>> ---
>>> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
>>> 1 file changed, 29 insertions(+), 66 deletions(-)
>>>
>>> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
>>> b/drivers/mtd/nand/raw/omap_gpmc.c
>>> index 1a5ed0de31..2d2d2c2b6d 100644
>>> --- a/drivers/mtd/nand/raw/omap_gpmc.c
>>> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
>>> @@ -293,7 +293,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
>>> mtd_info *mtd,
>>> break;
>>> case OMAP_ECC_BCH8_CODE_HW:
>>> bch_type = 1;
>>> - nsectors = chip->ecc.steps;
>>> + nsectors = 1;
>>> if (mode == NAND_ECC_READ) {
>>> wr_mode = BCH_WRAPMODE_1;
>>> ecc_size0 = BCH8R_ECC_SIZE0;
>>> @@ -306,7 +306,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
>>> mtd_info *mtd,
>>> break;
>>> case OMAP_ECC_BCH16_CODE_HW:
>>> bch_type = 0x2;
>>> - nsectors = chip->ecc.steps;
>>> + nsectors = 1;
>>> if (mode == NAND_ECC_READ) {
>>> wr_mode = 0x01;
>>> ecc_size0 = 52; /* ECC bits in nibbles per sector */
>>> @@ -345,17 +345,16 @@ static void __maybe_unused
>>> omap_enable_hwecc_bch(struct mtd_info *mtd,
>>> }
>>>
>>> /**
>>> - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
>>> + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
>>> * @mtd:MTD device structure
>>> * @dat:The pointer to data on which ecc is computed
>>> * @ecc_code: The ecc_code buffer
>>> - * @sector: The sector number (for a multi sector page)
>>> *
>>> * Support calculating of BCH4/8/16 ECC vectors for one sector
>>> * within a page. Sector number is in @sector.
>>> */
>>> -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
>>> -u8 *ecc_code, int sector)
>>> +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
>>> + u8 *ecc_code)
>>> {
>
> This should be as before
> static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
>
>>> struct nand_chip *chip = mtd_to_nand(mtd);
>>> struct omap_nand_info *info = nand_get_controller_data(chip);
>>> @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info
>>> *mtd, const u8 *dat,
>>> case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
>>> #endif
>>> case OMAP_ECC_BCH8_CODE_HW:
>>> - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
>>> + ptr = _cfg->bch_result_0_3[0].bch_result_x[3];
>>> val = readl(ptr);
>>> ecc_code[i++] = (val >> 0) & 0xFF;
>>> ptr--;
>>> @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct mtd_info
>>> *mtd, const u8 *dat,
>>>
>>> break;
>>> case OMAP_ECC_BCH16_CODE_HW:
>>> - val =
>>> readl(_cfg->bch_result_4_6[sector].bch_result_x[2]);
>>> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[2]);
>>> ecc_code[i++] = (val >> 8) & 0xFF;
>>> ecc_code[i++] = (val >> 0) & 0xFF;
>>> - val =
>>> readl(_cfg->bch_result_4_6[sector].bch_result_x[1]);
>>> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[1]);
>>> ecc_code[i++] = (val >> 24) & 0xFF;
>>> ecc_code[i++] = (val >> 16) & 0xFF;
>>> ecc_code[i++] = (val >> 8) & 0xFF;
>>> ecc_code[i++] = (val >> 0) & 0xFF;
>>> - val =
>>> readl(_cfg->bch_result_4_6[sector].bch_result_x[0]);
>>> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[0]);
>>> ecc_code[i++] = (val >> 24) & 0xFF;
>>> ecc_code[i++] = (val >> 16) & 0xFF;
>>> ecc_code[i++] = (val >> 8) & 0xFF;
>>> ecc_code[i++] = (val >> 0) & 0xFF;
>>> for (j = 3; j >= 0; j--) {
>>> - val =
>>> readl(_cfg->bch_result_0_3[sector].bch_result_x[j]
>>> +
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
Hi
On Fri, Dec 8, 2023 at 9:32 AM Roger Quadros wrote:
>
> On 25/11/2023 13:16, Roger Quadros wrote:
> > AM335x uses a special driver "am335x_spl_bch.c" as SPL
> > NAND loader. This driver expects 1 sector at a time ECC
> > and doesn't work well with multi-sector ECC that was implemented in
> > commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> > correction")
> >
> > Switch back to 1 sector at a time read/ECC.
> >
> > Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> > correction")
> > Signed-off-by: Roger Quadros
>
> Azure pipeline build fails. Not because of this patch though.
> https://dev.azure.com/u-boot/u-boot/_build/results?buildId=7479=logs=c6c7c3ee-a125-5e20-d856-38cb989f4743=d274418e-7320-5c59-39b7-156cfcddae0b
>
My comment below
> > ---
> > drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
> > 1 file changed, 29 insertions(+), 66 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
> > b/drivers/mtd/nand/raw/omap_gpmc.c
> > index 1a5ed0de31..2d2d2c2b6d 100644
> > --- a/drivers/mtd/nand/raw/omap_gpmc.c
> > +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> > @@ -293,7 +293,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> > mtd_info *mtd,
> > break;
> > case OMAP_ECC_BCH8_CODE_HW:
> > bch_type = 1;
> > - nsectors = chip->ecc.steps;
> > + nsectors = 1;
> > if (mode == NAND_ECC_READ) {
> > wr_mode = BCH_WRAPMODE_1;
> > ecc_size0 = BCH8R_ECC_SIZE0;
> > @@ -306,7 +306,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> > mtd_info *mtd,
> > break;
> > case OMAP_ECC_BCH16_CODE_HW:
> > bch_type = 0x2;
> > - nsectors = chip->ecc.steps;
> > + nsectors = 1;
> > if (mode == NAND_ECC_READ) {
> > wr_mode = 0x01;
> > ecc_size0 = 52; /* ECC bits in nibbles per sector */
> > @@ -345,17 +345,16 @@ static void __maybe_unused
> > omap_enable_hwecc_bch(struct mtd_info *mtd,
> > }
> >
> > /**
> > - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> > + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> > * @mtd:MTD device structure
> > * @dat:The pointer to data on which ecc is computed
> > * @ecc_code: The ecc_code buffer
> > - * @sector: The sector number (for a multi sector page)
> > *
> > * Support calculating of BCH4/8/16 ECC vectors for one sector
> > * within a page. Sector number is in @sector.
> > */
> > -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> > -u8 *ecc_code, int sector)
> > +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> > + u8 *ecc_code)
> > {
This should be as before
static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
> > struct nand_chip *chip = mtd_to_nand(mtd);
> > struct omap_nand_info *info = nand_get_controller_data(chip);
> > @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info
> > *mtd, const u8 *dat,
> > case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> > #endif
> > case OMAP_ECC_BCH8_CODE_HW:
> > - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
> > + ptr = _cfg->bch_result_0_3[0].bch_result_x[3];
> > val = readl(ptr);
> > ecc_code[i++] = (val >> 0) & 0xFF;
> > ptr--;
> > @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct mtd_info
> > *mtd, const u8 *dat,
> >
> > break;
> > case OMAP_ECC_BCH16_CODE_HW:
> > - val =
> > readl(_cfg->bch_result_4_6[sector].bch_result_x[2]);
> > + val = readl(_cfg->bch_result_4_6[0].bch_result_x[2]);
> > ecc_code[i++] = (val >> 8) & 0xFF;
> > ecc_code[i++] = (val >> 0) & 0xFF;
> > - val =
> > readl(_cfg->bch_result_4_6[sector].bch_result_x[1]);
> > + val = readl(_cfg->bch_result_4_6[0].bch_result_x[1]);
> > ecc_code[i++] = (val >> 24) & 0xFF;
> > ecc_code[i++] = (val >> 16) & 0xFF;
> > ecc_code[i++] = (val >> 8) & 0xFF;
> > ecc_code[i++] = (val >> 0) & 0xFF;
> > - val =
> > readl(_cfg->bch_result_4_6[sector].bch_result_x[0]);
> > + val = readl(_cfg->bch_result_4_6[0].bch_result_x[0]);
> > ecc_code[i++] = (val >> 24) & 0xFF;
> > ecc_code[i++] = (val >> 16) & 0xFF;
> > ecc_code[i++] = (val >> 8) & 0xFF;
> > ecc_code[i++] = (val >> 0) & 0xFF;
> > for (j = 3; j >= 0; j--) {
> > - val =
> > readl(_cfg->bch_result_0_3[sector].bch_result_x[j]
> > + val =
> > readl(_cfg->bch_result_0_3[0].bch_result_x[j]
> >
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
On 25/11/2023 13:16, Roger Quadros wrote:
> AM335x uses a special driver "am335x_spl_bch.c" as SPL
> NAND loader. This driver expects 1 sector at a time ECC
> and doesn't work well with multi-sector ECC that was implemented in
> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
>
> Switch back to 1 sector at a time read/ECC.
>
> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
> Signed-off-by: Roger Quadros
Azure pipeline build fails. Not because of this patch though.
https://dev.azure.com/u-boot/u-boot/_build/results?buildId=7479=logs=c6c7c3ee-a125-5e20-d856-38cb989f4743=d274418e-7320-5c59-39b7-156cfcddae0b
> ---
> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
> 1 file changed, 29 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
> b/drivers/mtd/nand/raw/omap_gpmc.c
> index 1a5ed0de31..2d2d2c2b6d 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -293,7 +293,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> break;
> case OMAP_ECC_BCH8_CODE_HW:
> bch_type = 1;
> - nsectors = chip->ecc.steps;
> + nsectors = 1;
> if (mode == NAND_ECC_READ) {
> wr_mode = BCH_WRAPMODE_1;
> ecc_size0 = BCH8R_ECC_SIZE0;
> @@ -306,7 +306,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> break;
> case OMAP_ECC_BCH16_CODE_HW:
> bch_type = 0x2;
> - nsectors = chip->ecc.steps;
> + nsectors = 1;
> if (mode == NAND_ECC_READ) {
> wr_mode = 0x01;
> ecc_size0 = 52; /* ECC bits in nibbles per sector */
> @@ -345,17 +345,16 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> }
>
> /**
> - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> * @mtd:MTD device structure
> * @dat:The pointer to data on which ecc is computed
> * @ecc_code: The ecc_code buffer
> - * @sector: The sector number (for a multi sector page)
> *
> * Support calculating of BCH4/8/16 ECC vectors for one sector
> * within a page. Sector number is in @sector.
> */
> -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> -u8 *ecc_code, int sector)
> +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> + u8 *ecc_code)
> {
> struct nand_chip *chip = mtd_to_nand(mtd);
> struct omap_nand_info *info = nand_get_controller_data(chip);
> @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
> const u8 *dat,
> case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> #endif
> case OMAP_ECC_BCH8_CODE_HW:
> - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
> + ptr = _cfg->bch_result_0_3[0].bch_result_x[3];
> val = readl(ptr);
> ecc_code[i++] = (val >> 0) & 0xFF;
> ptr--;
> @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct mtd_info
> *mtd, const u8 *dat,
>
> break;
> case OMAP_ECC_BCH16_CODE_HW:
> - val = readl(_cfg->bch_result_4_6[sector].bch_result_x[2]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[2]);
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> - val = readl(_cfg->bch_result_4_6[sector].bch_result_x[1]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[1]);
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> - val = readl(_cfg->bch_result_4_6[sector].bch_result_x[0]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[0]);
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> for (j = 3; j >= 0; j--) {
> - val =
> readl(_cfg->bch_result_0_3[sector].bch_result_x[j]
> + val = readl(_cfg->bch_result_0_3[0].bch_result_x[j]
> );
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> @@ -431,22 +430,6 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
> const u8 *dat,
> return 0;
> }
>
> -/**
> - * omap_calculate_ecc_bch - ECC generator for 1 sector
> - * @mtd:
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
Hi Tom,
On 26/11/2023 19:35, Tom Rini wrote:
> On Sat, Nov 25, 2023 at 01:16:05PM +0200, Roger Quadros wrote:
>
>> AM335x uses a special driver "am335x_spl_bch.c" as SPL
>> NAND loader. This driver expects 1 sector at a time ECC
>> and doesn't work well with multi-sector ECC that was implemented in
>> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
>> correction")
>>
>> Switch back to 1 sector at a time read/ECC.
>>
>> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
>> correction")
>> Signed-off-by: Roger Quadros
>> ---
>> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
>> 1 file changed, 29 insertions(+), 66 deletions(-)
>
> I'm glad to see this fixed. My question is, can we abstract this
> slightly as I assume there's a performance hit on the newer SoCs that
> support more than one sector at a time for ECC and I assume it's just
> am335x and related that don't support the feature. Thanks.
>
It looks like that the ELM driver (omap_elm.c) is not yet ready for
multi-sector setup yet.
I will need more time to test the multi-sector implementation.
--
cheers,
-roger
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
On 27/11/2023 16:43, Michael Nazzareno Trimarchi wrote:
> Hi dario
>
> On Mon, Nov 27, 2023 at 3:00 PM Leto, Enrico wrote:
>>
>> Hi,
>>
>> Works on my draco thuban AM335x based boards booting from NAND with ECC BCH8
>> code.
>>
>> Tested-by: Enrico Leto
>>
>> Thanks
>>
>>
>>> -Original Message-
>>> From: Michael Nazzareno Trimarchi
>>> Sent: Saturday, November 25, 2023 2:07 PM
>>> To: Roger Quadros
>>> Cc: dario.binac...@amarulasolutions.com; Schocher, Heiko (EXT) (DENX
>>> Software Engineering GmbH) ; Leto, Enrico (SI BP R ZG FW
>>> CCP) ; tr...@konsulko.com; prane...@ti.com;
>>> n...@ti.com; vigne...@ti.com; u-boot@lists.denx.de
>>> Subject: Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
>>>
>>> Hi Roger
>>>
>>> On Sat, Nov 25, 2023 at 12:16 PM Roger Quadros
>>> wrote:
>>>>
>>>> AM335x uses a special driver "am335x_spl_bch.c" as SPL NAND loader.
>>>> This driver expects 1 sector at a time ECC and doesn't work well with
>>>> multi-sector ECC that was implemented in commit 04fcd2587321 ("mtd:
>>>> rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
>>>>
>>>> Switch back to 1 sector at a time read/ECC.
>>>>
>>>> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
>>>> correction")
>>>> Signed-off-by: Roger Quadros
>>>> ---
>>>> drivers/mtd/nand/raw/omap_gpmc.c | 95
>>>> ++--
>>>> 1 file changed, 29 insertions(+), 66 deletions(-)
>>>>
>>>> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
>>>> b/drivers/mtd/nand/raw/omap_gpmc.c
>>>> index 1a5ed0de31..2d2d2c2b6d 100644
>>>> --- a/drivers/mtd/nand/raw/omap_gpmc.c
>>>> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
>>>> @@ -293,7 +293,7 @@ static void __maybe_unused
>>> omap_enable_hwecc_bch(struct mtd_info *mtd,
>>>> break;
>>>> case OMAP_ECC_BCH8_CODE_HW:
>>>> bch_type = 1;
>>>> - nsectors = chip->ecc.steps;
>>>> + nsectors = 1;
>>>> if (mode == NAND_ECC_READ) {
>>>> wr_mode = BCH_WRAPMODE_1;
>>>> ecc_size0 = BCH8R_ECC_SIZE0; @@ -306,7 +306,7
>>>> @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info
>>> *mtd,
>>>> break;
>>>> case OMAP_ECC_BCH16_CODE_HW:
>>>> bch_type = 0x2;
>>>> - nsectors = chip->ecc.steps;
>>>> + nsectors = 1;
>>>> if (mode == NAND_ECC_READ) {
>>>> wr_mode = 0x01;
>>>> ecc_size0 = 52; /* ECC bits in nibbles per
>>>> sector */ @@ -345,17 +345,16 @@ static void __maybe_unused
>>>> omap_enable_hwecc_bch(struct mtd_info *mtd, }
>>>>
>>>> /**
>>>> - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
>>>> + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
>>>> * @mtd:MTD device structure
>>>> * @dat:The pointer to data on which ecc is computed
>>>> * @ecc_code: The ecc_code buffer
>>>> - * @sector: The sector number (for a multi sector page)
>>>> *
>>>> * Support calculating of BCH4/8/16 ECC vectors for one sector
>>>> * within a page. Sector number is in @sector.
>>>> */
>>>> -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
>>>> - u8 *ecc_code, int sector)
>>>> +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
>>>> + u8 *ecc_code)
>>>> {
>>>> struct nand_chip *chip = mtd_to_nand(mtd);
>>>> struct omap_nand_info *info = nand_get_controller_data(chip);
>>>> @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info
>>> *mtd, const u8 *dat,
>>>> case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
>>>> #endif
>>>> case OMAP_ECC_BCH8_CODE_HW:
>>>> - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
>>>> + ptr = _cfg-&
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
Hi dario
On Mon, Nov 27, 2023 at 3:00 PM Leto, Enrico wrote:
>
> Hi,
>
> Works on my draco thuban AM335x based boards booting from NAND with ECC BCH8
> code.
>
> Tested-by: Enrico Leto
>
> Thanks
>
>
> > -Original Message-
> > From: Michael Nazzareno Trimarchi
> > Sent: Saturday, November 25, 2023 2:07 PM
> > To: Roger Quadros
> > Cc: dario.binac...@amarulasolutions.com; Schocher, Heiko (EXT) (DENX
> > Software Engineering GmbH) ; Leto, Enrico (SI BP R ZG FW
> > CCP) ; tr...@konsulko.com; prane...@ti.com;
> > n...@ti.com; vigne...@ti.com; u-boot@lists.denx.de
> > Subject: Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
> >
> > Hi Roger
> >
> > On Sat, Nov 25, 2023 at 12:16 PM Roger Quadros
> > wrote:
> > >
> > > AM335x uses a special driver "am335x_spl_bch.c" as SPL NAND loader.
> > > This driver expects 1 sector at a time ECC and doesn't work well with
> > > multi-sector ECC that was implemented in commit 04fcd2587321 ("mtd:
> > > rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
> > >
> > > Switch back to 1 sector at a time read/ECC.
> > >
> > > Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> > > correction")
> > > Signed-off-by: Roger Quadros
> > > ---
> > > drivers/mtd/nand/raw/omap_gpmc.c | 95
> > > ++--
> > > 1 file changed, 29 insertions(+), 66 deletions(-)
> > >
> > > diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
> > > b/drivers/mtd/nand/raw/omap_gpmc.c
> > > index 1a5ed0de31..2d2d2c2b6d 100644
> > > --- a/drivers/mtd/nand/raw/omap_gpmc.c
> > > +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> > > @@ -293,7 +293,7 @@ static void __maybe_unused
> > omap_enable_hwecc_bch(struct mtd_info *mtd,
> > > break;
> > > case OMAP_ECC_BCH8_CODE_HW:
> > > bch_type = 1;
> > > - nsectors = chip->ecc.steps;
> > > + nsectors = 1;
> > > if (mode == NAND_ECC_READ) {
> > > wr_mode = BCH_WRAPMODE_1;
> > > ecc_size0 = BCH8R_ECC_SIZE0; @@ -306,7 +306,7
> > > @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info
> > *mtd,
> > > break;
> > > case OMAP_ECC_BCH16_CODE_HW:
> > > bch_type = 0x2;
> > > - nsectors = chip->ecc.steps;
> > > + nsectors = 1;
> > > if (mode == NAND_ECC_READ) {
> > > wr_mode = 0x01;
> > > ecc_size0 = 52; /* ECC bits in nibbles per
> > > sector */ @@ -345,17 +345,16 @@ static void __maybe_unused
> > > omap_enable_hwecc_bch(struct mtd_info *mtd, }
> > >
> > > /**
> > > - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> > > + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> > > * @mtd:MTD device structure
> > > * @dat:The pointer to data on which ecc is computed
> > > * @ecc_code: The ecc_code buffer
> > > - * @sector: The sector number (for a multi sector page)
> > > *
> > > * Support calculating of BCH4/8/16 ECC vectors for one sector
> > > * within a page. Sector number is in @sector.
> > > */
> > > -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> > > - u8 *ecc_code, int sector)
> > > +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> > > + u8 *ecc_code)
> > > {
> > > struct nand_chip *chip = mtd_to_nand(mtd);
> > > struct omap_nand_info *info = nand_get_controller_data(chip);
> > > @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info
> > *mtd, const u8 *dat,
> > > case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> > > #endif
> > > case OMAP_ECC_BCH8_CODE_HW:
> > > - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
> > > + ptr = _cfg->bch_result_0_3[0].bch_result_x[3];
> > > val = readl(ptr);
> > > ecc_code[i++] = (val >> 0) & 0xFF;
> > > ptr--;
> > > @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct
> > >
RE: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
Hi,
Works on my draco thuban AM335x based boards booting from NAND with ECC BCH8
code.
Tested-by: Enrico Leto
Thanks
> -Original Message-
> From: Michael Nazzareno Trimarchi
> Sent: Saturday, November 25, 2023 2:07 PM
> To: Roger Quadros
> Cc: dario.binac...@amarulasolutions.com; Schocher, Heiko (EXT) (DENX
> Software Engineering GmbH) ; Leto, Enrico (SI BP R ZG FW
> CCP) ; tr...@konsulko.com; prane...@ti.com;
> n...@ti.com; vigne...@ti.com; u-boot@lists.denx.de
> Subject: Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
>
> Hi Roger
>
> On Sat, Nov 25, 2023 at 12:16 PM Roger Quadros
> wrote:
> >
> > AM335x uses a special driver "am335x_spl_bch.c" as SPL NAND loader.
> > This driver expects 1 sector at a time ECC and doesn't work well with
> > multi-sector ECC that was implemented in commit 04fcd2587321 ("mtd:
> > rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
> >
> > Switch back to 1 sector at a time read/ECC.
> >
> > Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> > correction")
> > Signed-off-by: Roger Quadros
> > ---
> > drivers/mtd/nand/raw/omap_gpmc.c | 95
> > ++--
> > 1 file changed, 29 insertions(+), 66 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
> > b/drivers/mtd/nand/raw/omap_gpmc.c
> > index 1a5ed0de31..2d2d2c2b6d 100644
> > --- a/drivers/mtd/nand/raw/omap_gpmc.c
> > +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> > @@ -293,7 +293,7 @@ static void __maybe_unused
> omap_enable_hwecc_bch(struct mtd_info *mtd,
> > break;
> > case OMAP_ECC_BCH8_CODE_HW:
> > bch_type = 1;
> > - nsectors = chip->ecc.steps;
> > + nsectors = 1;
> > if (mode == NAND_ECC_READ) {
> > wr_mode = BCH_WRAPMODE_1;
> > ecc_size0 = BCH8R_ECC_SIZE0; @@ -306,7 +306,7
> > @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info
> *mtd,
> > break;
> > case OMAP_ECC_BCH16_CODE_HW:
> > bch_type = 0x2;
> > - nsectors = chip->ecc.steps;
> > + nsectors = 1;
> > if (mode == NAND_ECC_READ) {
> > wr_mode = 0x01;
> > ecc_size0 = 52; /* ECC bits in nibbles per
> > sector */ @@ -345,17 +345,16 @@ static void __maybe_unused
> > omap_enable_hwecc_bch(struct mtd_info *mtd, }
> >
> > /**
> > - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> > + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> > * @mtd:MTD device structure
> > * @dat:The pointer to data on which ecc is computed
> > * @ecc_code: The ecc_code buffer
> > - * @sector: The sector number (for a multi sector page)
> > *
> > * Support calculating of BCH4/8/16 ECC vectors for one sector
> > * within a page. Sector number is in @sector.
> > */
> > -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> > - u8 *ecc_code, int sector)
> > +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> > + u8 *ecc_code)
> > {
> > struct nand_chip *chip = mtd_to_nand(mtd);
> > struct omap_nand_info *info = nand_get_controller_data(chip);
> > @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info
> *mtd, const u8 *dat,
> > case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> > #endif
> > case OMAP_ECC_BCH8_CODE_HW:
> > - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
> > + ptr = _cfg->bch_result_0_3[0].bch_result_x[3];
> > val = readl(ptr);
> > ecc_code[i++] = (val >> 0) & 0xFF;
> > ptr--;
> > @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct
> > mtd_info *mtd, const u8 *dat,
> >
> > break;
> > case OMAP_ECC_BCH16_CODE_HW:
> > - val =
> > readl(_cfg->bch_result_4_6[sector].bch_result_x[2]);
> > + val =
> > + readl(_cfg->bch_result_4_6[0].bch_result_x[2]);
> > ecc_code[i++] = (val >> 8) & 0xFF;
> > ecc_code[i++] = (val >> 0) & 0xFF;
> > - val =
> > readl(_cfg->bch_result_4_6[sector].bch_result_x[1]);
&g
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
Hello Roger,
On 25.11.23 12:16, Roger Quadros wrote:
> AM335x uses a special driver "am335x_spl_bch.c" as SPL
> NAND loader. This driver expects 1 sector at a time ECC
> and doesn't work well with multi-sector ECC that was implemented in
> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
>
> Switch back to 1 sector at a time read/ECC.
>
> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
> Signed-off-by: Roger Quadros
> ---
> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
> 1 file changed, 29 insertions(+), 66 deletions(-)
[...]
>
> base-commit: 9e53e45292ee2f1d9d2ccc59914b161bef9b10d7
Based on this commit and with the (rebased) patchset from Enrico:
https://lists.denx.de/pipermail/u-boot/2023-November/536793.html
I can confirm, that the draco thuban board now boots again from
NAND.
Tested-by: Heiko Schocher
Thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
On Sat, Nov 25, 2023 at 01:16:05PM +0200, Roger Quadros wrote:
> AM335x uses a special driver "am335x_spl_bch.c" as SPL
> NAND loader. This driver expects 1 sector at a time ECC
> and doesn't work well with multi-sector ECC that was implemented in
> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
>
> Switch back to 1 sector at a time read/ECC.
>
> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
> Signed-off-by: Roger Quadros
> ---
> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
> 1 file changed, 29 insertions(+), 66 deletions(-)
I'm glad to see this fixed. My question is, can we abstract this
slightly as I assume there's a performance hit on the newer SoCs that
support more than one sector at a time for ECC and I assume it's just
am335x and related that don't support the feature. Thanks.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
Hi Roger
On Sat, Nov 25, 2023 at 12:16 PM Roger Quadros wrote:
>
> AM335x uses a special driver "am335x_spl_bch.c" as SPL
> NAND loader. This driver expects 1 sector at a time ECC
> and doesn't work well with multi-sector ECC that was implemented in
> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
>
> Switch back to 1 sector at a time read/ECC.
>
> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
> Signed-off-by: Roger Quadros
> ---
> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++--
> 1 file changed, 29 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c
> b/drivers/mtd/nand/raw/omap_gpmc.c
> index 1a5ed0de31..2d2d2c2b6d 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -293,7 +293,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> break;
> case OMAP_ECC_BCH8_CODE_HW:
> bch_type = 1;
> - nsectors = chip->ecc.steps;
> + nsectors = 1;
> if (mode == NAND_ECC_READ) {
> wr_mode = BCH_WRAPMODE_1;
> ecc_size0 = BCH8R_ECC_SIZE0;
> @@ -306,7 +306,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> break;
> case OMAP_ECC_BCH16_CODE_HW:
> bch_type = 0x2;
> - nsectors = chip->ecc.steps;
> + nsectors = 1;
> if (mode == NAND_ECC_READ) {
> wr_mode = 0x01;
> ecc_size0 = 52; /* ECC bits in nibbles per sector */
> @@ -345,17 +345,16 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
> mtd_info *mtd,
> }
>
> /**
> - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> * @mtd:MTD device structure
> * @dat:The pointer to data on which ecc is computed
> * @ecc_code: The ecc_code buffer
> - * @sector: The sector number (for a multi sector page)
> *
> * Support calculating of BCH4/8/16 ECC vectors for one sector
> * within a page. Sector number is in @sector.
> */
> -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> - u8 *ecc_code, int sector)
> +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> + u8 *ecc_code)
> {
> struct nand_chip *chip = mtd_to_nand(mtd);
> struct omap_nand_info *info = nand_get_controller_data(chip);
> @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
> const u8 *dat,
> case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> #endif
> case OMAP_ECC_BCH8_CODE_HW:
> - ptr = _cfg->bch_result_0_3[sector].bch_result_x[3];
> + ptr = _cfg->bch_result_0_3[0].bch_result_x[3];
> val = readl(ptr);
> ecc_code[i++] = (val >> 0) & 0xFF;
> ptr--;
> @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct mtd_info
> *mtd, const u8 *dat,
>
> break;
> case OMAP_ECC_BCH16_CODE_HW:
> - val =
> readl(_cfg->bch_result_4_6[sector].bch_result_x[2]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[2]);
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> - val =
> readl(_cfg->bch_result_4_6[sector].bch_result_x[1]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[1]);
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> - val =
> readl(_cfg->bch_result_4_6[sector].bch_result_x[0]);
> + val = readl(_cfg->bch_result_4_6[0].bch_result_x[0]);
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> ecc_code[i++] = (val >> 8) & 0xFF;
> ecc_code[i++] = (val >> 0) & 0xFF;
> for (j = 3; j >= 0; j--) {
> - val =
> readl(_cfg->bch_result_0_3[sector].bch_result_x[j]
> + val =
> readl(_cfg->bch_result_0_3[0].bch_result_x[j]
> );
> ecc_code[i++] = (val >> 24) & 0xFF;
> ecc_code[i++] = (val >> 16) & 0xFF;
> @@ -431,22 +430,6 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
> const u8 *dat,
> return 0;
> }
>
> -/**
> - * omap_calculate_ecc_bch - ECC generator for 1 sector
> - * @mtd:MTD device structure
> - * @dat: The pointer to data on which ecc is
