Re: [U-Boot] [PATCH] microblaze: usable uart16550 for big endian systems
Stephan Linz wrote:
Am Donnerstag, den 24.11.2011, 20:13 +0100 schrieb Michal Simek:
Stephan Linz wrote:
--snip--
Here is patch I have used. Please add that changes to v2 patch.
I'll do it this way. Give me a little time to change and test it.
Currently I am sill working on refactoring of the LL TEMAC driver. I
hope, the refactored driver than can merge in mainline ...
I have done it some time ago and look at [PATCH v3] net: ll_temac:
Add LL TEMAC driver to u-boot thread.
Hi Michal,
yes, I've read the whole thread.
ok.
I have attached the latest version I have and I am not going to change
it to follow new u-boot network driver style
Hm, but it is possible ...
sure, it is software almost everything is possible.
because I would like to keep ppc dcr support.
Even this was the main work I've done last week. I've split the driver
code into differnt sub modules (xilinx_ll_temac_fifo and
xilinx_ll_temac_sdram), introduce some call back functions into the sub
modules to harmonize the main driver code and divide the sdma code into
the two different bus access methodes: direct 32 bit memory access
(Microblaze) and indirect access via DCR (Xilinx PPC4xx).
Please, give me some time to finish the refactoring. I'll release all
results as fast as possible her in U-Boot list.
ok. Look forward for patches.
But, one issue was uncleare to me. Some functions, for example
xps_ll_temac_hostif_set(), were prepared to set bit 10 of CTL register.
But CTL bit 10 is not defined by any LL TEMAC documentation. Why did you
done this?
I was in origin Yoshio Kashiwagi's driver. emac parameter should be possible to
remove entirely as below.
static unsigned int xps_ll_temac_hostif_get(struct eth_device *dev,
int phy_addr, int reg_addr)
{
struct temac_reg *regs = (struct temac_reg *)dev-iobase;
out_be32(regs-lsw, (phy_addr 5) | reg_addr);
out_be32(regs-ctl, MIIMAI);
xps_ll_temac_check_status(regs, XTE_RSE_MIIM_RR_MASK);
return in_be32(regs-lsw);
}
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
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Re: [U-Boot] [PATCH] microblaze: usable uart16550 for big endian systems
Am Mittwoch, den 23.11.2011, 15:40 +0100 schrieb Michal Simek: Hi Stephan, Stephan Linz wrote: As a result of the commit 6833260 the uart16550 driver is broken for Microblaze big endian systems, because of the missing 3 byte offset. Other than as described, the U-Boot BSP does not treat properly the 3 byte offset. However, with the new 32 bit access to ns16550 registers we can enable correct register access for Microblaze big and little endian systems in the same manner. The reason why I have applied that patch is that baseaddress generation was moved to u-boot BSP out of u-boot configs. --snip-- Anyway you solution looks interesting and I will test it. However since commit 79df120 we can use direct 32 bit access to 8 bit NS16550 registers without gap generation in ns16550.h ... we need sane in_*/out_* implementation. I have look at it and tested on BE/LE. For 32bit accesses we need to implement in/out_le32 functions which we don't have right now Hi Michal, Oh yes, of course. There are no *_le32 operations, not yet. that's why please remove this macro from your patch. Our BSP generates/ed +3 offset that's why I prefer to mask it in the same patch to be sure that baseaddr is correct and compatible with old versions. Here is patch I have used. Please add that changes to v2 patch. I'll do it this way. Give me a little time to change and test it. Currently I am sill working on refactoring of the LL TEMAC driver. I hope, the refactored driver than can merge in mainline ... Thanks, Stephan diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index b740a28..8085130 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -55,10 +55,16 @@ #elif XILINX_UART16550_BASEADDR # define CONFIG_SYS_NS165501 # define CONFIG_SYS_NS16550_SERIAL + +#if defined(__MICROBLAZEEL__) # define CONFIG_SYS_NS16550_REG_SIZE -4 +#else +# define CONFIG_SYS_NS16550_REG_SIZE 4 +#endif + # define CONFIG_CONS_INDEX 1 # define CONFIG_SYS_NS16550_COM1 \ - (XILINX_UART16550_BASEADDR + 0x1000) + ((XILINX_UART16550_BASEADDR ~0xF) + 0x1000) # define CONFIG_SYS_NS16550_CLKXILINX_UART16550_CLOCK_HZ # define CONFIG_BAUDRATE 115200 -- Viele Grüße, Stephan Linz __ MB-Ref: http://www.li-pro.de/xilinx_mb:mbref:start OpenDCC: http://www.li-pro.net/opendcc.phtml PC/M: http://www.li-pro.net/pcm.phtml Sourceforge: http://sourceforge.net/users/slz Gitorious: https://gitorious.org/~slz ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] microblaze: usable uart16550 for big endian systems
Stephan Linz wrote:
Am Mittwoch, den 23.11.2011, 15:40 +0100 schrieb Michal Simek:
Hi Stephan,
Stephan Linz wrote:
As a result of the commit 6833260 the uart16550 driver
is broken for Microblaze big endian systems, because of
the missing 3 byte offset. Other than as described, the
U-Boot BSP does not treat properly the 3 byte offset.
However, with the new 32 bit access to ns16550 registers
we can enable correct register access for Microblaze big
and little endian systems in the same manner.
The reason why I have applied that patch is that baseaddress generation
was moved to u-boot BSP out of u-boot configs.
--snip--
Anyway you solution looks interesting and I will test it.
However since commit 79df120 we can use direct 32 bit access to 8 bit
NS16550 registers without gap generation in ns16550.h ... we need sane
in_*/out_* implementation.
I have look at it and tested on BE/LE. For 32bit accesses we need to implement
in/out_le32 functions which we don't have right now
Hi Michal,
Oh yes, of course. There are no *_le32 operations, not yet.
that's why please remove this macro
from your patch.
Our BSP generates/ed +3 offset that's why I prefer to mask it in the same patch
to be sure that baseaddr is correct and compatible with old versions.
Here is patch I have used. Please add that changes to v2 patch.
I'll do it this way. Give me a little time to change and test it.
Currently I am sill working on refactoring of the LL TEMAC driver. I
hope, the refactored driver than can merge in mainline ...
I have done it some time ago and look at [PATCH v3] net: ll_temac: Add LL TEMAC
driver to u-boot thread.
I have attached the latest version I have and I am not going to change it to
follow
new u-boot network driver style because I would like to keep ppc dcr support.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
/*
* Xilinx xps_ll_temac ethernet driver for u-boot
*
* Copyright (C) 2008 - 2011 Michal Simek mon...@monstr.eu
* Copyright (C) 2008 - 2011 PetaLogix
*
* Based on Yoshio Kashiwagi kashiw...@co-nss.co.jp driver
* Copyright (C) 2008 Nissin Systems Co.,Ltd.
* March 2008 created
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include config.h
#include common.h
#include net.h
#include malloc.h
#include asm/processor.h
#include asm/io.h
#include phy.h
#include miiphy.h
#undef ETH_HALTING
#if !defined(CONFIG_PHYLIB)
# error LL_TEMAC requires PHYLIB
#endif
#define XTE_EMMC_LINKSPEED_MASK 0xC000 /* Link speed */
/* XTE_EMCFG_LINKSPD_MASK */
#define XTE_EMMC_LINKSPD_10 0x /* for 10 Mbit */
#define XTE_EMMC_LINKSPD_100 0x4000 /* for 100 Mbit */
#define XTE_EMMC_LINKSPD_1000 0x8000 /* forr 1000 Mbit */
#define XTE_RSE_MIIM_RR_MASK 0x0002
#define XTE_RSE_MIIM_WR_MASK 0x0004
#define XTE_RSE_CFG_RR_MASK 0x0020
#define XTE_RSE_CFG_WR_MASK 0x0040
/* XPS_LL_TEMAC indirect registers offset definition */
#define RCW1 0x240
#define TC 0x280
#define EMMC 0x300
#define MC 0x340
#define UAW0 0x380
#define UAW1 0x384
#define AFM 0x390
#define MIIMWD 0x3b0
#define MIIMAI 0x3b4
#define CNTLREG_WRITE_ENABLE_MASK 0x8000
#define MDIO_ENABLE_MASK 0x40
#define MDIO_CLOCK_DIV_100MHz 0x28
/* XPS_LL_TEMAC SDMA registers definition */
#define TX_CURDESC_PTR 0x03
#define TX_TAILDESC_PTR 0x04
#define TX_CHNL_CTRL 0x05
#define TX_IRQ_REG 0x06
#define TX_CHNL_STS 0x07
#define RX_NXTDESC_PTR 0x08
#define RX_CURDESC_PTR 0x0b
#define RX_TAILDESC_PTR 0x0c
#define RX_CHNL_CTRL 0x0d
#define RX_IRQ_REG 0x0e
#define RX_CHNL_STS 0x0f
#define DMA_CONTROL_REG 0x10
/* DMA control bit */
#define DMA_CONTROL_RESET 0x1
/* CDMAC descriptor status bit definitions */
# define BDSTAT_STOP_ON_END_MASK 0x20
# define BDSTAT_COMPLETED_MASK 0x10
# define BDSTAT_SOP_MASK 0x08
# define BDSTAT_EOP_MASK 0x04
# define CHNL_STS_ERROR_MASK 0x80
/* All interrupt enable bits */
#define XLLDMA_CR_IRQ_ALL_EN_MASK 0x0087
/* All interrupt bits */
#define XLLDMA_IRQ_ALL_MASK 0x001F
/* Disable error when 2 or 4 bit coalesce counter overflows */
#define XLLDMA_DMACR_RX_OVERFLOW_ERR_DIS_MASK 0x0010
/* Disable error when 2 or 4 bit coalesce counter overflows */
#define XLLDMA_DMACR_TX_OVERFLOW_ERR_DIS_MASK 0x0008
/* Enable use of tail pointer register */
#define XLLDMA_DMACR_TAIL_PTR_EN_MASK 0x0004
#define LL_FIFO_ISR_RC_COMPLETE 0x0400
#define SDMA_BIT 1
#define DCR_BIT 2
#define DMAALIGN 32
/* SDMA Buffer Descriptor */
struct cdmac_bd_t {
struct cdmac_bd_t *next_p;
unsigned char *phys_buf_p;
unsigned long buf_len;
unsigned char stat;
unsigned char app1_1;
unsigned short app1_2;
unsigned long app2;
unsigned long app3;
unsigned
Re: [U-Boot] [PATCH] microblaze: usable uart16550 for big endian systems
Am Donnerstag, den 24.11.2011, 20:13 +0100 schrieb Michal Simek: Stephan Linz wrote: --snip-- Here is patch I have used. Please add that changes to v2 patch. I'll do it this way. Give me a little time to change and test it. Currently I am sill working on refactoring of the LL TEMAC driver. I hope, the refactored driver than can merge in mainline ... I have done it some time ago and look at [PATCH v3] net: ll_temac: Add LL TEMAC driver to u-boot thread. Hi Michal, yes, I've read the whole thread. I have attached the latest version I have and I am not going to change it to follow new u-boot network driver style Hm, but it is possible ... because I would like to keep ppc dcr support. Even this was the main work I've done last week. I've split the driver code into differnt sub modules (xilinx_ll_temac_fifo and xilinx_ll_temac_sdram), introduce some call back functions into the sub modules to harmonize the main driver code and divide the sdma code into the two different bus access methodes: direct 32 bit memory access (Microblaze) and indirect access via DCR (Xilinx PPC4xx). Please, give me some time to finish the refactoring. I'll release all results as fast as possible her in U-Boot list. But, one issue was uncleare to me. Some functions, for example xps_ll_temac_hostif_set(), were prepared to set bit 10 of CTL register. But CTL bit 10 is not defined by any LL TEMAC documentation. Why did you done this? Thanks, Stephan Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian -- Viele Grüße, Stephan Linz __ MB-Ref: http://www.li-pro.de/xilinx_mb:mbref:start OpenDCC: http://www.li-pro.net/opendcc.phtml PC/M: http://www.li-pro.net/pcm.phtml Sourceforge: http://sourceforge.net/users/slz Gitorious: https://gitorious.org/~slz ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] microblaze: usable uart16550 for big endian systems
Hi Stephan,
Stephan Linz wrote:
As a result of the commit 6833260 the uart16550 driver
is broken for Microblaze big endian systems, because of
the missing 3 byte offset. Other than as described, the
U-Boot BSP does not treat properly the 3 byte offset.
However, with the new 32 bit access to ns16550 registers
we can enable correct register access for Microblaze big
and little endian systems in the same manner.
The reason why I have applied that patch is that baseaddress generation
was moved to u-boot BSP out of u-boot configs.
Here is example how addresses are generated.
BE system:
#define XILINX_UART16550
#define XILINX_UART16550_BASEADDR 0x83e3
Hi Michal,
Who is generating this entry (especially incl. this offset)? Was it the
MDL environment from PetaLinux? If so, which version?
u-boot BSP.
I use my own MDL environment from TPOS, and the generator for
xparameters.h does not add this offset, see proc put_uart16550_cfg():
https://gitorious.org/mbref/mbref/blobs/master/edk-repository/ThirdParty/lib/tpos_misclib.tcl#line1384
And seriously we never need this offset. With a sane endianess handling
in software we will access the right bytes in uart16550. The Xilinx FPGA
synthesis produce results that are good enough for us. All NS16550 8 bit
registers alligned on 32 bit memory access: 0x00rr on BE and
0xrr00 in LE.
The BSP generator (Xilinx MDL part) may never knows specifics about
software or unclean code. Moreover we have to change the code ;-)
Till now we have set CONFIG_SYS_NS16550_REG_SIZE to -4 and a offset of 3
to the NS16550 base address for Microblaze BE systems. As I can see in
ns16550.h that was completely wrong, or not? See:
#if !defined(CONFIG_SYS_NS16550_REG_SIZE)
#error Please define NS16550 registers size.
#elif (CONFIG_SYS_NS16550_REG_SIZE 0)
#define UART_REG(x) \
unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1];\
unsigned char x;
#elif (CONFIG_SYS_NS16550_REG_SIZE 0)
#define UART_REG(x) \
unsigned char x;\
unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
#endif
struct NS16550 {
UART_REG(rbr); /* 0 */
UART_REG(ier); /* 1 */
... and so on. For BE systems we should use CONFIG_SYS_NS16550_REG_SIZE
set to 4 -- have a 3 byte gap on NS16550 base address and then point to
the right byte on offset 3, or not? On LE systems we need to set -4 for
*_REG_SIZE -- have a 3 byte gap after and betweeen each 8 bit
registers.
Anyway you solution looks interesting and I will test it.
However since commit 79df120 we can use direct 32 bit access to 8 bit
NS16550 registers without gap generation in ns16550.h ... we need sane
in_*/out_* implementation.
I have look at it and tested on BE/LE. For 32bit accesses we need to implement
in/out_le32 functions which we don't have right now that's why please remove
this macro
from your patch.
Our BSP generates/ed +3 offset that's why I prefer to mask it in the same patch
to be sure that baseaddr is correct and compatible with old versions.
Here is patch I have used. Please add that changes to v2 patch.
Thanks,
Michal
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index b740a28..8085130 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -55,10 +55,16 @@
#elif XILINX_UART16550_BASEADDR
# define CONFIG_SYS_NS165501
# define CONFIG_SYS_NS16550_SERIAL
+
+#if defined(__MICROBLAZEEL__)
# define CONFIG_SYS_NS16550_REG_SIZE -4
+#else
+# define CONFIG_SYS_NS16550_REG_SIZE 4
+#endif
+
# define CONFIG_CONS_INDEX 1
# define CONFIG_SYS_NS16550_COM1 \
- (XILINX_UART16550_BASEADDR + 0x1000)
+ ((XILINX_UART16550_BASEADDR ~0xF) + 0x1000)
# define CONFIG_SYS_NS16550_CLKXILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE 115200
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
___
U-Boot mailing list
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Re: [U-Boot] [PATCH] microblaze: usable uart16550 for big endian systems
Am Montag, den 21.11.2011, 08:21 +0100 schrieb Michal Simek:
Hi Stephan,
Stephan Linz wrote:
As a result of the commit 6833260 the uart16550 driver
is broken for Microblaze big endian systems, because of
the missing 3 byte offset. Other than as described, the
U-Boot BSP does not treat properly the 3 byte offset.
However, with the new 32 bit access to ns16550 registers
we can enable correct register access for Microblaze big
and little endian systems in the same manner.
The reason why I have applied that patch is that baseaddress generation
was moved to u-boot BSP out of u-boot configs.
Here is example how addresses are generated.
BE system:
#define XILINX_UART16550
#define XILINX_UART16550_BASEADDR 0x83e3
Hi Michal,
Who is generating this entry (especially incl. this offset)? Was it the
MDL environment from PetaLinux? If so, which version?
I use my own MDL environment from TPOS, and the generator for
xparameters.h does not add this offset, see proc put_uart16550_cfg():
https://gitorious.org/mbref/mbref/blobs/master/edk-repository/ThirdParty/lib/tpos_misclib.tcl#line1384
And seriously we never need this offset. With a sane endianess handling
in software we will access the right bytes in uart16550. The Xilinx FPGA
synthesis produce results that are good enough for us. All NS16550 8 bit
registers alligned on 32 bit memory access: 0x00rr on BE and
0xrr00 in LE.
The BSP generator (Xilinx MDL part) may never knows specifics about
software or unclean code. Moreover we have to change the code ;-)
Till now we have set CONFIG_SYS_NS16550_REG_SIZE to -4 and a offset of 3
to the NS16550 base address for Microblaze BE systems. As I can see in
ns16550.h that was completely wrong, or not? See:
#if !defined(CONFIG_SYS_NS16550_REG_SIZE)
#error Please define NS16550 registers size.
#elif (CONFIG_SYS_NS16550_REG_SIZE 0)
#define UART_REG(x) \
unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1];\
unsigned char x;
#elif (CONFIG_SYS_NS16550_REG_SIZE 0)
#define UART_REG(x) \
unsigned char x;\
unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
#endif
struct NS16550 {
UART_REG(rbr); /* 0 */
UART_REG(ier); /* 1 */
... and so on. For BE systems we should use CONFIG_SYS_NS16550_REG_SIZE
set to 4 -- have a 3 byte gap on NS16550 base address and then point to
the right byte on offset 3, or not? On LE systems we need to set -4 for
*_REG_SIZE -- have a 3 byte gap after and betweeen each 8 bit
registers.
Anyway you solution looks interesting and I will test it.
However since commit 79df120 we can use direct 32 bit access to 8 bit
NS16550 registers without gap generation in ns16550.h ... we need sane
in_*/out_* implementation.
--
Best regards,
Stephan Linz
__
MB-Ref: http://www.li-pro.de/xilinx_mb:mbref:start
OpenDCC: http://www.li-pro.net/opendcc.phtml
PC/M: http://www.li-pro.net/pcm.phtml
Sourceforge: http://sourceforge.net/users/slz
Gitorious: https://gitorious.org/~slz
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Re: [U-Boot] [PATCH] microblaze: usable uart16550 for big endian systems
Hi Stephan, Stephan Linz wrote: As a result of the commit 6833260 the uart16550 driver is broken for Microblaze big endian systems, because of the missing 3 byte offset. Other than as described, the U-Boot BSP does not treat properly the 3 byte offset. However, with the new 32 bit access to ns16550 registers we can enable correct register access for Microblaze big and little endian systems in the same manner. The reason why I have applied that patch is that baseaddress generation was moved to u-boot BSP out of u-boot configs. Here is example how addresses are generated. BE system: #define XILINX_UART16550 #define XILINX_UART16550_BASEADDR 0x83e3 LE system: #define XILINX_UART16550 #define XILINX_UART16550_BASEADDR 0x83e0 Then you can use origin config file and change is only in xparameters.h in board folder. Anyway you solution looks interesting and I will test it. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
