On Thu, Jul 11, 2019 at 12:13 PM Bin Meng wrote:
>
> This syncs csr.h with Linux kernel 5.2, and imports asm.h that
> is required by csr.h.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/include/asm/asm.h | 68
>
> arch/riscv/include/asm/csr.h | 62 +---
> 2 files changed, 114 insertions(+), 16 deletions(-)
> create mode 100644 arch/riscv/include/asm/asm.h
>
> diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> new file mode 100644
> index 000..5a02b7d
> --- /dev/null
> +++ b/arch/riscv/include/asm/asm.h
> @@ -0,0 +1,68 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2015 Regents of the University of California
> + */
> +
> +#ifndef _ASM_RISCV_ASM_H
> +#define _ASM_RISCV_ASM_H
> +
> +#ifdef __ASSEMBLY__
> +#define __ASM_STR(x) x
> +#else
> +#define __ASM_STR(x) #x
> +#endif
> +
> +#if __riscv_xlen == 64
> +#define __REG_SEL(a, b)__ASM_STR(a)
> +#elif __riscv_xlen == 32
> +#define __REG_SEL(a, b)__ASM_STR(b)
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +
> +#define REG_L __REG_SEL(ld, lw)
> +#define REG_S __REG_SEL(sd, sw)
> +#define SZREG __REG_SEL(8, 4)
> +#define LGREG __REG_SEL(3, 2)
> +
> +#if __SIZEOF_POINTER__ == 8
> +#ifdef __ASSEMBLY__
> +#define RISCV_PTR .dword
> +#define RISCV_SZPTR8
> +#define RISCV_LGPTR3
> +#else
> +#define RISCV_PTR ".dword"
> +#define RISCV_SZPTR"8"
> +#define RISCV_LGPTR"3"
> +#endif
> +#elif __SIZEOF_POINTER__ == 4
> +#ifdef __ASSEMBLY__
> +#define RISCV_PTR .word
> +#define RISCV_SZPTR4
> +#define RISCV_LGPTR2
> +#else
> +#define RISCV_PTR ".word"
> +#define RISCV_SZPTR"4"
> +#define RISCV_LGPTR"2"
> +#endif
> +#else
> +#error "Unexpected __SIZEOF_POINTER__"
> +#endif
> +
> +#if (__SIZEOF_INT__ == 4)
> +#define RISCV_INT __ASM_STR(.word)
> +#define RISCV_SZINT__ASM_STR(4)
> +#define RISCV_LGINT__ASM_STR(2)
> +#else
> +#error "Unexpected __SIZEOF_INT__"
> +#endif
> +
> +#if (__SIZEOF_SHORT__ == 2)
> +#define RISCV_SHORT__ASM_STR(.half)
> +#define RISCV_SZSHORT __ASM_STR(2)
> +#define RISCV_LGSHORT __ASM_STR(1)
> +#else
> +#error "Unexpected __SIZEOF_SHORT__"
> +#endif
> +
> +#endif /* _ASM_RISCV_ASM_H */
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 644e6ba..1a6bcfc 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> +/* SPDX-License-Identifier: GPL-2.0-only */
> /*
> * Copyright (C) 2015 Regents of the University of California
> *
> @@ -8,13 +8,14 @@
> #ifndef _ASM_RISCV_CSR_H
> #define _ASM_RISCV_CSR_H
>
> +#include
> #include
>
> /* Status register flags */
> #define SR_SIE _AC(0x0002, UL) /* Supervisor Interrupt Enable */
> #define SR_SPIE_AC(0x0020, UL) /* Previous Supervisor IE
> */
> #define SR_SPP _AC(0x0100, UL) /* Previously Supervisor */
> -#define SR_SUM _AC(0x0004, UL) /* Supervisor access User Memory
> */
> +#define SR_SUM _AC(0x0004, UL) /* Supervisor User Memory Access
> */
>
> #define SR_FS _AC(0x6000, UL) /* Floating-point Status */
> #define SR_FS_OFF _AC(0x, UL)
> @@ -35,7 +36,7 @@
> #endif
>
> /* SATP flags */
> -#if __riscv_xlen == 32
> +#ifndef CONFIG_64BIT
> #define SATP_PPN _AC(0x003F, UL)
> #define SATP_MODE_32 _AC(0x8000, UL)
> #define SATP_MODE SATP_MODE_32
> @@ -45,10 +46,18 @@
> #define SATP_MODE SATP_MODE_39
> #endif
>
> -/* Interrupt Enable and Interrupt Pending flags */
> -#define MIE_MSIE _AC(0x0008, UL) /* Software Interrupt Enable */
> -#define SIE_SSIE _AC(0x0002, UL) /* Software Interrupt Enable */
> -#define SIE_STIE _AC(0x0020, UL) /* Timer Interrupt Enable */
> +/* SCAUSE */
> +#define SCAUSE_IRQ_FLAG(_AC(1, UL) << (__riscv_xlen - 1))
> +
> +#define IRQ_U_SOFT 0
> +#define IRQ_S_SOFT 1
> +#define IRQ_M_SOFT 3
> +#define IRQ_U_TIMER4
> +#define IRQ_S_TIMER5
> +#define IRQ_M_TIMER7
> +#define IRQ_U_EXT 8
> +#define IRQ_S_EXT 9
> +#define IRQ_M_EXT 11
>
> #define EXC_INST_MISALIGNED0
> #define EXC_INST_ACCESS1
> @@ -60,14 +69,35 @@
> #define EXC_LOAD_PAGE_FAULT13
> #define EXC_STORE_PAGE_FAULT 15
>
> -#ifndef __ASSEMBLY__
> +/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
> +#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
> +#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
> +#define SIE_STIE (_AC(0x1, UL) << IRQ_
