Re: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V
I think, the boot flow explained above is supported the sifive fu540 board default boot mode. if we want to select debug mode, then, does this patches work with the u-boot to TFTP booting(dhcp, bootp) in debug mode? Regards Padmarao On Fri, Mar 22, 2019 at 4:47 AM Atish Patra wrote: > On 3/21/19 4:06 PM, Bin Meng wrote: > > On Thu, Mar 21, 2019 at 11:39 PM Troy Benjegerdes > wrote: > >> > >> On Sun, Mar 17, 2019 at 07:28:31PM +0100, Lukas Auer wrote: > >>> This patch series adds SMP support for RISC-V to U-Boot. It allows > >>> U-Boot to run on multi-hart systems (hart is the RISC-V terminology for > >>> hardware thread). Images passed to bootm will be started on all harts. > >>> The bootm command is currently the only one that will boot images on > all > >>> harts, bootefi is not yet supported. > >>> > >>> The patches have been successfully tested on both QEMU (machine and > >>> supervisor mode) and the HiFive Unleashed board (supervisor mode), > using > >>> BBL and OpenSBI. > >> > >> Can you describe the test configuration and boot flow a little more, or > post an > >> SDcard image that boots with the switches as shown in the readme at [1] > >> > >> I don't see any board-specific memory initialization code anywhere, so > I assume > >> you are still using the original SiFive FSBL, and not the u-boot > version that > >> includes the memory init code [2] > >> > > > > Correct. Mainline U-Boot on the FU540 board runs on S-mode currently. > > You can refer to documentation doc/README.sifive-fu540 > > > > To add Bin's comment, the boot flow described in README.sifive-fu540 is > > ZSBL->FSBL->OpenSBI/BBL->U-Boot(S Mode)->Linux > > FYI: For BBL, you need to hack U-Boot to add serial console in DT. > > IMHO, we should avoid forks and use upstream code as much as possible. > > The memory initialization patches in [2] were never upstreamed. It would > be great if that can upstream them so that we can replace FSBL as well. > U-Boot SPL support for RISC-V would even be better. > > Regards, > Atish > >> [1] https://github.com/sifive/freedom-u-sdk > >> [2] https://github.com/sifive/HiFive_U-Boot > >> > > > > Regards, > > Bin > > ___ > > U-Boot mailing list > > U-Boot@lists.denx.de > > https://lists.denx.de/listinfo/u-boot > > > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V
On 3/21/19 4:06 PM, Bin Meng wrote: On Thu, Mar 21, 2019 at 11:39 PM Troy Benjegerdes wrote: On Sun, Mar 17, 2019 at 07:28:31PM +0100, Lukas Auer wrote: This patch series adds SMP support for RISC-V to U-Boot. It allows U-Boot to run on multi-hart systems (hart is the RISC-V terminology for hardware thread). Images passed to bootm will be started on all harts. The bootm command is currently the only one that will boot images on all harts, bootefi is not yet supported. The patches have been successfully tested on both QEMU (machine and supervisor mode) and the HiFive Unleashed board (supervisor mode), using BBL and OpenSBI. Can you describe the test configuration and boot flow a little more, or post an SDcard image that boots with the switches as shown in the readme at [1] I don't see any board-specific memory initialization code anywhere, so I assume you are still using the original SiFive FSBL, and not the u-boot version that includes the memory init code [2] Correct. Mainline U-Boot on the FU540 board runs on S-mode currently. You can refer to documentation doc/README.sifive-fu540 To add Bin's comment, the boot flow described in README.sifive-fu540 is ZSBL->FSBL->OpenSBI/BBL->U-Boot(S Mode)->Linux FYI: For BBL, you need to hack U-Boot to add serial console in DT. IMHO, we should avoid forks and use upstream code as much as possible. The memory initialization patches in [2] were never upstreamed. It would be great if that can upstream them so that we can replace FSBL as well. U-Boot SPL support for RISC-V would even be better. Regards, Atish [1] https://github.com/sifive/freedom-u-sdk [2] https://github.com/sifive/HiFive_U-Boot Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V
On Thu, Mar 21, 2019 at 11:39 PM Troy Benjegerdes wrote: > > On Sun, Mar 17, 2019 at 07:28:31PM +0100, Lukas Auer wrote: > > This patch series adds SMP support for RISC-V to U-Boot. It allows > > U-Boot to run on multi-hart systems (hart is the RISC-V terminology for > > hardware thread). Images passed to bootm will be started on all harts. > > The bootm command is currently the only one that will boot images on all > > harts, bootefi is not yet supported. > > > > The patches have been successfully tested on both QEMU (machine and > > supervisor mode) and the HiFive Unleashed board (supervisor mode), using > > BBL and OpenSBI. > > Can you describe the test configuration and boot flow a little more, or post > an > SDcard image that boots with the switches as shown in the readme at [1] > > I don't see any board-specific memory initialization code anywhere, so I > assume > you are still using the original SiFive FSBL, and not the u-boot version that > includes the memory init code [2] > Correct. Mainline U-Boot on the FU540 board runs on S-mode currently. You can refer to documentation doc/README.sifive-fu540 > [1] https://github.com/sifive/freedom-u-sdk > [2] https://github.com/sifive/HiFive_U-Boot > Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V
On Sun, Mar 17, 2019 at 07:28:31PM +0100, Lukas Auer wrote: > This patch series adds SMP support for RISC-V to U-Boot. It allows > U-Boot to run on multi-hart systems (hart is the RISC-V terminology for > hardware thread). Images passed to bootm will be started on all harts. > The bootm command is currently the only one that will boot images on all > harts, bootefi is not yet supported. > > The patches have been successfully tested on both QEMU (machine and > supervisor mode) and the HiFive Unleashed board (supervisor mode), using > BBL and OpenSBI. Can you describe the test configuration and boot flow a little more, or post an SDcard image that boots with the switches as shown in the readme at [1] I don't see any board-specific memory initialization code anywhere, so I assume you are still using the original SiFive FSBL, and not the u-boot version that includes the memory init code [2] [1] https://github.com/sifive/freedom-u-sdk [2] https://github.com/sifive/HiFive_U-Boot > Mainline QEMU requires two patches [1, 2] to run in this configuration. > Patch [1] has been dropped and will be replaced with a U-Boot patch. > > [1]: https://patchwork.ozlabs.org/patch/1039493/ > [2]: https://patchwork.ozlabs.org/patch/1039082/ > > Changes in v3: > - Print error if riscv_send_ipi() fails > - Adjust error message for failures of riscv_clear_ipi() to match error > message for failures of riscv_send_ipi() > - New patch to save the hart ID in register tp instead of s0 > - Adjust patch to use the new location of the hart ID (register tp) > - New patch to hang if relocation of secondary harts fails > > Changes in v2: > - Remove unneeded quotes from NR_CPUS Kconfig entry > - Move memory barrier from send_ipi_many() to handle_ipi() > - Add check in send_ipi_many so that IPIs are only sent to available > harts as indicated by the available_harts mask > - Implement hart lottery to pick main hart to run U-Boot > - Remove CONFIG_MAIN_HART as it is not required anymore > - Register available harts in the available_harts mask > - New patch to populate register a0 with the hart ID from the mhartid > CSR in machine-mode > - New patch to enable SMP on the SiFive FU540, which was previously sent > independently > > Lukas Auer (11): > riscv: add infrastructure for calling functions on other harts > riscv: import the supervisor binary interface header file > riscv: implement IPI platform functions using SBI > riscv: delay initialization of caches and debug UART > riscv: save hart ID in register tp instead of s0 > riscv: add support for multi-hart systems > riscv: boot images passed to bootm on all harts > riscv: do not rely on hart ID passed by previous boot stage > riscv: hang if relocation of secondary harts fails > riscv: fu540: enable SMP > riscv: qemu: enable SMP > > arch/riscv/Kconfig | 28 + > arch/riscv/cpu/cpu.c | 9 +- > arch/riscv/cpu/start.S | 167 +-- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/include/asm/global_data.h | 6 + > arch/riscv/include/asm/sbi.h | 94 +++ > arch/riscv/include/asm/smp.h | 53 + > arch/riscv/lib/Makefile | 2 + > arch/riscv/lib/asm-offsets.c | 1 + > arch/riscv/lib/bootm.c | 13 ++- > arch/riscv/lib/sbi_ipi.c | 25 > arch/riscv/lib/smp.c | 118 +++ > board/emulation/qemu-riscv/Kconfig | 1 + > board/sifive/fu540/Kconfig | 1 + > 14 files changed, 507 insertions(+), 12 deletions(-) > create mode 100644 arch/riscv/include/asm/sbi.h > create mode 100644 arch/riscv/include/asm/smp.h > create mode 100644 arch/riscv/lib/sbi_ipi.c > create mode 100644 arch/riscv/lib/smp.c > > -- > 2.20.1 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V
On Wed, 2019-03-20 at 05:37 -0700, Palmer Dabbelt wrote: > On Sun, 17 Mar 2019 11:28:31 PDT (-0700), > lukas.a...@aisec.fraunhofer.de wrote: > > This patch series adds SMP support for RISC-V to U-Boot. It allows > > U-Boot to run on multi-hart systems (hart is the RISC-V terminology > > for > > hardware thread). Images passed to bootm will be started on all > > harts. > > The bootm command is currently the only one that will boot images > > on all > > harts, bootefi is not yet supported. > > > > The patches have been successfully tested on both QEMU (machine and > > supervisor mode) and the HiFive Unleashed board (supervisor mode), > > using > > BBL and OpenSBI. > > Mainline QEMU requires two patches [1, 2] to run in this > > configuration. > > Patch [1] has been dropped and will be replaced with a U-Boot > > patch. > > > > [1]: https://patchwork.ozlabs.org/patch/1039493/ > > As far as I understand it we're taking a different approach here, so > this patch > won't be going in. > > > [2]: https://patchwork.ozlabs.org/patch/1039082/ > > This should be in rc0, LMK if I screwed something up. > > Thanks for the patches, and also for testing on the board :) > Everything looks good, thanks for merging the patch! U-Boot with the SMP patches now runs in supervisor mode on mainline QEMU. I will send a U-Boot patch later this week to get it running in machine mode on mainline QEMU as well. Thanks, Lukas > > Changes in v3: > > - Print error if riscv_send_ipi() fails > > - Adjust error message for failures of riscv_clear_ipi() to match > > error > > message for failures of riscv_send_ipi() > > - New patch to save the hart ID in register tp instead of s0 > > - Adjust patch to use the new location of the hart ID (register tp) > > - New patch to hang if relocation of secondary harts fails > > > > Changes in v2: > > - Remove unneeded quotes from NR_CPUS Kconfig entry > > - Move memory barrier from send_ipi_many() to handle_ipi() > > - Add check in send_ipi_many so that IPIs are only sent to > > available > > harts as indicated by the available_harts mask > > - Implement hart lottery to pick main hart to run U-Boot > > - Remove CONFIG_MAIN_HART as it is not required anymore > > - Register available harts in the available_harts mask > > - New patch to populate register a0 with the hart ID from the > > mhartid > > CSR in machine-mode > > - New patch to enable SMP on the SiFive FU540, which was previously > > sent > > independently > > > > Lukas Auer (11): > > riscv: add infrastructure for calling functions on other harts > > riscv: import the supervisor binary interface header file > > riscv: implement IPI platform functions using SBI > > riscv: delay initialization of caches and debug UART > > riscv: save hart ID in register tp instead of s0 > > riscv: add support for multi-hart systems > > riscv: boot images passed to bootm on all harts > > riscv: do not rely on hart ID passed by previous boot stage > > riscv: hang if relocation of secondary harts fails > > riscv: fu540: enable SMP > > riscv: qemu: enable SMP > > > > arch/riscv/Kconfig | 28 + > > arch/riscv/cpu/cpu.c | 9 +- > > arch/riscv/cpu/start.S | 167 > > +-- > > arch/riscv/include/asm/csr.h | 1 + > > arch/riscv/include/asm/global_data.h | 6 + > > arch/riscv/include/asm/sbi.h | 94 +++ > > arch/riscv/include/asm/smp.h | 53 + > > arch/riscv/lib/Makefile | 2 + > > arch/riscv/lib/asm-offsets.c | 1 + > > arch/riscv/lib/bootm.c | 13 ++- > > arch/riscv/lib/sbi_ipi.c | 25 > > arch/riscv/lib/smp.c | 118 +++ > > board/emulation/qemu-riscv/Kconfig | 1 + > > board/sifive/fu540/Kconfig | 1 + > > 14 files changed, 507 insertions(+), 12 deletions(-) > > create mode 100644 arch/riscv/include/asm/sbi.h > > create mode 100644 arch/riscv/include/asm/smp.h > > create mode 100644 arch/riscv/lib/sbi_ipi.c > > create mode 100644 arch/riscv/lib/smp.c ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V
On Sun, 17 Mar 2019 11:28:31 PDT (-0700), lukas.a...@aisec.fraunhofer.de wrote: This patch series adds SMP support for RISC-V to U-Boot. It allows U-Boot to run on multi-hart systems (hart is the RISC-V terminology for hardware thread). Images passed to bootm will be started on all harts. The bootm command is currently the only one that will boot images on all harts, bootefi is not yet supported. The patches have been successfully tested on both QEMU (machine and supervisor mode) and the HiFive Unleashed board (supervisor mode), using BBL and OpenSBI. Mainline QEMU requires two patches [1, 2] to run in this configuration. Patch [1] has been dropped and will be replaced with a U-Boot patch. [1]: https://patchwork.ozlabs.org/patch/1039493/ As far as I understand it we're taking a different approach here, so this patch won't be going in. [2]: https://patchwork.ozlabs.org/patch/1039082/ This should be in rc0, LMK if I screwed something up. Thanks for the patches, and also for testing on the board :) Changes in v3: - Print error if riscv_send_ipi() fails - Adjust error message for failures of riscv_clear_ipi() to match error message for failures of riscv_send_ipi() - New patch to save the hart ID in register tp instead of s0 - Adjust patch to use the new location of the hart ID (register tp) - New patch to hang if relocation of secondary harts fails Changes in v2: - Remove unneeded quotes from NR_CPUS Kconfig entry - Move memory barrier from send_ipi_many() to handle_ipi() - Add check in send_ipi_many so that IPIs are only sent to available harts as indicated by the available_harts mask - Implement hart lottery to pick main hart to run U-Boot - Remove CONFIG_MAIN_HART as it is not required anymore - Register available harts in the available_harts mask - New patch to populate register a0 with the hart ID from the mhartid CSR in machine-mode - New patch to enable SMP on the SiFive FU540, which was previously sent independently Lukas Auer (11): riscv: add infrastructure for calling functions on other harts riscv: import the supervisor binary interface header file riscv: implement IPI platform functions using SBI riscv: delay initialization of caches and debug UART riscv: save hart ID in register tp instead of s0 riscv: add support for multi-hart systems riscv: boot images passed to bootm on all harts riscv: do not rely on hart ID passed by previous boot stage riscv: hang if relocation of secondary harts fails riscv: fu540: enable SMP riscv: qemu: enable SMP arch/riscv/Kconfig | 28 + arch/riscv/cpu/cpu.c | 9 +- arch/riscv/cpu/start.S | 167 +-- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/global_data.h | 6 + arch/riscv/include/asm/sbi.h | 94 +++ arch/riscv/include/asm/smp.h | 53 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c | 13 ++- arch/riscv/lib/sbi_ipi.c | 25 arch/riscv/lib/smp.c | 118 +++ board/emulation/qemu-riscv/Kconfig | 1 + board/sifive/fu540/Kconfig | 1 + 14 files changed, 507 insertions(+), 12 deletions(-) create mode 100644 arch/riscv/include/asm/sbi.h create mode 100644 arch/riscv/include/asm/smp.h create mode 100644 arch/riscv/lib/sbi_ipi.c create mode 100644 arch/riscv/lib/smp.c ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
