[uClinux-dev] [PATCH m68knommu] Add the m54xx fec driver

2012-09-24 Thread Philippe De Muyter 
Hello,

I have cleaned up and updated to 3.6-rc5 my previous port of the
freescale-written driver for the fast Ethernet Controller of the M547x
and M548x ColdFires.  It seems from comments found in Freescale sources
that this uses a MultiChannel DMA controller marketed as MCD and available
also in the NPC8220 also from Freescale.  Therefore, I have split the
submission in three parts :
A generic MCD dma driver
The M54xx instantiation of the MCD driver
The FEC driver for M54xx

I know there are still lines above 80 characters, but I feel they must be
left that way.  There are also parts of an unfinished netpoll interface.

Feel free to test and comment.

Philippe

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[uClinux-dev] [PATCH 2/3] m68knommu: Add the m54xx-specific bits for the MultiChannel DMA driver

2012-09-24 Thread Philippe De Muyter 
This driver is not (yet) dmaengine enabled, but is needed by the
ethernet fec driver for the ColdFire M54xx processors.
Original work was made by Kurt Mahan at Freescale.

Signed-off-by: Philippe De Muyter p...@macqel.be
---
 arch/m68k/include/asm/m54xxdma.h |   67 +
 arch/m68k/include/asm/m54xxdma_api.h |   62 
 arch/m68k/include/asm/m54xxsim.h |1 +
 arch/m68k/include/asm/m54xxsram.h|   11 +
 drivers/dma/Kconfig  |   10 +
 drivers/dma/fsl_mcd_dma/Makefile |1 +
 drivers/dma/fsl_mcd_dma/m54xx_dma.c  |  519 ++
 7 files changed, 671 insertions(+), 0 deletions(-)
 create mode 100644 arch/m68k/include/asm/m54xxdma.h
 create mode 100644 arch/m68k/include/asm/m54xxdma_api.h
 create mode 100644 arch/m68k/include/asm/m54xxsram.h
 create mode 100644 drivers/dma/fsl_mcd_dma/m54xx_dma.c

diff --git a/arch/m68k/include/asm/m54xxdma.h b/arch/m68k/include/asm/m54xxdma.h
new file mode 100644
index 000..cc57872
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxdma.h
@@ -0,0 +1,67 @@
+/*
+ * ColdFire 547x/548x DMA controller support.
+ */
+#ifndef __MCF548X_DMA_H__
+#define __MCF548X_DMA_H__
+
+
+/* Register read/write macros */
+#define MCF_DMA_DIPR(MCF_MBAR+0x008014)
+#define MCF_DMA_DIMR(MCF_MBAR+0x008018)
+#define MCF_DMA_IMCR(MCF_MBAR+0x00805C)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x) (1  (x))
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x) (1  (x))
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_SRC16(x)(((x)0x0003)0)
+#define MCF_DMA_IMCR_SRC17(x)(((x)0x0003)2)
+#define MCF_DMA_IMCR_SRC18(x)(((x)0x0003)4)
+#define MCF_DMA_IMCR_SRC19(x)(((x)0x0003)6)
+#define MCF_DMA_IMCR_SRC20(x)(((x)0x0003)8)
+#define MCF_DMA_IMCR_SRC21(x)(((x)0x0003)10)
+#define MCF_DMA_IMCR_SRC22(x)(((x)0x0003)12)
+#define MCF_DMA_IMCR_SRC23(x)(((x)0x0003)14)
+#define MCF_DMA_IMCR_SRC24(x)(((x)0x0003)16)
+#define MCF_DMA_IMCR_SRC25(x)(((x)0x0003)18)
+#define MCF_DMA_IMCR_SRC26(x)(((x)0x0003)20)
+#define MCF_DMA_IMCR_SRC27(x)(((x)0x0003)22)
+#define MCF_DMA_IMCR_SRC28(x)(((x)0x0003)24)
+#define MCF_DMA_IMCR_SRC29(x)(((x)0x0003)26)
+#define MCF_DMA_IMCR_SRC30(x)(((x)0x0003)28)
+#define MCF_DMA_IMCR_SRC31(x)(((x)0x0003)30)
+#define MCF_DMA_IMCR_SRC16_FEC0RX(0x)
+#define MCF_DMA_IMCR_SRC17_FEC0TX(0x)
+#define MCF_DMA_IMCR_SRC18_FEC0RX(0x0020)
+#define MCF_DMA_IMCR_SRC19_FEC0TX(0x0080)
+#define MCF_DMA_IMCR_SRC20_FEC1RX(0x0100)
+#define MCF_DMA_IMCR_SRC21_DREQ1 (0x)
+#define MCF_DMA_IMCR_SRC21_FEC1TX(0x0400)
+#define MCF_DMA_IMCR_SRC22_FEC0RX(0x1000)
+#define MCF_DMA_IMCR_SRC23_FEC0TX(0x4000)
+#define MCF_DMA_IMCR_SRC24_CTM0  (0x0001)
+#define MCF_DMA_IMCR_SRC24_FEC1RX(0x0002)
+#define MCF_DMA_IMCR_SRC25_CTM1  (0x0004)
+#define MCF_DMA_IMCR_SRC25_FEC1TX(0x0008)
+#define MCF_DMA_IMCR_SRC26_USBEP4(0x)
+#define MCF_DMA_IMCR_SRC26_CTM2  (0x0020)
+#define MCF_DMA_IMCR_SRC27_USBEP5(0x)
+#define MCF_DMA_IMCR_SRC27_CTM3  (0x0080)
+#define MCF_DMA_IMCR_SRC28_USBEP6(0x)
+#define MCF_DMA_IMCR_SRC28_CTM4  (0x0100)
+#define MCF_DMA_IMCR_SRC28_DREQ1 (0x0200)
+#define MCF_DMA_IMCR_SRC28_PSC2RX(0x0300)
+#define MCF_DMA_IMCR_SRC29_DREQ1 (0x0400)
+#define MCF_DMA_IMCR_SRC29_CTM5  (0x0800)
+#define MCF_DMA_IMCR_SRC29_PSC2TX(0x0C00)
+#define MCF_DMA_IMCR_SRC30_FEC1RX(0x)
+#define MCF_DMA_IMCR_SRC30_CTM6  (0x1000)
+#define MCF_DMA_IMCR_SRC30_PSC3RX(0x3000)
+#define MCF_DMA_IMCR_SRC31_FEC1TX(0x)
+#define MCF_DMA_IMCR_SRC31_CTM7  (0x8000)
+#define MCF_DMA_IMCR_SRC31_PSC3TX(0xC000)
+
+#endif /* __MCF548X_DMA_H__ */
diff --git a/arch/m68k/include/asm/m54xxdma_api.h 
b/arch/m68k/include/asm/m54xxdma_api.h
new file mode 100644
index 000..22bfb23
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxdma_api.h
@@ -0,0 +1,62 @@
+/
+ * Multichannel DMA definitions*
+ /
+#include linux/MCD_dma.h
+
+struct scatterlist;
+
+#define MAX_DMA_CHANNELS NCHANNELS
+/*
+ *  identifiers for each initiator/requestor
+ */
+#define DMA_ALWAYS  (0)
+#define DMA_DSPI_RX (1)
+#define DMA_DSPI_TX (2)
+#define DMA_DREQ0   (3)
+#define DMA_PSC0_RX (4)
+#define DMA_PSC0_TX (5)
+#define DMA_USBEP0  (6)
+#define DMA_USBEP1  (7)
+#define DMA_USBEP2  (8)
+#define DMA_USBEP3  (9)
+#define DMA_PCI_TX  (10)
+#define DMA_PCI_RX  (11)
+#define DMA_PSC1_RX (12)
+#define DMA_PSC1_TX

[uClinux-dev] [PATCH 3/3] m68knommu: Add ethernet driver for MCF547x/MCF548x

2012-09-24 Thread Philippe De Muyter 
This is a fully functionnal ethernet driver for the MCF547x and MCF548x
processors, tested on the M5484EVB board and on a custom board inpired
by the M5484EVB board.  It implements a FEC+DMA driver and a mdio driver.

Original work was made by freescale for 2.6.25, but never submitted for
mainline, but cache support, mdio driver, phylib support, general
cleanup and 2.6.30-3.6 ports are mine.

Signed-off-by: Philippe De Muyter p...@macqel.be
---
 arch/m68k/include/asm/m54xxsim.h   |2 +
 arch/m68k/kernel/setup_no.c|5 +
 drivers/net/ethernet/freescale/Kconfig |   26 +-
 drivers/net/ethernet/freescale/Makefile|1 +
 drivers/net/ethernet/freescale/fec_m54xx.c | 1506 
 drivers/net/ethernet/freescale/fec_m54xx.h |  144 +++
 6 files changed, 1683 insertions(+), 1 deletions(-)
 create mode 100644 drivers/net/ethernet/freescale/fec_m54xx.c
 create mode 100644 drivers/net/ethernet/freescale/fec_m54xx.h

diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index f5531d5..b4c81bf 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -46,6 +46,8 @@
 #define MCF_IRQ_UART2  (MCFINT_VECBASE + 33)
 #define MCF_IRQ_UART3  (MCFINT_VECBASE + 32)
 #define MCF_IRQ_DMA(MCFINT_VECBASE + 48)   /* DMA */
+#define MCF_IRQ_FEC0   (MCFINT_VECBASE + 39)   /* FEC0 */
+#define MCF_IRQ_FEC1   (MCFINT_VECBASE + 38)   /* FEC1 */
 
 /*
  * Generic GPIO support
diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
index 71fb299..10131b4 100644
--- a/arch/m68k/kernel/setup_no.c
+++ b/arch/m68k/kernel/setup_no.c
@@ -261,6 +261,11 @@ void __init setup_arch(char **cmdline_p)
paging_init();
 }
 
+const char *machdep_get_mac_address(int i)
+{
+   return 0;
+}
+
 /*
  * Get CPU information for use by the procfs.
  */
diff --git a/drivers/net/ethernet/freescale/Kconfig 
b/drivers/net/ethernet/freescale/Kconfig
index 3574e14..64d8fc6 100644
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -7,7 +7,7 @@ config NET_VENDOR_FREESCALE
default y
depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
   M523x || M527x || M5272 || M528x || M520x || M532x || \
-  ARCH_MXC || ARCH_MXS || (PPC_MPC52xx  PPC_BESTCOMM)
+  M54xx || ARCH_MXC || ARCH_MXS || (PPC_MPC52xx  
PPC_BESTCOMM)
---help---
  If you have a network (Ethernet) card belonging to this class, say Y
  and read the Ethernet-HOWTO, available from
@@ -30,6 +30,30 @@ config FEC
  Say Y here if you want to use the built-in 10/100 Fast ethernet
  controller on some Motorola ColdFire and Freescale i.MX processors.
 
+config FEC_54xx
+   tristate MCF547x/MCF548x Fast Ethernet Controller support
+   depends on M54xx
+   default y
+   select CRC32
+   select PHYLIB
+   select M54xx_DMA
+   help
+ The MCF547x and MCF548x have a built-in Fast Ethernet Controller.
+ This is not the same FEC controller as on other ColdFire as here
+ the DMA controller is not reserved to the FEC driver, but made
+ available for general DMA work.
+ Saying Y here will include support for this device in the kernel.
+
+config FEC2
+   bool Second FEC ethernet controller (on some ColdFire CPUs)
+   depends on FEC || FEC_54xx
+   default y
+   help
+ Say Y here if you want to use the second built-in 10/100 Fast
+ ethernet controller on some Motorola ColdFire processors. On M54xx,
+ If your second ethernet port is not connected, saying N here will
+ free 2 DMA channels and allow you to use FEC io ports as GPIO's.
+
 config FEC_MPC52xx
tristate FEC MPC52xx driver
depends on PPC_MPC52xx  PPC_BESTCOMM
diff --git a/drivers/net/ethernet/freescale/Makefile 
b/drivers/net/ethernet/freescale/Makefile
index 1752488..05a5022 100644
--- a/drivers/net/ethernet/freescale/Makefile
+++ b/drivers/net/ethernet/freescale/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_FEC) += fec.o
+obj-$(CONFIG_FEC_54xx) += fec_m54xx.o
 obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o
 ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y)
obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o
diff --git a/drivers/net/ethernet/freescale/fec_m54xx.c 
b/drivers/net/ethernet/freescale/fec_m54xx.c
new file mode 100644
index 000..b28c89a
--- /dev/null
+++ b/drivers/net/ethernet/freescale/fec_m54xx.c
@@ -0,0 +1,1506 @@
+/*
+ * Performance and stability improvements: (C) Copyright 2008,
+ *  Daniel Krueger, SYSTEC electronic GmbH
+ *
+ * Code crunched to get it to work on 2.6.24 -- FEC cleanup coming
+ * soon -- Kurt Mahan
+ *
+ * 2.6.30 and above port, cleanup, cache support, netdev_ops, mdio,
+ * phy  ethtool support,
+ * (C) Copyright 2010-2012 Philippe De Muyter p...@macqel.be Macq SA
+ */