Re: [USRP-users] I want to build my custom FPGA image but failed to get the license
Hi,
Which OS and OS Version are you using?
Regards,
Nate
> On Jul 25, 2017, at 5:55 PM, 이진세 via USRP-users
> wrote:
>
> hello
>
> I use e310 and try to build custom fpga image.
>
> and i entered a trial license, including webPack, from Vivado License manager.
>
> In the View License Status tab, the license named Synthesis and XC7Z020 is
> displayed.
>
> However, i received error message saying that the license is not available.
>
> this is error log about command 'sudo ./uhd_image_builder.py window fft -d
> e310 -t E310_RFNOC_sg3 -m 5 --fill-with-fifos'.
>
> please tell me what is wrong.
>
> thanks.
>
>
> spade@spade-DREAMPRO:~/rfnoc/src/uhd-fpga/usrp3/tools/scripts$ sudo
> ./uhd_image_builder.py window fft -d e310 -t E310_RFNOC_sg3 -m 5
> --fill-with-fifos
> [sudo] password for spade:
> --Using the following blocks to generate image:
> * window
> * fft
> Adding CE instantiation file for 'E310_RFNOC_sg3'
> changing temporarily working directory to
> /home/spade/rfnoc/src/uhd-fpga/usrp3/tools/scripts/../../top/e300
> Setting up a 64-bit FPGA build environment for the USRP-E3x0...
> - Vivado: Found (/opt/Xilinx/Vivado/2015.4/bin)
> - Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin)
>
> Environment successfully initialized.
> make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
> PART_ID=xc7z020/clg484/-3 RFNOC=1 E310=1 EXTRA_DEFS="RFNOC=1 E310=1"
> make[1]: Entering directory '/home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300'
> BUILDER: Checking tools...
> * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
> * Python 2.7.12
> * Vivado v2015.4 (64-bit)
>
> BUILDER: Building IP axi_fft
>
> BUILDER: Staging IP in build directory...
> BUILDER: Reserving IP location:
> /home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_fft
> BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
> BUILDER: Building IP...
>
> ** Vivado v2015.4 (64-bit)
> SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
> IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
> ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
>
> source /home/spade/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl
> # set xci_file $::env(XCI_FILE) ;
> # set part_name$::env(PART_NAME) ;
> # set gen_example_proj $::env(GEN_EXAMPLE);
> # set synth_ip $::env(SYNTH_IP) ;
> # set ip_name [file rootname [file tail $xci_file]] ;
> # file delete -force "$xci_file.out"
> # create_project -part $part_name -in_memory -ip
> # set_property target_simulator XSim [current_project]
> # add_files -norecurse -force $xci_file
> INFO: [IP_Flow 19-234] Refreshing IP repositories
> INFO: [IP_Flow 19-1704] No user IP repositories specified
> INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
> '/opt/Xilinx/Vivado/2015.4/data/ip'.
> # reset_target all [get_files $xci_file]
> # puts "BUILDER: Generating IP Target..."
> BUILDER: Generating IP Target...
> # generate_target all [get_files $xci_file]
> INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP
> 'axi_fft'...
> INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_fft'...
> INFO: [Device 21-403] Loading part xc7z020clg484-3
> INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_fft'...
> INFO: [IP_Flow 19-1686] Generating 'C Simulation' target for IP 'axi_fft'...
> INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'axi_fft'...
> INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_fft'...
> generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB):
> peak = 1134.184 ; gain = 162.906 ; free physical = 1258 ; free virtual = 6661
> # if [string match $synth_ip "1"] {
> # puts "BUILDER: Synthesizing IP Target..."
> # synth_ip [get_ips $ip_name]
> # }
> BUILDER: Synthesizing IP Target...
> INFO: [IP_Flow 19-234] Refreshing IP repositories
> INFO: [IP_Flow 19-1704] No user IP repositories specified
> INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
> '/opt/Xilinx/Vivado/2015.4/data/ip'.
> Command: synth_design -top axi_fft -part xc7z020clg484-3 -mode out_of_context
> Starting synth_design
> Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
> WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis'
> and/or device 'xc7z020'
> 1 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
> synth_design failed
> ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis'
> and/or device 'xc7z020'. Please run the Vivado License Manager for assistance
> in determining
> which features and devices are licensed for your system.
> Resolution: Check the status of your licenses in the Vivado License Manager.
> For debug help search Xilinx Support for "Licensing FAQ".
Re: [USRP-users] 答复: frequency shift of B210
Hi all, Any suggestions is welcome. best regards Jong On Mon, Jul 24, 2017 at 5:35 PM, john liu wrote: > HI,all, > Do you have any suggestions about this? > thank you. > best regards > John > > On Mon, Jul 24, 2017 at 9:15 AM, 戚科峰(研三 福州) > wrote: > >> Hi,Marcus, >> >> >> >> we use The B210 as a basestation and cc1120 as the tranceiver of UE. >> >> The B210 uses the Frequency offset estimation algorithm to estimate the >> frequency offset of cc1120 and records it. >> >> there are several UE in the system,UE will receive the B210'signal >> periodically and will send a signal to B210 in another period. >> >> when the phenomenon of the 3.2k frequency shift occured， all UE could >> not receive the signal of B210.when time for UE to send a signal， >> >> B210 would estimate the new frequency shift and found that the Frequency >> offset of every UE shifts 3.2k。So we think the shifting occured in B210 >> instead of UE。 >> >> >> >> best regards >> >> >> >> >> >> *发件人:* john liu [mailto:johncorad1...@gmail.com] >> *发送时间:* 2017年7月21日 16:42 >> *收件人:* Marcus D. Leech >> *抄送:* USRP-users@lists.ettus.com; 戚科峰(研三 福州) >> *主题:* Re: frequency shift of B210 >> >> >> >> Hi,Marcus, >> >> We calculated this. >> >> The B210 not only generate a GFSK signal,but also received the signal >> from CC1120.The CC1120 and B210 both work in full duplex mode. >> >> Hi qi, >> >> Can you describe your test method?I am not clear for that. >> >> >> >> best regards >> >> John >> >> >> >> >> >> On Fri, Jul 21, 2017 at 10:47 AM, Marcus D. Leech >> wrote: >> >> On 07/20/2017 10:08 PM, john liu wrote: >> >> i am sorry. >> >> We generate a GFSK signal with B210 and received the signal with >> multiple cc1120.When frequency shift occurred,the cc1120 can not received >> the signal. >> >> Also, another b210 has been running for several days without such a jump >> phenomenon. >> >> So, sorry to be a bother, but, where did the 3.2kHz frequency shift >> measurement come from? The CC1120 is just a GFSK demodulating digital >> receiver. >> >> >> >> >> >> On Fri, Jul 21, 2017 at 9:37 AM, Marcus D. Leech >> wrote: >> >> No i mean what were you measuring? >> >> >> >> Were you using an external signal generator and what were its specs? >> >> >> >> >> Sent from my iPhone >> >> >> On Jul 20, 2017, at 9:09 PM, john liu wrote: >> >> HI Marcus, >> >> internal with TCXO. >> >> >> >> On Thu, Jul 20, 2017 at 11:31 PM, Marcus D. Leech >> wrote: >> >> On 07/20/2017 02:22 AM, john liu wrote: >> >> >> >> What was your tuned frequency in this case? >> >> >> >> Hi,Marcus, >> >> >> >> It is 433.05Mhz >> >> That's about 7PPM. >> >> What was your signal source? >> >> >> >> >> >> On Thu, Jul 20, 2017 at 11:46 AM, john liu >> wrote: >> >> Hi all, >> >> We used B210 with TCXO,and run about 2 hours , a 3.2K frequency shift >> occurred when the temperature did not change significantly.Is it a normal? >> >> How can we improve this situation? >> >> >> >> thank you. >> >> best regards >> >> John >> >> >> >> >> >> >> >> >> >> >> >> >> > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] I want to build my custom FPGA image but failed to get the license
hello
I use e310 and try to build custom fpga image.
and i entered a trial license, including webPack, from Vivado License manager.
In the View License Status tab, the license named Synthesis and XC7Z020 is
displayed.
However, i received error message saying that the license is not available.
this is error log about command 'sudo ./uhd_image_builder.py window fft -d e310
-t E310_RFNOC_sg3 -m 5 --fill-with-fifos'.
please tell me what is wrong.
thanks.
spade@spade-DREAMPRO:~/rfnoc/src/uhd-fpga/usrp3/tools/scripts$ sudo
./uhd_image_builder.py window fft -d e310 -t E310_RFNOC_sg3 -m 5
--fill-with-fifos
[sudo] password for spade:
--Using the following blocks to generate image:
* window
* fft
Adding CE instantiation file for 'E310_RFNOC_sg3'
changing temporarily working directory to
/home/spade/rfnoc/src/uhd-fpga/usrp3/tools/scripts/../../top/e300
Setting up a 64-bit FPGA build environment for the USRP-E3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2015.4/bin)
- Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin)
Environment successfully initialized.
make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
PART_ID=xc7z020/clg484/-3 RFNOC=1 E310=1 EXTRA_DEFS="RFNOC=1 E310=1"
make[1]: Entering directory '/home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2015.4 (64-bit)
BUILDER: Building IP axi_fft
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_fft
BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
BUILDER: Building IP...
** Vivado v2015.4 (64-bit)
SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source /home/spade/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl
# set xci_file $::env(XCI_FILE) ;
# set part_name$::env(PART_NAME) ;
# set gen_example_proj $::env(GEN_EXAMPLE);
# set synth_ip $::env(SYNTH_IP) ;
# set ip_name [file rootname [file tail $xci_file]] ;
# file delete -force "$xci_file.out"
# create_project -part $part_name -in_memory -ip
# set_property target_simulator XSim [current_project]
# add_files -norecurse -force $xci_file
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
# reset_target all [get_files $xci_file]
# puts "BUILDER: Generating IP Target..."
BUILDER: Generating IP Target...
# generate_target all [get_files $xci_file]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP
'axi_fft'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_fft'...
INFO: [Device 21-403] Loading part xc7z020clg484-3
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_fft'...
INFO: [IP_Flow 19-1686] Generating 'C Simulation' target for IP 'axi_fft'...
INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'axi_fft'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_fft'...
generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB):
peak = 1134.184 ; gain = 162.906 ; free physical = 1258 ; free virtual = 6661
# if [string match $synth_ip "1"] {
# puts "BUILDER: Synthesizing IP Target..."
# synth_ip [get_ips $ip_name]
# }
BUILDER: Synthesizing IP Target...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
Command: synth_design -top axi_fft -part xc7z020clg484-3 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis'
and/or device 'xc7z020'
1 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis'
and/or device 'xc7z020'. Please run the Vivado License Manager for assistance
in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager.
For debug help search Xilinx Support for "Licensing FAQ".
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception:
[USRP-users] Using a reference clock on USRP E310/312
Hello - I have 2 USRPs (both E310/E312) which I want to sync up using an external clock. I read that the embedded series cannot take in a 10MHz reference clock but can take in a 1PPS. I generated a 1 PPS signal using a signal generator and using a power splitter, I sent the 1PPS signal to both USRPs via the sync port on the USRPs. When I try to run an example programs (rx_samples_to_file on one USRP and tx_samples_from_file on the other USRP) using the ref argument, it says that the ref argument is not supported. How can I sync up the two USRPs? Thanks ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Issues with dual full duplex on x310
Hi, I'm using gnuradio 3.7.12 and rfnoc-devel commit 1908672. I'm trying to use both daughter boards on the x310 each at full duplex (that is, I will have 2 independent tx paths and 2 independent rx paths). So far I have accomplished this by using the UHD: USRP Sink/Source blocks and setting them to 2 channels, selecting the appropriate antennas, and specifying a subdev spec of A:0 B:0. The flowgraph works perfectly sending and receiving 2 sets of data simultaneously. However, I need to have the same capability when using the RFNoC blocks. I've attempted to use 2 RFNoC radio blocks, one set to Tx, 2 channels, and the other set to Rx, 2 channels, however the block's parameters have only a radio select of A or B unlike the usrp source's subdev spec, so this setup does not appear to work no matter what configurations I try. Am I mistaken about what the 2 channels refers to here? I did finally get an RFNoC setup that works by using 4 RFNoC radio blocks (2 for transmit with radio select A, B respectively, and 2 for receive with radio select A, B respectively). However, with this setup I get tons of underflow "U" in the console. Curiously this happens even when using the DMAFIFO as ettus recommends so I'm not sure what's going on. My flowgraph is attached showing this setup. (A quick note on why I want to use the rfnoc blocks, apparently the uhd usrp sink block now automatically includes a DMAFIFO in the tx chain to deal with the underflow issue caused by tcp flow control, however for my application the depth/size of this fifo is much too large and causing massive delays, I've found that by reducing the depth I can minimize my delay and I'll only get underflows on flowgraph startup which I assume is due to the tcp slow start phase before backoff occurs. All this to say, if there is a way to adjust the dma fifo depth from the usrp sink blocks I'd gladly use that instead). Thanks, Mike test_dual_fullduplex_x310.grc Description: Binary data ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] X300 recovery after LATE_COMMAND or OVERFLOW_ERROR
Hi Martin, Without seeing some source code, it is difficult to say exactly what is going on. The ERROR_CODE_LATE_COMMAND means that the radio block in the FPGA received a command late. An ERROR_CODE_OVERFLOW with the out_of_sequence flag set is alarming and means that packets are getting dropped somewhere. Make sure you have the number of RX buffers set to max (i.e. sudo ethtool -G rx 4096). An ERROR_CODE_OVERFLOW without the out_of_sequence flag set most likely means there is too much of a delay before a recv() call somewhere in your code. The "failure to align" error is the UHD code attempting and failing to re-align the data streams. When an overflow occurs, UHD will stop the streams and re-issue stream commands to try to realign the data. Data is discarded until packets with the same timestamp on all streams are seen. It sounds to me like occasionally the application is falling behind and the recovery attempts are having issues due to dropped packets. We did some testing with the X710 and found that it is possible to overrun the socket buffer because the driver for the X710 seems to use up the full MTU size in the socket buffer regardless of the actual packet size. This potentially leads to dropped packets. You can try increasing the socket buffer size using the recv_buff_size parameter (i.e. set to 50 MB) in the device arguments, but that will not make a difference if there is a delay before the recv() call somewhere in the application that allows the socket buffer to fill up. Regards, Michael On Tue, Jul 25, 2017 at 12:22 PM, Martin Guski via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi! > > We are using 8 X300s which are each connected to a computer via dedicated > 10 GigE ports. Our application is transmitting and receiving for bursts of > 1 second (@10 Msps) on both slots of the USRP. After that we process the > data, transmit/receive again, and so on. > > After running without errors for some time (a few hour), the rx_streamer > returns errors for the next four bursts in the following pattern: > > 1) ERROR_CODE_LATE_COMMAND > 2) ERROR_CODE_LATE_COMMAND > 3) ERROR_CODE_OVERFLOW > 4) ERROR_CODE_TIMEOUT > > And after that it usually continues running without problems for about 20 > - 60 min before it happens again. All 8 USRPs report the errors at the same > time. (Each USRP is controlled by a separate multi_usrp running in a > dedicated process..) > I took a closer look when I start the streaming: The first LATE_COMMAND is > really to late (time of preparation of the stream varies ). The following > command if definitely not to late, but nevertheless the LATE_ERROR is > raised. > > Sometimes one USRP doesn't recover after returning the ERROR_CODE_TIMEOUT > error and reports LATE_COMMAND and OVERFLOW_ERRORS (with and without > out_of_sequence flag) for all following transmissions. After restarting the > usrp program everything works again. > > And from time to time I also get this error: > >> UHD Error: >> The receive packet handler failed to time-align packets. >> 1002 received packets were processed by the handler. >> However, a timestamp match could not be determined. > > > So my question is: Is there a way to recover the USRP or the steamer after > I detect an extended sequence of LATE_COMMAND and OVERFLOW_ERRORS? > > > Thanks > Martin > > *Maybe some interesting further information:* > - The error only occurs when using both slots of the USRP, for one side > everything works. > - Reducing the sampling rate to 5 Msps doesn't help > - The ERROR_CODE_TIMEOUT is new for the new UHD3.9.7 release and it looks > like this resets the USRP sometimes. > - For the older versions of UHD 3.9 it never recovered form the first > occurring error. > - For UHD3.10 (maint branch) after ( I guess) the first error occurred the > driver process had a CPU usage of 200 % until the process was killed. Also > there were underflows for nearly each transmission (when using both > sides/channels and 10 Msps). > > > *More information about our setup:* > > Ubuntu 16.04.1 LTS > UHD_003.009.007 release > > X300 > - Hardware Versions 5, 6 > Frontends: 2x LFRX and 2x LFTX2x > > Intel i7 (i7-5930K @3.50GHz, 6 Cores / 12 threads), 12 GB Ram > - disabled CPU power management > > Network: Intel X710 for 10GbE SFP+ (quad-port) > Each X300 (port1) connected directly to NIC port, all have separate > netmasks > - MTU set to 9000 > - increase the maximum size of the socket buffers > - Flow Control disabled for rx and tx > - ifconfig shows 0 errors, dropped packets or overruns > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] X300 recovery after LATE_COMMAND or OVERFLOW_ERROR
Hi! We are using 8 X300s which are each connected to a computer via dedicated 10 GigE ports. Our application is transmitting and receiving for bursts of 1 second (@10 Msps) on both slots of the USRP. After that we process the data, transmit/receive again, and so on. After running without errors for some time (a few hour), the rx_streamer returns errors for the next four bursts in the following pattern: 1) ERROR_CODE_LATE_COMMAND 2) ERROR_CODE_LATE_COMMAND 3) ERROR_CODE_OVERFLOW 4) ERROR_CODE_TIMEOUT And after that it usually continues running without problems for about 20 - 60 min before it happens again. All 8 USRPs report the errors at the same time. (Each USRP is controlled by a separate multi_usrp running in a dedicated process..) I took a closer look when I start the streaming: The first LATE_COMMAND is really to late (time of preparation of the stream varies ). The following command if definitely not to late, but nevertheless the LATE_ERROR is raised. Sometimes one USRP doesn't recover after returning the ERROR_CODE_TIMEOUT error and reports LATE_COMMAND and OVERFLOW_ERRORS (with and without out_of_sequence flag) for all following transmissions. After restarting the usrp program everything works again. And from time to time I also get this error: > UHD Error: > The receive packet handler failed to time-align packets. > 1002 received packets were processed by the handler. > However, a timestamp match could not be determined. So my question is: Is there a way to recover the USRP or the steamer after I detect an extended sequence of LATE_COMMAND and OVERFLOW_ERRORS? Thanks Martin *Maybe some interesting further information:* - The error only occurs when using both slots of the USRP, for one side everything works. - Reducing the sampling rate to 5 Msps doesn't help - The ERROR_CODE_TIMEOUT is new for the new UHD3.9.7 release and it looks like this resets the USRP sometimes. - For the older versions of UHD 3.9 it never recovered form the first occurring error. - For UHD3.10 (maint branch) after ( I guess) the first error occurred the driver process had a CPU usage of 200 % until the process was killed. Also there were underflows for nearly each transmission (when using both sides/channels and 10 Msps). *More information about our setup:* Ubuntu 16.04.1 LTS UHD_003.009.007 release X300 - Hardware Versions 5, 6 Frontends: 2x LFRX and 2x LFTX2x Intel i7 (i7-5930K @3.50GHz, 6 Cores / 12 threads), 12 GB Ram - disabled CPU power management Network: Intel X710 for 10GbE SFP+ (quad-port) Each X300 (port1) connected directly to NIC port, all have separate netmasks - MTU set to 9000 - increase the maximum size of the socket buffers - Flow Control disabled for rx and tx - ifconfig shows 0 errors, dropped packets or overruns ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] E310 rx_samples_from_file stores data based on sample rate and not Bandwidth
On 07/25/2017 08:43 AM, olivani via USRP-users wrote:
Hi ,
Let me first describe my application
I have to collected data (type short, wirefmt sc16) at a particular
center frequency at a sampling rate of 25 Msps and set the bandwidth
to be 20 MHz and the master clock is set to be 25 MHz. I have a custom
fpga to detect the presence of unwanted signal within the 20 MHz bw of
data collected .
I am using rx_samples_to_file script to collect data . I assume that
when I plot the data ,, any tone below -10MHz and beyond +10 MHz
should be discarded.
But when I used the script ./rx_samples_to_file I noticed that the
data collected is equal to the sample rate specified and when plotted
using pwelch function with bin size 512 I still see the tone after 20
MHz bw.
/usr/lib/uhd/examples/rx_samples_to_file --file /dev/test_5bw_20msps_1
--subdev A:A --args="type=e3x0,master_clock_rate=25e6" --bw 20e6
--freq 110e6 --rate 25e6 --duration 1 --stats
as per input parameter specified above I set the centre frequency at
110 MHz and have injected a tone at 122.5 MHz and set the BW to be 20
MHz. I assumed the tone should not be visible , but unfortunately it
does.
This may lead to faulty detection in my application.
1. I added debug statements to see if at all the bw setting code is
executed and it does.
2. I varied the bandwidth to be 5 MHz and I am able to see the roll
off and also the tone.
Please find the plot below for the above input command
Inline image 1
Now setting the bandwidth to 5 MHz for verification purposeInline image 2
The code snippet used to plot the data in matlab as follows
binary_file =
'\\fargo\projects\wls\staging\subbuku-o\test_5bw_20msps_1';%./rx_samples_to_file
--file /dev/test_5bw_20msps_2 --subdev A:B
--args="type=e3x0,master_clock_rate=50e6" --bw 20e6 --freq 110e6
--rate 25e6 --duration 1 --stats
if~exist('plotOn', 'var') || isempty(plotOn)
plotOn = 1;
end
if~exist('power_dbm', 'var') || isempty(power_dbm)
power_dbm = -100;
end
fid = fopen(binary_file,'r');
%A = fread(fid,inf,'bit16','ieee-le');
if~exist('wordWidth','var') || isempty(wordWidth)
% default to 16 bits...
A = fread(fid,inf,'bit16','ieee-le');
else
% extract according to word desired word width
width = ['bit',num2str(wordWidth)];
A = fread(fid,inf,width,'ieee-le');
end
%A = fread(fid,inf,'bit16','ieee-le');
%A = fread(fid,inf,'float32');
%parse the entire binary file
%A = fread(fid);
fclose(fid);
%A = A(1:2*4096);
I = A(1:2:end);
%figure; plot(I,'b-'); %-->counter test
Q = A(2:2:end);
if0
figure;
mag = 20*log10(abs(I));
plot(faxis,mag(1:N));
end
complex_sig = I + 1i*Q;
%complex_sig = transpose(complex_sig);
%fs = 1024e3;%512e3; %1024kHz for 4x and 8x; 768kHz, 512kHz and 256kHz
for 6x, 2x and 1x
%fs = 512e3;
%fs = 256e3;
%fs = 7.68e6;
%fs = 15.36e6;
%fs = 7.68e6;
fs =25e6;
%[Pxx,F] =
pwelch(complex_sig(1:4096*15),4096,[],[],fs,'centered');%%4x and 8x
%[Pxx,F] = pwelch(complex_sig(1:end),[],[],fs,'centered');%%4x and 8x
[Pxx,F] = pwelch(complex_sig(1:end),512,[],[],fs,'centered');%%4x and 8x
ifplotOn
figure; plot(F,10*log10((Pxx)),'b-'); grid on
title(binary_file)
ifexist('title_str','var')
if~isempty(title_str)
title(title_str)
end
end
end
Please let me know if it is possible to resolve the issue to
eliminating the tone beyond 20 MHz bandwidth for 25 Msps sampling rate
. I know with bandwidth and sample rate being pretty close it might
not be possible to eliminate the tone or there might be aliasing
effect . I did increase the master clock but the highest I could go is
50 MHz. I need 25 Msps sample rate and cannot change that.
Thanks and Regards,
Olivani
If you're only using a single channel, then you might try increasing the
master clock rate to 50MHz, which will give the digital filtering more
"head room"
to work.
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[USRP-users] E310 rx_samples_from_file stores data based on sample rate and not Bandwidth
Hi ,
Let me first describe my application
I have to collected data (type short, wirefmt sc16) at a particular center
frequency at a sampling rate of 25 Msps and set the bandwidth to be 20 MHz
and the master clock is set to be 25 MHz. I have a custom fpga to detect
the presence of unwanted signal within the 20 MHz bw of data collected .
I am using rx_samples_to_file script to collect data . I assume that when I
plot the data ,, any tone below -10MHz and beyond +10 MHz should be
discarded.
But when I used the script ./rx_samples_to_file I noticed that the data
collected is equal to the sample rate specified and when plotted using
pwelch function with bin size 512 I still see the tone after 20 MHz bw.
/usr/lib/uhd/examples/rx_samples_to_file --file /dev/test_5bw_20msps_1
--subdev A:A --args="type=e3x0,master_clock_rate=25e6" --bw 20e6 --freq
110e6 --rate 25e6 --duration 1 --stats
as per input parameter specified above I set the centre frequency at 110
MHz and have injected a tone at 122.5 MHz and set the BW to be 20 MHz. I
assumed the tone should not be visible , but unfortunately it does.
This may lead to faulty detection in my application.
1. I added debug statements to see if at all the bw setting code is
executed and it does.
2. I varied the bandwidth to be 5 MHz and I am able to see the roll off and
also the tone.
Please find the plot below for the above input command
[image: Inline image 1]
Now setting the bandwidth to 5 MHz for verification purpose[image: Inline
image 2]
The code snippet used to plot the data in matlab as follows
binary_file =
'\\fargo\projects\wls\staging\subbuku-o\test_5bw_20msps_1';%./rx_samples_to_file
--file /dev/test_5bw_20msps_2 --subdev A:B
--args="type=e3x0,master_clock_rate=50e6"
--bw 20e6 --freq 110e6 --rate 25e6 --duration 1 --stats
if ~exist('plotOn', 'var') || isempty(plotOn)
plotOn = 1;
end
if ~exist('power_dbm', 'var') || isempty(power_dbm)
power_dbm = -100;
end
fid = fopen(binary_file,'r');
%A = fread(fid,inf,'bit16','ieee-le');
if ~exist('wordWidth','var') || isempty(wordWidth)
% default to 16 bits...
A = fread(fid,inf,'bit16','ieee-le');
else
% extract according to word desired word width
width = ['bit',num2str(wordWidth)];
A = fread(fid,inf,width,'ieee-le');
end
%A = fread(fid,inf,'bit16','ieee-le');
%A = fread(fid,inf,'float32');
%parse the entire binary file
%A = fread(fid);
fclose(fid);
%A = A(1:2*4096);
I = A(1:2:end);
%figure; plot(I,'b-'); %-->counter test
Q = A(2:2:end);
if 0
figure;
mag = 20*log10(abs(I));
plot(faxis,mag(1:N));
end
complex_sig = I + 1i*Q;
%complex_sig = transpose(complex_sig);
%fs = 1024e3;%512e3; %1024kHz for 4x and 8x; 768kHz, 512kHz and 256kHz for
6x, 2x and 1x
%fs = 512e3;
%fs = 256e3;
%fs = 7.68e6;
%fs = 15.36e6;
%fs = 7.68e6;
fs =25e6;
%[Pxx,F] = pwelch(complex_sig(1:4096*15),4096,[],[],fs,'centered');%%4x and
8x
%[Pxx,F] = pwelch(complex_sig(1:end),[],[],fs,'centered');%%4x and 8x
[Pxx,F] = pwelch(complex_sig(1:end),512,[],[],fs,'centered');%%4x and 8x
if plotOn
figure; plot(F,10*log10((Pxx)),'b-'); grid on
title(binary_file)
if exist('title_str','var')
if ~isempty(title_str)
title(title_str)
end
end
end
Please let me know if it is possible to resolve the issue to eliminating
the tone beyond 20 MHz bandwidth for 25 Msps sampling rate . I know with
bandwidth and sample rate being pretty close it might not be possible to
eliminate the tone or there might be aliasing effect . I did increase the
master clock but the highest I could go is 50 MHz. I need 25 Msps sample
rate and cannot change that.
Thanks and Regards,
Olivani
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