date:20171011

Re: [USRP-users] No output from OOT RFNOC Module

2017-10-11 Thread Dario Pennisi via USRP-users

Hi,
If your block is sending small amounts of bursty data the timeout being printed 
is irrelevant as it just indicates no data has been sent for a given time lapse 
not that no data has been received at all.

Dario Pennisi








On Wed, Oct 11, 2017 at 10:10 PM +0200, "John Medrano via USRP-users" 
> wrote:

We are in process of debugging an out of tree module that we created. It is a 
source object that generates a given sequence.

We have compiled and loaded in our X310 device and all looks good. But when we 
run it, we get no output.

Below is some of the output from the device.

Two questions:

1. Why do we receive the following debug message:
[INFO] [RFNOC] Assuming max packet size for 0/memory_0

2. What is meant by RFNOC blocks with streaming port, and creating rx_streamer 
messages?

Please advise,

Thanks,
John

[INFO] [CORES] Performing timer loopback test...
[INFO] [CORES] Timer loopback test passed
INFO: Setting args on 0/FIFO_0 (gr_vlen=256,spp=256)
DEBUG: output item size: 2048
INFO: Setting args on 0/memory_0 (gr_vlen=256,spp=256)
DEBUG: output item size: 2048
[INFO] [RFNOC] Assuming max packet size for 0/memory_0
DEBUG: check_topology()
DEBUG: RFNoC blocks with streaming ports: 1
DEBUG: start(): ninputs == 0 noutputs == 1
DEBUG: creating rx streamer with: 
gr_vlen=256,spp=256,block_id=0/FIFO_0,block_port=0
timeout on chan 0

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[USRP-users] Removing DC offset on USRP B200

2017-10-11 Thread Oliver Wayne via USRP-users

Hello,

I've implemented a DDS signal on the USRP device. In radio_legacy.v, I
input get_tx_I and get_tx_Q as my I and Q channels.

   always @(posedge radio_clk) begin tx[31:16] <= (run_tx) ?
get_tx_I[31:16] : tx_idle[31:16]; // I channel tx[15:0] <= (run_tx) ?
get_tx_Q[31:16] : tx_idle[15:0]; // Q channel end These are 32 bit
registers and I calculate the value of get_tx_I and get_tx_Q in external
modules. Currently I use 10 bit registers in my sine lookup table, so
something like

sine[0] = 340;
sine[1] = 342;
...
And I sum several of these sine terms, then set get_tx_I(Q) equal to their
sum. The problem is this has a DC offset, which means that that the local
oscillator signal also shows up in my spectrum, which I don't want. When I
try to kill the DC offset, so I write

sine[0] = 0;
sine[1] = 1;
...

Then I still get a local oscillator term, but also get garbage in the
spectrum. What's the optimal way to remove a DC offset? I was not sure
whether I should explicitly write out the negative value as two's
complement in the lookup table, or use something like
https://files.ettus.com/manual/classuhd_1_1usrp_1_1multi__usrp.html#
a263ab7f0364c03e8a6e330c546769e4f.

thanks
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Re: [USRP-users] Frequency offset between two USRPs B210 synchronized with use of Octoclock-G

2017-10-11 Thread Piotr Krysik via USRP-users

Hi all,

After discussion on IRC and few questions (by Brian Padalino and Marcus
D. Leech), that made me not so sure about how I made the measurement, I
found the reason for frequency offset.

It wasn't fault of USRP B210 or broken cable providing 10MHz reference
signal. The issue was a bit more complex:
-two B210s were not time synchronized,
-signal generator wasn't producing ideal sine wave but with slightly
drifting frequency (connecting the generator's Ref input to Octoclock
didn't help in case of that particular generato, which was FLUKE 6061A).

If at two points in time frequency of the generated signal is different,
then by looking at the phase difference between two USRPs, that are time
shifted with respect to each other, the effects of that frequency
difference will be observed.

I made the following experiment to show that it was generator's fault:
-phase difference between inputs of two USRPs was constantly measured,
-first I connected FLUKE 6061A signal generator to USRPs (through splitter),
-then I've disconnected the splitter from that generator and connected
another one(Agilent N5182A),
-both generators' Ref inputs were connected to Octoclock-G.

The effect can be seen on the attached image. For FLUKE 6061A you can
observe frequency offset while for Agilent N5182A in the measured period
no frequency offset effect can be observed.

So the conclusion is to synchronize USRPs B210 in time and to not trust
our FLUKE 6061A signal generator as a laboratory equipment.

Best Regards,
Piotr Krysik
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[USRP-users] RFNoC Block with 2 inputs and 1 output

2017-10-11 Thread Andrew Thommesen via USRP-users

Hi all,

I am trying to create a custom RFNoC block with 2 inputs and 1 output. I have 
attached my block code as well as the XML files for the UHD and GNU radio 
integration. The block behaves as expected when I run the testbench. However, 
when synthesised and used within the GNU radio flowgraph it does not seem to 
output anything. Further investigation using chipscope revealed that 
m_axis_data_tvalid is only ever 0 or 1. In simulation, the value can be 3 when 
data is received on both input channels. This suggests that on the hardware I 
am not receiving data from both streams, which would explain why I never get 
any output. This may suggest that the XML files are incorrect? Does anyone know 
what I could be doing wrong?

Thanks,

Andy



  combiner
  combiner
  
CF4CE20A208DF91B
  
  
  

  in0
  sc16
  0


  in1
  sc16
  1


  out0
  sc16

  



noc_block_combiner.v
Description: noc_block_combiner.v


  RFNoC: combiner
  tutorial_combiner
  tutorial
  import tutorial
  tutorial.combiner(
  self.device3,
  uhd.stream_args( # TX Stream Args
cpu_format="fc32",
otw_format="sc16",
channels = (0,1),
args="gr_vlen={0},{1}".format(${grvlen}, "" if $grvlen == 1 else "spp={0}".format($grvlen)),
  ),
  uhd.stream_args( # RX Stream Args
cpu_format="fc32",
otw_format="sc16",
args="gr_vlen={0},{1}".format(${grvlen}, "" if $grvlen == 1 else "spp={0}".format($grvlen)),
  ),
  $block_index,$device_index
  )
  

  
Host Data Type
type
enum

  Complex float32
  fc32
  type:complex


  Complex int16
  sc16
  type:sc16


  Byte
  u8
  type:byte


  VITA word32
  item32
  type:s32

  
  
  
Device Select
device_index
-1
int
#if int($device_index())  0 then 'part' else 'none'#
RFNoC Config
  

  
combiner Select
block_index
-1
int
#if int($block_index())  0 then 'part' else 'none'#
RFNoC Config
  

  
FPGA Module Name
fpga_module_name
noc_block_combiner
string
all
RFNoC Config
  

  
Force Vector Length
grvlen
1
int
  

  
Device Format
otw
enum

  Complex int16
  sc16


  Complex int8
  sc8


  Byte
  u8

  

  
  
in0
complex
$grvlen
rfnoc
  
  
in1
complex
$grvlen
rfnoc
  
  
  
out
complex
$grvlen
rfnoc
  

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Re: [USRP-users] ADC Self-Test FAILED

2017-10-11 Thread Mark Koenig via USRP-users

Thank you for the follow up.  Is this the only resolution?

Thank you


Mark

From: Michael West 
Date: Tuesday, October 10, 2017 at 4:00 PM
To: Mark Koenig 
Cc: "usrp-users@lists.ettus.com" 
Subject: Re: [USRP-users] ADC Self-Test FAILED

Hi Mark,
Update UHD to a newer version.  The head of the maint branch or the latest 
3.10.2.0 release should work.  The ADC self test is skipped when supplying 
"recover_mb_eeprom" as of UHD 3.10.0.0.
Regards,
Michael

On Tue, Oct 10, 2017 at 12:32 PM, Mark Koenig via USRP-users 
> wrote:
Just following up on the message I sent out 8 days ago.  Does anyone have any 
resolution to this issue?  I have seen other people have the problem, but have 
yet to find a fix.

Thanks

Mark

From: Mark Koenig 
>
Date: Monday, October 2, 2017 at 10:18 AM
To: "usrp-users@lists.ettus.com" 
>
Subject: ADC Self-Test FAILED

All,


I am getting the following output when trying to recover the mb EEprom.  Can 
anyone be of assistance?

Thank you

Mark


[root@localhost utils]# ./usrp_burn_mb_eeprom 
--args="recover_mb_eeprom,addr=192.168.20.2" --values="revision=4"
linux; GNU C++ version 4.8.5 20150623 (Red Hat 4.8.5-16); Boost_105300; 
UHD_003.009.000-0-gcd88f80f

Creating USRP device from address: recover_mb_eeprom,addr=192.168.20.2
-- X300 initialization sequence...
-- Determining maximum frame size... 1472 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...

UHD Warning:
UHD is operating in EEPROM Recovery Mode which disables hardware version 
checks.
Operating in this mode may cause hardware damage and unstable radio 
performance!
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- Detecting internal GPSDO Found an internal GPSDO
-- Initialize Radio0 control...
-- Performing register loopback test... pass
-- Initialize Radio1 control...
-- Performing register loopback test... pass
Error: RuntimeError: ADC self-test failed! Ramp checker status: {ADC0_I=Bit 
Errors!, ADC0_Q=Good, ADC1_I=Good, ADC1_Q=Good}


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Re: [USRP-users] Help to configure/install PCI-Express Connectivity Kit for X310

2017-10-11 Thread Neel Pandeya via USRP-users

Hello Daniele Disco:

Unfortunately, at this time, the kernel driver for the PCIe Kit only
supports up to kernel 4.2, and you are using kernel 4.10. Would you be able
to downgrade you kernel, perhaps by using Ubuntu 14.04? We are working to
add support for newer kernels to the PCIe driver, but I don't yet have a
date for when that will be available.

--Neel Pandeya





On 11 October 2017 at 07:39, Disco Daniele via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi!
>
> With the X310 we have also taken the PCI-Express Connectivity Kit.
>
>
>
> Following the instruction reported here (http://files.ettus.com/
> manual/page_usrp_x3x0.html#x3x0_hw)
>
> And going in the section : PCI Express (Desktop) that send to
> http://files.ettus.com/manual/page_ni_rio_kernel.html
>
> Downloading the http://files.ettus.com/binaries/niusrprio/niusrprio-
> installer-15.0.0.tar.gz
>
> And executing the command: sudo niusrprio-installer/INSTALL
>
> The procedure install all. Then in the post installation occurs a lot of
> errors.
>
> You can find in the attached file the log of all the procedure.
>
> Than with the X310 switched on, re-run the same command, there are a lot
> of skip instruction and at the end it looks like the installation is
> finished with success.
>
> Try to execute the command
>
> sudo /usr/local/bin/niusrprio_pcie start
>
> it declare unable to insert ‘NiRioSrv’ so following the procedure suggested
>
> sudo /usr/local/bin/niusrprio_pcie stop
>
> sudo /usr/local/bin/updateNIDrivers --no-prompt
>
> I obtain a lot of error message that I report in the second attached file
> error2.txt
>
> Please, could you help me to solve this issue?
>
> Thank you in advance
>
> Daniele
>
>
>
> PS: The system is Ubuntu 16.04 LTS
>
> uname –a:
>
> Linux nomeHost 4.10.0-37-generic #41~16.04.1-Ubuntu SMP Fri Oct 6 22:42:59
> UTC 2017 x86_64 x86_64 x86_64 GNU/Linux
>
> UHD info:
>
> [Info] [UHDlinux; GNU C++ version 5.4.0 20160609; Boost_105800;
> UHD_3.11.0.git-0-unknow]
>
>
>
>
>
>
>
> _
>
> [image: logo1]
> *Daniele Disco*
> Engeenering & Tilab – Wireless Access
> Wireless Innovation
> Via Reiss Romoli, 274 – 10148 Torino
> tel . +39 011 228 7271 <+39%20011%20228%207271>
> cell. +39 331 600 1113 <+39%20331%20600%201113>
>
> Fax. +39 06 4186 5196 <+39%2006%204186%205196>
> Tim Official: *Facebook*  -
> *Twitter* 
> *www.tim.it* 
>
>
> Questo messaggio e i suoi allegati sono indirizzati esclusivamente alle
> persone indicate. La diffusione, copia o qualsiasi altra azione derivante
> dalla conoscenza di queste informazioni sono rigorosamente vietate. Qualora
> abbiate ricevuto questo documento per errore siete cortesemente pregati di
> darne immediata comunicazione al mittente e di provvedere alla sua
> distruzione, Grazie.
>
> * This e-mail and any attachments is confidential and may contain
> privileged information intended for the addressee(s) only. Dissemination,
> copying, printing or use by anybody else is unauthorised. If you are not
> the intended recipient, please delete this message and any attachments and
> advise the sender by return e-mail, Thanks. *
>
> *Rispetta l'ambiente. Non stampare questa mail se non è necessario.*
>
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>
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[USRP-users] Help to configure/install PCI-Express Connectivity Kit for X310

2017-10-11 Thread Disco Daniele via USRP-users

Hi!
With the X310 we have also taken the PCI-Express Connectivity Kit.

Following the instruction reported here 
(http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw)
And going in the section : PCI Express (Desktop) that send to 
http://files.ettus.com/manual/page_ni_rio_kernel.html
Downloading the 
http://files.ettus.com/binaries/niusrprio/niusrprio-installer-15.0.0.tar.gz
And executing the command: sudo niusrprio-installer/INSTALL
The procedure install all. Then in the post installation occurs a lot of errors.
You can find in the attached file the log of all the procedure.
Than with the X310 switched on, re-run the same command, there are a lot of 
skip instruction and at the end it looks like the installation is finished with 
success.
Try to execute the command
sudo /usr/local/bin/niusrprio_pcie start
it declare unable to insert 'NiRioSrv' so following the procedure suggested
sudo /usr/local/bin/niusrprio_pcie stop
sudo /usr/local/bin/updateNIDrivers --no-prompt
I obtain a lot of error message that I report in the second attached file 
error2.txt
Please, could you help me to solve this issue?
Thank you in advance
Daniele

PS: The system is Ubuntu 16.04 LTS
uname -a:
Linux nomeHost 4.10.0-37-generic #41~16.04.1-Ubuntu SMP Fri Oct 6 22:42:59 UTC 
2017 x86_64 x86_64 x86_64 GNU/Linux
UHD info:
[Info] [UHDlinux; GNU C++ version 5.4.0 20160609; Boost_105800; 
UHD_3.11.0.git-0-unknow]



_
[logo1]
Daniele Disco
Engeenering & Tilab - Wireless Access
Wireless Innovation
Via Reiss Romoli, 274 - 10148 Torino
tel . +39 011 228 7271
cell. +39 331 600 1113
Fax. +39 06 4186 5196
Tim Official: Facebook - 
Twitter
www.tim.it


Questo messaggio e i suoi allegati sono indirizzati esclusivamente alle persone 
indicate. La diffusione, copia o qualsiasi altra azione derivante dalla 
conoscenza di queste informazioni sono rigorosamente vietate. Qualora abbiate 
ricevuto questo documento per errore siete cortesemente pregati di darne 
immediata comunicazione al mittente e di provvedere alla sua distruzione, 
Grazie.

This e-mail and any attachments is confidential and may contain privileged 
information intended for the addressee(s) only. Dissemination, copying, 
printing or use by anybody else is unauthorised. If you are not the intended 
recipient, please delete this message and any attachments and advise the sender 
by return e-mail, Thanks.

Rispetta l'ambiente. Non stampare questa mail se non è necessario.
$> sudo niusrprio-installer/INSTALL

*
  NI USRP RIO distribution installer
 version 15.0.0f0 for Linux
*

National Instruments products support the following Linux distributions:
   openSUSE
   Red Hat Enterprise Linux Desktop + Workstation
   Fedora
   Scientific Linux
   Debian
   Ubuntu
Refer to README.txt for the latest information at the time of release.
Refer to www.ni.com/linux for the most recent information about Linux
support at National Instruments.

Continue? [Yn] 

Checking required install tools...
Checking installer tool versions...
dpkg found
rpmNot found in current path
tar1.28
Checking dependencies...
glibc  2.23 
Unpacking install files to /tmp/niusrpriodistributioni-15.0.0f0.install...

NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT (LINUX DRIVER SOFTWARE)


INSTALLATION NOTICE: THIS IS A CONTRACT. BEFORE YOU DOWNLOAD THE SOFTWARE AND/OR
COMPLETE THE INSTALLATION PROCESS, CAREFULLY READ THIS AGREEMENT. BY DOWNLOADING
THE SOFTWARE AND/OR ENTERING 'y' TO COMPLETE THE INSTALLATION PROCESS, YOU
CONSENT TO THE TERMS OF THIS AGREEMENT AND YOU AGREE TO BE BOUND BY THIS
AGREEMENT. IF YOU DO NOT WISH TO BECOME A PARTY TO THIS AGREEMENT AND BE BOUND
BY ALL OF ITS TERMS AND CONDITIONS, ENTER 'n' OR 'q' TO CANCEL THE INSTALLATION
PROCESS, DO NOT INSTALL OR USE THE SOFTWARE, AND RETURN THE SOFTWARE (INCLUDING,
IF APPLICABLE, ALL ACCOMPANYING WRITTEN MATERIALS, ALONG WITH THEIR CONTAINERS)
WITHIN THIRTY (30) DAYS OF RECEIPT OF THE SOFTWARE TO THE PLACE YOU OBTAINED
THEM. ALL RETURNS SHALL BE SUBJECT TO NI'S THEN CURRENT RETURN POLICY.


1. Definitions. As used in this Agreement, the following terms have the
following meanings:

A. "You." Means you the individual using the SOFTWARE as well as your employer
if you are using the SOFTWARE within the scope of your employment. If you are 
using the SOFTWARE within the scope of your employment, then you represent that
you are authorized to bind your employer to this Agreement.

B. "NI." Means National Instruments Corporation, a company organized under the 
laws of the State of Delaware, U.S.A., unless the SOFTWARE is manufactured in 
the Republic of Ireland, in which event, "NI" shall mean National Instruments 
Ireland Resources Ltd., a company

[USRP-users] IQ samples being lost when using SOB/EOB

2017-10-11 Thread Felipe Augusto Pereira de Figueiredo via USRP-users

Dear All,

I'm sending OFDM frames in a bursty manner, i.e., a have slots of 1 ms with
14 OFDM symbols.

These 1 ms slots are transmitted from time to time and I'm using SOB and
EOB to make it a busrty transmission.

What I have noticed is that some samples at the beginning of the slot are
being missed somehow. In order to solve it I had to pad 1000 zero IQ
samples to the beginning of the slot, only after that I started receiving
the slots correctly, however, now I have lots of "U" characters being
printed on the screen.

Is there some issue with the current UHD (host source or FPGA source) that
might be causing that problem?

I have tried with different UHD versions and the issue happen with all of
them:

- UHD_003.009.005-0-unknown
- UHD_003.010.002.000-3-g122bfae1
- UHD_4.0.0.rfnoc-devel-369-g1908672f

Could you guys, please, help me understand/solve this problem?

Many thanks and Kind Regards,

Felipe Augusto
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Re: [USRP-users] RFNOC complex_multiplier not found

2017-10-11 Thread Nicolas Cuervo via USRP-users

Hello Kau-Uwe,

You have to point your Makefile where the IP is located so that it can
build it for simulation. You can base this on the Makefile for the FIR
filter, for example [1], where the IP specific settings are introduced.

In your specific use case, it should be something like:

#-
# IP Specific
#-
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory

IP_DIR = $(BASE_DIR)/x300/ip

# Include makefiles and sources for all IP components
# *after* defining the IP_DIR

include $(LIB_IP_DIR)/complex_multiplier/Makefile.inc
DESIGN_SRCS += $(abspath \
$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \
)


Regards,
- Nicolas

[1]
> https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/noc_block_fft_tb/Makefile#L14
>


On Wed, Oct 11, 2017 at 9:47 AM, Kai-Uwe Storek via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hey,
>
> if I use an instantiation of rfnoc-devel/usrp3/lib/rfnoc/cmul.v in my
> design, the compilation / elaboration process (make
> noc_block_myblock_tb) fails with:
>
> ERROR: [VRFC 10-2063] Module  not found while
> processing module instance 
> [/home/labor/gr_prefixes/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cmul.v:13]
> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design
> unit(s) in library work failed.
>
>
> As far as I can see the usrp3/lib/ip/Makefile.inc is correct, but it
> seems that this inc-File is untouched / unused.
>
> Can some point me in the right direction how to make
> "complex_multiplier" discoverable for the "make noc_block_myblock_tb"
> command?
>
> Thanks!
> Kai
>
>
>
> The instantiation snippet of my custom block is:
>
>   generate
>cmul inst_cmul (
> .clk(ce_clk), .reset(ce_rst),
> .a_tdata(in_tdata[0]), .a_tlast(in_tlast[0]),
> .a_tvalid(in_tvalid[0]), .a_tready(in_tready[0]),
> .b_tdata(in_tdata[1]), .b_tlast(in_tlast[1]),
> .b_tvalid(in_tvalid[1]), .b_tready(in_tready[1]),
> .o_tdata(out_tdata[0]), .o_tlast(out_tlast[0]),
> .o_tvalid(out_tvalid[0]), .o_tready(out_tready[0]));
>   endgenerate
>
> and without this snippet the testbench runs without any problem.
>
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Re: [USRP-users] additional Verilog file in OOT RFNoC block

2017-10-11 Thread Nicolas Cuervo via USRP-users

Hello Dixon,

Daniel's suggestion works, but that would mean adding a hard-coded path
into the fpga build system. It does the trick, but it is not recommended.

The OOT module has its own Makefile.srcs that intends to contain all the
HDL code that is required for the module. The procedure is the same: just
add the multTest.v file in the Makefile.srcs located at
your_oot_module/rfnoc/fpga/, as follows (assuming it is located in the same
directory as the noc_block_* file):

$(addprefix SOURCES_PATH, \
> noc_block_your_block.v \
>
*multTest.v \*

) \
>

Don't forget to add the trailing "\".

For simulation in the testbench, the procedure is basically the same. In
the rfnoc/testbenches/noc_block_your_bloc_tb/ directory, there is a
Makefile that would need to have explicit access to that new module in
order to work. You just add the file name below the noc_block:


> SIM_SRCS = \
> $(abspath noc_block_yourblock_tb.sv) \
> $(abspath ../../fpga-src/noc_block_yourblock.v) \
> *$(abspath ../../fpga-src/multTest.v) \*


Please let us know if you are still facing issues with this.

Regards,
- Nicolas

On Wed, Oct 11, 2017 at 8:15 AM, Daniel Rauschen via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi Jim,
>
> try to add the file multTest.v (with the complete absolute path) in the
> Makefile.srcs located at .../uhd/fpga-src/usrp3/top/x300/.
> At least this worked for me.
>
> Best regards,
>
> Daniel
>
>
>
> On 11.10.2017 03:45, Dixon, James L via USRP-users wrote:
>
> Hi,
>
> I am trying to figure out how to add additional Verilog code in a separate
> .v file and have it build.  For a simple proof-of-concept test, I started
> with the "tutorial" module and the "gain" block, as per the instructions in
> the "Getting Started" document.  I then substituted this code in the
> noc_block_gain.v file:
>
> Instead of:
> wire [31:0] i_mult_gain = i * gain;
> wire [31:0] q_mult_gain = q * gain;
>
> I put this:
> wire [31:0] i_mult_gain;
> wire [31:0] q_mult_gain;
>
> multTest mult1 (
> .i(i),
> .q(q),
> .gain(gain),
> .iout(i_mult_gain),
> .qout(q_mult_gain) );
>
> And then at the end of the noc_block_gain.v file, I added this:
>
> module multTest(i, q, gain, iout, qout);
> input [15:0] i;
> input [15:0] q;
> input [15:0] gain;
> output [31:0] iout;
> output [31:0] qout;
>
> assign iout = i * gain;
> assign qout = q * gain;
> endmodule
>
> This builds fine.  However, I would like to put the multTest module code
> in a separate .v file.  I tried just putting it in a file called multTest.v
> in the same directory as the noc_block_gain.v file, but I get an error that
> the module "multTest" can't be found.  As I mentioned, this is just a
> simple test and my real goal is to put a significant amount of code into
> the additional Verilog file, and to eventually use an additional VHDL file.
>
> Any ideas?  I'm guessing that there may be some additional steps.
>
> Thanks,
>
> Jim
>
>
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[USRP-users] RFNOC complex_multiplier not found

2017-10-11 Thread Kai-Uwe Storek via USRP-users

Hey,

if I use an instantiation of rfnoc-devel/usrp3/lib/rfnoc/cmul.v in my
design, the compilation / elaboration process (make
noc_block_myblock_tb) fails with:

ERROR: [VRFC 10-2063] Module  not found while
processing module instance 
[/home/labor/gr_prefixes/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cmul.v:13]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design
unit(s) in library work failed.


As far as I can see the usrp3/lib/ip/Makefile.inc is correct, but it
seems that this inc-File is untouched / unused.

Can some point me in the right direction how to make
"complex_multiplier" discoverable for the "make noc_block_myblock_tb"
command?

Thanks!
Kai



The instantiation snippet of my custom block is:

  generate
   cmul inst_cmul (
.clk(ce_clk), .reset(ce_rst),
.a_tdata(in_tdata[0]), .a_tlast(in_tlast[0]),
.a_tvalid(in_tvalid[0]), .a_tready(in_tready[0]),
.b_tdata(in_tdata[1]), .b_tlast(in_tlast[1]),
.b_tvalid(in_tvalid[1]), .b_tready(in_tready[1]),
.o_tdata(out_tdata[0]), .o_tlast(out_tlast[0]),
.o_tvalid(out_tvalid[0]), .o_tready(out_tready[0]));
  endgenerate

and without this snippet the testbench runs without any problem.

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Re: [USRP-users] RFNOC x300 Rx/Tx loopback

2017-10-11 Thread Daniel Rauschen via USRP-users


Update...

I figured it out. The conversation "Re: [USRP-users] GRC + RFNoC + Radio 
Loopback" was kind of helpful.





On 04.10.2017 11:29, Daniel Rauschen via USRP-users wrote:


Hi,

I am trying to do a Rx / Tx loopback test and I am stuck for days with it.

For the sake of simplicity I altered the gain example [1] with the 
approach 3 from [2] (find my noc_block_gain.v and the test bench 
attached).


I connect the blocks like this (UHD):

*rx_graph->connect(m_radio_ctrl->get_block_id(),0, 
split_ctrl->get_block_id(),0,1024);
rx_graph->connect(split_ctrl->get_block_id(),0, 
fifo_ctrl->get_block_id(),0,***1024*);
rx_graph->connect(split_ctrl->get_block_id(),1, 
gain_ctrl->get_block_id(),0,***1024*);
rx_graph->connect(gain_ctrl->get_block_id(),0, 
dma_fifo_ctrl->get_block_id(),0,***1024*);

rx_graph->connect(dma_fifo_ctrl->get_block_id(),0,m_radio_ctrl->get_block_id(),1,***1024*);*

Which is some how wrong, because I get following error when running 
the programm:*

*

*[32;1m[INFO] [UHDlinux; GNU C++ version 5.4.0 20160609; Boost_105800; 
UHD_4.0.0.rfnoc-devel-369-g1908672f] [39;0m**

**[32;1m[INFO] [X300] [39;0mX300 initialization sequence...**
**[32;1m[INFO] [X300] [39;0mDetermining maximum frame size... **
**[32;1m[INFO] [X300] [39;0mMaximum frame size: 8000 bytes.**
**[32;1m[INFO] [X300] [39;0mSetup basic communication...**
**[32;1m[INFO] [X300] [39;0mLoading values from EEPROM...**
**[32;1m[INFO] [X300] [39;0mSetup RF frontend clocking...**
**[32;1m[INFO] [X300] [39;0mRadio 1x clock:120**
**[32;1m[INFO] [X300] [39;0mDetecting internal GPSDO **
**[32;1m[INFO] [GPS] [39;0mNo GPSDO found**
**[32;1m[INFO] [RFNOC] [39;0m[DMA FIFO] Running BIST for FIFO 0... **
**[32;1m[INFO] [RFNOC] [39;0mpass (Throughput: 1302.6MB/s)**
**[32;1m[INFO] [RFNOC] [39;0m[DMA FIFO] Running BIST for FIFO 1... **
**[32;1m[INFO] [RFNOC] [39;0mpass (Throughput: 1296.1MB/s)**
**[32;1m[INFO] [RFNOC RADIO] [39;0mRegister loopback test passed**
**[32;1m[INFO] [RFNOC RADIO] [39;0mRegister loopback test passed**
**[32;1m[INFO] [RFNOC RADIO] [39;0mRegister loopback test passed**
**[32;1m[INFO] [RFNOC RADIO] [39;0mRegister loopback test passed**
**[33;1m[WARNING] [RFNOC] [39;0m[0/SplitStream_0] defines 2 input 
buffer sizes, but 1 input ports**

**[32;1m[INFO] [CORES] [39;0mPerforming timer loopback test... **
**[32;1m[INFO] [CORES] [39;0mTimer loopback test passed**
**[32;1m[INFO] [CORES] [39;0mPerforming timer loopback test... **
**[32;1m[INFO] [CORES] [39;0mTimer loopback test passed**
**
****
**
**Radio0 Params:**
**Device Address:**
**    spp: 1024**
**
****
**
**SplitStream Params:**
**Empty Device Address**
****
**
**FIFO Params:**
**Empty Device Address**
****
**
**DmaFIFO Params:**
**Device Address:**
**    base_addr: 0**
**    depth: 65536**
**
****
**
**gain Params:**
**Device Address:**
**    gain: 10**
**    delaytime: 3600**
**
****
**Setting RX Freq: 2450.00 MHz...**
**Actual RX Freq: 2450.00 MHz...**
**
**Actual TX Freq: 2450.00 MHz...**
**
**Actual RX Gain: 0.00 dB...**
**
**Actual TX Gain: 0.00 dB...**
**
**Connecting blocks...**
**terminate called after throwing an instance of 'uhd::runtime_error'**
**  what():  RuntimeError: Input FIFO for block 0/Radio_0 is too small 
(0 kiB) for packets of size 1 kiB**

**coming from block 0/DmaFIFO_0.**
*

Is there anyone who did a Rx/Tx loop with a similar flow graph as 
shown in grc_block.png?


What am I doing wrong?

Best regards,

Daniel


[1] https://kb.ettus.com/Getting_Started_with_RFNoC_Development

[2] https://corvid.io/2017/04/22/stupid-rfnoc-tricks-loopback/

--

M.Sc. Daniel Rauschen

Communication Systems

  


Fraunhofer Institute for Communication, Information Processing and Ergonomics 
FKIE

Fraunhoferstr. 20 | 53343 Wachtberg | Germany

Phone +49 (0)228 9435-404

mailto:daniel.rausc...@fkie.fraunhofer.de

http://www.fkie.fraunhofer.de


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Re: [USRP-users] additional Verilog file in OOT RFNoC block

2017-10-11 Thread Daniel Rauschen via USRP-users


Hi Jim,

try to add the file multTest.v (with the complete absolute path) in the 
Makefile.srcs located at .../uhd/fpga-src/usrp3/top/x300/.

At least this worked for me.

Best regards,

Daniel


On 11.10.2017 03:45, Dixon, James L via USRP-users wrote:

Hi,

I am trying to figure out how to add additional Verilog code in a 
separate .v file and have it build.  For a simple proof-of-concept 
test, I started with the "tutorial" module and the "gain" block, as 
per the instructions in the "Getting Started" document.  I then 
substituted this code in the noc_block_gain.v file:


Instead of:
wire [31:0] i_mult_gain = i * gain;
wire [31:0] q_mult_gain = q * gain;

I put this:
wire [31:0] i_mult_gain;
wire [31:0] q_mult_gain;

multTest mult1 (
.i(i),
.q(q),
.gain(gain),
.iout(i_mult_gain),
.qout(q_mult_gain) );

And then at the end of the noc_block_gain.v file, I added this:

module multTest(i, q, gain, iout, qout);
input [15:0] i;
input [15:0] q;
input [15:0] gain;
output [31:0] iout;
output [31:0] qout;

assign iout = i * gain;
assign qout = q * gain;
endmodule

This builds fine.  However, I would like to put the multTest module 
code in a separate .v file.  I tried just putting it in a file called 
multTest.v in the same directory as the noc_block_gain.v file, but I 
get an error that the module "multTest" can't be found.  As I 
mentioned, this is just a simple test and my real goal is to put a 
significant amount of code into the additional Verilog file, and to 
eventually use an additional VHDL file.


Any ideas?  I'm guessing that there may be some additional steps.

Thanks,

Jim


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Re: [USRP-users] RFNOC x300 Rx/Tx loopback

Re: [USRP-users] additional Verilog file in OOT RFNoC block

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