Re: [USRP-users] External LO amplitude issue
Are you plotting a absolute magnitude or just the magnitude in real/imag axis ? If this is the magnitude for real or imag signal alone, then the result makes sense. Since the cable length and several factors will result in different projection value of the total magnitude in each real and imag axis. The amplitude is only the same for the absolute magnitude. On Fri, Sep 28, 2018 at 10:18 AM Yun Li via USRP-users < usrp-users@lists.ettus.com> wrote: > I tried increasing LO power by 1dB and 2dB and 3dB. No noticable > difference. What is interesting is channel 2 and 3 are from same dboard. > But they are the ones that differ the most. > > Yun > > Marcus D. Leech via USRP-users 于2018年9月28日周五 > 下午12:58写道： > >> On 09/28/2018 12:45 PM, Yun Li via USRP-users wrote: >> >> Hi there, >> >> I am testing external LO on N310 (UHD_3.13.0.2-1-g78745bda). The setup is >> I have a X310 sending SINE waves to N310's channel 1,2,3 via a splitter. A >> signal generator sends 2x frequency 3dBm signal to N310's LO IN 0/1 and LO >> IN 2/3 via a splitter. According to the doc, there is supposed to be a 180 >> degree phase shift which I did observe in following plot. >> >> [image: image.png] >> >> But the question is why all 3 channels are now having very different >> amplitude. If I use internal LO, the amplitude of all 3 channels are the >> same. >> >> Thanks. >> Yun >> >> What happens if you increase the LO power by 1dB or so? >> >> >> >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Coherent receiver configuration failure for two X310 equipped with 4 TwinRx
Actually, I do consider to try that. I have RF splitter which can take channel 1 as main LO for channel 5,6,7,8 so I can configure them by using external LO without warranty-voiding hardware mods. By using semi-rigid cable with fixed shape (i.e attach cables with some board to fix the shape), it should be able to maintain constant phase delay from cable issues. Those setup hopefully can maintain constant phase difference for one-time calibration purposes. I will update my results, if I decide to try this approach On Fri, Sep 14, 2018 at 6:06 AM Rob Kossler wrote: > Is it possible to run two LO cables out of channel 4 and into channel 5 > such that channel 5 & 6 should be configured as "external" rather than as > "internal/companion"? I realize that there is no external RF connector to > support the cables passing from USRP 1 to USRP 2, so you would have to > figure out how you would want to do that. > > Rob > > > On Thu, Sep 13, 2018 at 10:48 PM Marcus D. Leech via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> On 09/13/2018 10:12 PM, Jack Yang wrote: >> >> Hi Marcus, >> >> Thanks for the prompt reply. I have two questions. First, I remember I >> can align phase across multiple USRPs when using UBX-160 daughterboards >> (i.e 4 USRPs equipped with 8 UBX-160 for 8 phase-array receivers.). Just to >> double confirm that I cannot use the UBX-160 time configuration approach to >> align phase for TwinRx across two USRPs, right? Since TwinRxs >> use superheterodyne structure, the time setting configuration for phase >> alignment (which work for UBX-160) will not work for the TwinRx due to the >> second stage down-conversion having it's own LO and this LO is not able to >> access from the other USRP. Is my understanding correct? >> >> That is correct, as far as I understand the architecture of the TwinRX. >> >> >> My second questions is that do you know any approach which can have self >> calibration for each run? If I use two port RF splitter to connect Rx4 in >> the first USRP and Rx5 in the second USRP for the same antenna as input, >> ideally I can use the Rx4 & Rx5 phase difference to compensate other three >> receivers in the second USRP. Then, I can still set up a 7 receivers for >> coherent receivers, right? >> >> The usual approach is "measure and correct". This works well if you have: >> >> (A) A calibration source you can turn on that is visible to all inputs >> and of equal phase delay >> >> or >> >> (B) You have some continuous, but distant, signal source that is "seen" >> by all your receivers >> >> or >> >> (C) Other schemes that achieve the same thing >> >> The key is that you have to measure the phase delays and compensate. >> >> >> >> Really thanks for your time to answer my questions! >> >> All Best, >> Jack >> >> >> >> On Thu, Sep 13, 2018 at 6:20 PM Marcus D. Leech via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> On 09/13/2018 08:52 PM, Jack Yang via USRP-users wrote: >>> > Hi, >>> > >>> > I am trying to set up a 8 channels coherent receiver where I am using >>> > two X310 and each X310 is equipped with two TwinRx. However, the phase >>> > alignment across two USRP are always failed. The two X310 are using >>> > the OctoClock-G to have 1M PPS and 10MHz clock. Then, I am using a >>> > individual transmitter which can generate single tone with RF splitter >>> > to connect to the 8 channels via RF coaxial cable. My GNURadio >>> > configuration is shown as below the link ( >>> > https://www.dropbox.com/s/du15rakg1nacmql/DualX310_8Rec_v1.py?dl=0 ). >>> > Alternatively, one can also see the below summary configuration. I >>> > can have constant phase difference within the same USRP when I power >>> > on and off for different trials, while the phase difference across two >>> > USRP are always varying for each trial (i.e The phase difference >>> > between Ch4 in first USRP and Ch5 in second USRP is not constant among >>> > different runs). The below links refer to the results for two >>> > different trials. In first trials, all the phase difference is shifted >>> > based on itself mean value (First run, >>> > https://www.dropbox.com/s/z8so39bejzdofi8/Run1.png?dl=0 ). Then, >>> using >>> > the first-run average phase difference to compensate the phase >>> > difference in the second run (Seco
Re: [USRP-users] Coherent receiver configuration failure for two X310 equipped with 4 TwinRx
Hi Marcus, Thanks for the prompt reply. I have two questions. First, I remember I can align phase across multiple USRPs when using UBX-160 daughterboards (i.e 4 USRPs equipped with 8 UBX-160 for 8 phase-array receivers.). Just to double confirm that I cannot use the UBX-160 time configuration approach to align phase for TwinRx across two USRPs, right? Since TwinRxs use superheterodyne structure, the time setting configuration for phase alignment (which work for UBX-160) will not work for the TwinRx due to the second stage down-conversion having it's own LO and this LO is not able to access from the other USRP. Is my understanding correct? My second questions is that do you know any approach which can have self calibration for each run? If I use two port RF splitter to connect Rx4 in the first USRP and Rx5 in the second USRP for the same antenna as input, ideally I can use the Rx4 & Rx5 phase difference to compensate other three receivers in the second USRP. Then, I can still set up a 7 receivers for coherent receivers, right? Really thanks for your time to answer my questions! All Best, Jack On Thu, Sep 13, 2018 at 6:20 PM Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> wrote: > On 09/13/2018 08:52 PM, Jack Yang via USRP-users wrote: > > Hi, > > > > I am trying to set up a 8 channels coherent receiver where I am using > > two X310 and each X310 is equipped with two TwinRx. However, the phase > > alignment across two USRP are always failed. The two X310 are using > > the OctoClock-G to have 1M PPS and 10MHz clock. Then, I am using a > > individual transmitter which can generate single tone with RF splitter > > to connect to the 8 channels via RF coaxial cable. My GNURadio > > configuration is shown as below the link ( > > https://www.dropbox.com/s/du15rakg1nacmql/DualX310_8Rec_v1.py?dl=0 ). > > Alternatively, one can also see the below summary configuration. I > > can have constant phase difference within the same USRP when I power > > on and off for different trials, while the phase difference across two > > USRP are always varying for each trial (i.e The phase difference > > between Ch4 in first USRP and Ch5 in second USRP is not constant among > > different runs). The below links refer to the results for two > > different trials. In first trials, all the phase difference is shifted > > based on itself mean value (First run, > > https://www.dropbox.com/s/z8so39bejzdofi8/Run1.png?dl=0 ). Then, using > > the first-run average phase difference to compensate the phase > > difference in the second run (Second run, > > https://www.dropbox.com/s/xhkmp6cuxzwylvx/Run2.png?dl=0 ). As the > > result shown in the second run, the phase difference across Rx5 and > > Rx3 has been shifted to -214 degrees while all the other phase > > difference within itself USRP are still the same as the previous > > measurement. Could someone let me know how I can configure two USRP > > X310 with TwinRx for the coherent receivers? > > > > Many thanks for the help! > > > > All Best, > > Jack > > > So in the first USRP, your TwinRx is configured to share the LO from the > first channel to the other 3 channels. The only phase-offset compensation >you'll need to do is fixed, and is dominated just by the length of > the cables within the enclosure that are used to share LOs. > > However, in the second USRP, THAT LO is independent from the one on the > first X310, even though it uses a common phase reference >(the 10MHz shared between the two). What this means is that the two > USRPs won't drift relative to one another, but there will be >some unknown phase offset between them, due to the way that RF > synthesizers work--you have two synthesizers (one in the first USRP >on one of the TwinRX cards), and the other in the second. They won't > agree on startup phase, except "by accident". You'll have to resolve >this using a calibration procedure. There's really no way around > that with this type of architecture. > > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Time alignment failure for four channels coherent receiver in X310
Thank you so much!! Julian! Starting the RX streamer a little bit in the future works!! Now I can align 4 channels as coherent receiver with 50M sps without problem. Also thanks for Marcus's help All Best, Jack On Sun, Jul 29, 2018 at 12:49 PM, Julian Arnold wrote: > Hey, > > have you tried starting the RX streamer a little bit in the future, i.e > change the following lines: > > stream_cmd.stream_now = true; > stream_cmd.time_spec = uhd::time_spec_t(); > > to something like (out of the top of my head): > > stream_cmd.stream_now = false; > stream_cmd.time_spec = usrp->get_time_now() + 0.05; > > ? > > I have seen the same behavior on my B210 in dual channel RX setups when > starting the streamer immediately. So maybe this helps. > > Cheers, > Julian > > On 29.07.2018 21:23, Jack Yang via USRP-users wrote: > >> Hi Marcus, >> >> Even I used 1Msps or less than this sampling rate, I still saw this time >> alignment issue. When I am using GNURadio system with python script instead >> of using UHD API, I can run 10Msps for my 4 channel phase array receiver >> without any problems. My final goal is to have 50Msps for my 4 channel >> phase array receiver with dual 10 GiGe cable setup and CDUA computation for >> wideband AoA detection. My desktop spec is Processors: Intel Core i9 7900X >> 10-Core 3.3GHz (4.3GHz TurboBoost), Memory: 32GB ORIGIN PC DDR4 Powered by >> Kingston 3000MHz (4 X 8GB),. >> >> Thanks! >> >> All Best, >> Jack >> >> >> >> >> >> >> On Sun, Jul 29, 2018 at 11:59 AM, Marcus D. Leech > <mailto:mle...@ripnet.com>> wrote: >> >> On 07/29/2018 12:56 PM, Jack Yang wrote: >> >>> Hi Marcus, >>> >>> Thanks for your mail. Yes, I am using 10GiGe interface to run the >>> UHD C++ code. >>> Any thoughts or suggestions? >>> >>> All Best, >>> Jack >>> >>> On Sun, Jul 29, 2018 at 9:35 AM, Marcus D. Leech via USRP-users >>> mailto:usrp-users@lists.ettus.com>> >>> wrote: >>> >>> On 07/29/2018 12:52 AM, Jack Yang via USRP-users wrote: >>> >>>> Hi, >>>> >>>> I have rewrote "rx_samples_to_file.cpp" for making four >>>> channel coherent receiver (phased-array receiver) in X310. >>>> When I executed my code, the terminal showed that >>>> >>>> *[ERROR] [STREAMER] The receive packet handler failed to >>>> time-align packets. 1002 received packets were processed by >>>> the handler. However, a timestamp match could not be >>>> determined.* >>>> >>>> I have attached my code as the following link >>>> (https://www.dropbox.com/s/x0u0tw5e65iaual/rx_samples_X310_ >>>> TwinRx.cpp?dl=0 >>>> <https://www.dropbox.com/s/x0u0tw5e65iaual/rx_samples_X310_ >>>> TwinRx.cpp?dl=0>). >>>> The info for my UHD version is shown in below >>>> *"[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; >>>> Boost_105800; UHD_3.11.0.HEAD-0-ga1b5c4ae"* >>>> >>>> >>>> Could someone guide me how to fix this issue? I am using two >>>> TwinRx with a X310 for my coherent receiver. I basically >>>> followed gr-doa python configuration to set up the USRP >>>> device in C++ code. However, I cannot find out why the time >>>> alignment is failed in here. >>>> >>>> The detailed print-out message is also listed here >>>> >>>> Thanks! >>>> >>>> All Best, >>>> Jack >>>> >>>> Creating the usrp device with: addr=192.168.40.2... >>>> [INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; >>>> Boost_105800; UHD_3.11.0.HEAD-0-ga1b5c4ae >>>> [INFO] [X300] X300 initialization sequence... >>>> [INFO] [X300] Determining maximum frame size... >>>> [INFO] [X300] Maximum frame size: 8000 bytes. >>>> [INFO] [X300] Setup basic communication... >>>> [INFO] [X300] Loading values from EEPROM... >>>> [INFO] [X300] Setup RF frontend clocking... >>>> [INFO] [X300] Radio 1x clock:200 >>>> [INFO] [RFNOC DMA FIFO] Running BIST for FIFO 0...
Re: [USRP-users] Time alignment failure for four channels coherent receiver in X310
Hi Marcus, Even I used 1Msps or less than this sampling rate, I still saw this time alignment issue. When I am using GNURadio system with python script instead of using UHD API, I can run 10Msps for my 4 channel phase array receiver without any problems. My final goal is to have 50Msps for my 4 channel phase array receiver with dual 10 GiGe cable setup and CDUA computation for wideband AoA detection. My desktop spec is Processors: Intel Core i9 7900X 10-Core 3.3GHz (4.3GHz TurboBoost), Memory: 32GB ORIGIN PC DDR4 Powered by Kingston 3000MHz (4 X 8GB),. Thanks! All Best, Jack On Sun, Jul 29, 2018 at 11:59 AM, Marcus D. Leech wrote: > On 07/29/2018 12:56 PM, Jack Yang wrote: > > Hi Marcus, > > Thanks for your mail. Yes, I am using 10GiGe interface to run the UHD C++ > code. > Any thoughts or suggestions? > > All Best, > Jack > > On Sun, Jul 29, 2018 at 9:35 AM, Marcus D. Leech via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> On 07/29/2018 12:52 AM, Jack Yang via USRP-users wrote: >> >> Hi, >> >> I have rewrote "rx_samples_to_file.cpp" for making four channel coherent >> receiver (phased-array receiver) in X310. When I executed my code, the >> terminal showed that >> >> *[ERROR] [STREAMER] The receive packet handler failed to time-align >> packets. 1002 received packets were processed by the handler. However, a >> timestamp match could not be determined.* >> >> I have attached my code as the following link ( >> https://www.dropbox.com/s/x0u0tw5e65iaual/rx_samples_X310_TwinRx.cpp?dl=0). >> The info for my UHD version is shown in below >> *"[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; >> UHD_3.11.0.HEAD-0-ga1b5c4ae"* >> >> Could someone guide me how to fix this issue? I am using two TwinRx with >> a X310 for my coherent receiver. I basically followed gr-doa python >> configuration to set up the USRP device in C++ code. However, I cannot find >> out why the time alignment is failed in here. >> >> The detailed print-out message is also listed here >> >> Thanks! >> >> All Best, >> Jack >> >> Creating the usrp device with: addr=192.168.40.2... >> [INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; >> UHD_3.11.0.HEAD-0-ga1b5c4ae >> [INFO] [X300] X300 initialization sequence... >> [INFO] [X300] Determining maximum frame size... >> [INFO] [X300] Maximum frame size: 8000 bytes. >> [INFO] [X300] Setup basic communication... >> [INFO] [X300] Loading values from EEPROM... >> [INFO] [X300] Setup RF frontend clocking... >> [INFO] [X300] Radio 1x clock:200 >> [INFO] [RFNOC DMA FIFO] Running BIST for FIFO 0... >> [INFO] [RFNOC DMA FIFO] BIST passed (Throughput: 1299 MB/s) >> [INFO] [RFNOC DMA FIFO] Running BIST for FIFO 1... >> [INFO] [RFNOC DMA FIFO] BIST passed (Throughput: 1316 MB/s) >> [WARNING] [RFNOC] [0/Radio_0] defines 2 input buffer sizes, but 1 input >> ports >> [INFO] [RFNOC RADIO] Register loopback test passed >> [INFO] [RFNOC RADIO] Register loopback test passed >> [WARNING] [RFNOC] [0/Radio_1] defines 2 input buffer sizes, but 1 input >> ports >> [INFO] [RFNOC RADIO] Register loopback test passed >> [INFO] [RFNOC RADIO] Register loopback test passed >> [INFO] [CORES] Performing timer loopback test... >> [INFO] [CORES] Timer loopback test passed >> [INFO] [CORES] Performing timer loopback test... >> [INFO] [CORES] Timer loopback test passed >> Using Device: Single USRP: >> Device: X-Series Device >> Mboard 0: X310 >> RX Channel: 0 >> RX DSP: 0 >> RX Dboard: A >> RX Subdev: TwinRX RX0 >> RX Channel: 1 >> RX DSP: 1 >> RX Dboard: A >> RX Subdev: TwinRX RX1 >> RX Channel: 2 >> RX DSP: 0 >> RX Dboard: B >> RX Subdev: TwinRX RX0 >> RX Channel: 3 >> RX DSP: 1 >> RX Dboard: B >> RX Subdev: TwinRX RX1 >> TX Channel: 0 >> TX DSP: 0 >> TX Dboard: A >> TX Subdev: Unknown (0x0094) - 0 >> TX Channel: 1 >> TX DSP: 0 >> TX Dboard: B >> TX Subdev: Unknown (0x0094) - 0 >> >> Setting RX Rate: 10.00 Msps... >> Actual RX Rate: 10.00 Msps... >> >> [INFO] [MULTI_USRP] 1) catch time transition at pps edge >> [INFO] [MULTI_USRP] 2) set times next pps (synchronously) >> Setting RX Gain: 60.00 dB... >> Actual RX Gain: 60.00 dB... >> >> Setting RX Freq: 900.00 MHz... >> Waiting for "lo_locked": + locked. >> >> Press Ctrl + C to stop streaming... >> [ERROR] [STREAMER] The receive packet handler failed to time-align >> packets. 1002 received packets were processed by the handler. However, a >> timestamp match could not be determined. >> >> >> You're presumably doing this over a 10GiGe interface? >> >> If you run at a lower sample-rate, like 5Msps do you see this problem? > > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Time alignment failure for four channels coherent receiver in X310
Hi Marcus, Thanks for your mail. Yes, I am using 10GiGe interface to run the UHD C++ code. Any thoughts or suggestions? All Best, Jack On Sun, Jul 29, 2018 at 9:35 AM, Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> wrote: > On 07/29/2018 12:52 AM, Jack Yang via USRP-users wrote: > > Hi, > > I have rewrote "rx_samples_to_file.cpp" for making four channel coherent > receiver (phased-array receiver) in X310. When I executed my code, the > terminal showed that > > *[ERROR] [STREAMER] The receive packet handler failed to time-align > packets. 1002 received packets were processed by the handler. However, a > timestamp match could not be determined.* > > I have attached my code as the following link ( > https://www.dropbox.com/s/x0u0tw5e65iaual/rx_samples_X310_TwinRx.cpp?dl=0). > The info for my UHD version is shown in below > *"[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; > UHD_3.11.0.HEAD-0-ga1b5c4ae"* > > Could someone guide me how to fix this issue? I am using two TwinRx with a > X310 for my coherent receiver. I basically followed gr-doa python > configuration to set up the USRP device in C++ code. However, I cannot find > out why the time alignment is failed in here. > > The detailed print-out message is also listed here > > Thanks! > > All Best, > Jack > > Creating the usrp device with: addr=192.168.40.2... > [INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; > UHD_3.11.0.HEAD-0-ga1b5c4ae > [INFO] [X300] X300 initialization sequence... > [INFO] [X300] Determining maximum frame size... > [INFO] [X300] Maximum frame size: 8000 bytes. > [INFO] [X300] Setup basic communication... > [INFO] [X300] Loading values from EEPROM... > [INFO] [X300] Setup RF frontend clocking... > [INFO] [X300] Radio 1x clock:200 > [INFO] [RFNOC DMA FIFO] Running BIST for FIFO 0... > [INFO] [RFNOC DMA FIFO] BIST passed (Throughput: 1299 MB/s) > [INFO] [RFNOC DMA FIFO] Running BIST for FIFO 1... > [INFO] [RFNOC DMA FIFO] BIST passed (Throughput: 1316 MB/s) > [WARNING] [RFNOC] [0/Radio_0] defines 2 input buffer sizes, but 1 input > ports > [INFO] [RFNOC RADIO] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [WARNING] [RFNOC] [0/Radio_1] defines 2 input buffer sizes, but 1 input > ports > [INFO] [RFNOC RADIO] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [INFO] [CORES] Performing timer loopback test... > [INFO] [CORES] Timer loopback test passed > [INFO] [CORES] Performing timer loopback test... > [INFO] [CORES] Timer loopback test passed > Using Device: Single USRP: > Device: X-Series Device > Mboard 0: X310 > RX Channel: 0 > RX DSP: 0 > RX Dboard: A > RX Subdev: TwinRX RX0 > RX Channel: 1 > RX DSP: 1 > RX Dboard: A > RX Subdev: TwinRX RX1 > RX Channel: 2 > RX DSP: 0 > RX Dboard: B > RX Subdev: TwinRX RX0 > RX Channel: 3 > RX DSP: 1 > RX Dboard: B > RX Subdev: TwinRX RX1 > TX Channel: 0 > TX DSP: 0 > TX Dboard: A > TX Subdev: Unknown (0x0094) - 0 > TX Channel: 1 > TX DSP: 0 > TX Dboard: B > TX Subdev: Unknown (0x0094) - 0 > > Setting RX Rate: 10.00 Msps... > Actual RX Rate: 10.00 Msps... > > [INFO] [MULTI_USRP] 1) catch time transition at pps edge > [INFO] [MULTI_USRP] 2) set times next pps (synchronously) > Setting RX Gain: 60.00 dB... > Actual RX Gain: 60.00 dB... > > Setting RX Freq: 900.00 MHz... > Waiting for "lo_locked": + locked. > > Press Ctrl + C to stop streaming... > [ERROR] [STREAMER] The receive packet handler failed to time-align > packets. 1002 received packets were processed by the handler. However, a > timestamp match could not be determined. > > > You're presumably doing this over a 10GiGe interface? > > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Time alignment failure for four channels coherent receiver in X310
Hi, I have rewrote "rx_samples_to_file.cpp" for making four channel coherent receiver (phased-array receiver) in X310. When I executed my code, the terminal showed that *[ERROR] [STREAMER] The receive packet handler failed to time-align packets. 1002 received packets were processed by the handler. However, a timestamp match could not be determined.* I have attached my code as the following link (https://www.dropbox.com/s/x0u 0tw5e65iaual/rx_samples_X310_TwinRx.cpp?dl=0). The info for my UHD version is shown in below *"[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; UHD_3.11.0.HEAD-0-ga1b5c4ae"* Could someone guide me how to fix this issue? I am using two TwinRx with a X310 for my coherent receiver. I basically followed gr-doa python configuration to set up the USRP device in C++ code. However, I cannot find out why the time alignment is failed in here. The detailed print-out message is also listed here Thanks! All Best, Jack Creating the usrp device with: addr=192.168.40.2... [INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; UHD_3.11.0.HEAD-0-ga1b5c4ae [INFO] [X300] X300 initialization sequence... [INFO] [X300] Determining maximum frame size... [INFO] [X300] Maximum frame size: 8000 bytes. [INFO] [X300] Setup basic communication... [INFO] [X300] Loading values from EEPROM... [INFO] [X300] Setup RF frontend clocking... [INFO] [X300] Radio 1x clock:200 [INFO] [RFNOC DMA FIFO] Running BIST for FIFO 0... [INFO] [RFNOC DMA FIFO] BIST passed (Throughput: 1299 MB/s) [INFO] [RFNOC DMA FIFO] Running BIST for FIFO 1... [INFO] [RFNOC DMA FIFO] BIST passed (Throughput: 1316 MB/s) [WARNING] [RFNOC] [0/Radio_0] defines 2 input buffer sizes, but 1 input ports [INFO] [RFNOC RADIO] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [WARNING] [RFNOC] [0/Radio_1] defines 2 input buffer sizes, but 1 input ports [INFO] [RFNOC RADIO] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [INFO] [CORES] Performing timer loopback test... [INFO] [CORES] Timer loopback test passed [INFO] [CORES] Performing timer loopback test... [INFO] [CORES] Timer loopback test passed Using Device: Single USRP: Device: X-Series Device Mboard 0: X310 RX Channel: 0 RX DSP: 0 RX Dboard: A RX Subdev: TwinRX RX0 RX Channel: 1 RX DSP: 1 RX Dboard: A RX Subdev: TwinRX RX1 RX Channel: 2 RX DSP: 0 RX Dboard: B RX Subdev: TwinRX RX0 RX Channel: 3 RX DSP: 1 RX Dboard: B RX Subdev: TwinRX RX1 TX Channel: 0 TX DSP: 0 TX Dboard: A TX Subdev: Unknown (0x0094) - 0 TX Channel: 1 TX DSP: 0 TX Dboard: B TX Subdev: Unknown (0x0094) - 0 Setting RX Rate: 10.00 Msps... Actual RX Rate: 10.00 Msps... [INFO] [MULTI_USRP] 1) catch time transition at pps edge [INFO] [MULTI_USRP] 2) set times next pps (synchronously) Setting RX Gain: 60.00 dB... Actual RX Gain: 60.00 dB... Setting RX Freq: 900.00 MHz... Waiting for "lo_locked": + locked. Press Ctrl + C to stop streaming... [ERROR] [STREAMER] The receive packet handler failed to time-align packets. 1002 received packets were processed by the handler. However, a timestamp match could not be determined. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Random Phase Offset Between Two Rx Channels of B210 ???
Hi I would like to follow up this conversation. Is it possible to have a constant initial phase offset for every run when power is up? I knew the B210 can remains constant phase offset across two receivers during the operation. However, the challenge for me is that whenever power is up, the initial phase across devices is not constant. Namely, the first run v.s. the second run will have different phase offset across two receiver even though I feed into the same single frequency tone through the power-splitter. Is there anyway we can fix this thing? Thanks! All Best, Jack On Fri, Jul 13, 2018 at 8:05 PM, Jack Yang wrote: > Hi I would like to follow up this conversation. Is it possible to have a > constant initial phase offset for every run when power is up? > I knew the B210 can remains constant phase offset across two receivers > during the operation. However, the challenge for me is that whenever power > is up, the initial phase across devices is not constant. Namely, the first > run v.s. the second run will have different phase offset across two > receiver even though I feed into the same single frequency tone through the > power-splitter. Is there anyway we can fix this thing? > > Thanks! > > All Best, > Jack > > > On Tue, Mar 24, 2015 at 2:38 PM, Ufuk Tamer via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> I am using the block in default settings so time sync part is in default. >> >> On 24.3.2015 23:20, Marcus D. Leech wrote: >> >> On 03/24/2015 05:18 PM, Ufuk Tamer wrote: >> >> I am using the latest version. I have a simple GRC flow graph that takes >> two channel I&Q data and then processing this data in Octave. And every >> time I turn on the receiver (tx & rx locations are fixed), I get different >> phase offset between two rx channels. >> >> In order to apply direction of arrival (DOA) technique, I have to first >> use a reference signal to detect this random phase offset, remove it and >> then estimate the angle of transmitter. >> >> What are you using for time-synch in the UHD source block? >> >> >> On 24.3.2015 22:12, Marcus D. Leech via USRP-users wrote: >> >> On 03/24/2015 03:12 PM, Ufuk Tamer via USRP-users wrote: >> >> Dear all, >> >> I am testing the phase offset between two Rx channels of B210. For this >> case, I transmit a sine signal with another USRP device and receive it with >> two RX channels of B210. Then I calculate the phase offset between >> channels. The problem is the phase offset changes whenever I reset the >> receiver. So it gives a random phase offset on each device turn on. >> >> Is this normal? If yes, what is the reason for this random phase offset. >> Since both channels share the same LO, where this "random" phase offset >> come from? >> >> Thank you... >> >> -- >> >> *Ufuk Tamer * >> >> What version of UHD are you using? >> >> How are you doing the two-channel receive? >> >> >> >> >> >> ___ >> USRP-users mailing >> listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >> -- >> *Ufuk* >> >> >> >> -- >> *Ufuk * >> >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
