Re: [USRP-users] Trying to build v. 003.010 Win64
Hi Vladimir, You need to link with libusb. It seems to be needed regardless of whether you enable the sub module or not. Kind regards, Joshua Sendall On 25 Sep 2017 6:18 PM, Vladimir via USRP-users wrote:[The e-mail server of the sender could not be verified (SPF Record)]Hello USRP team! In our Linux application for quite a while we use some 3.10 version of UHD (which requires FPGA ver. 33) and it works fine. Now we want to use the same version in Windows app, to match the FPGA ver. But trying to build any of 3.10 versions in MS Visual Studio 2013 (Release x64 cfg) I'm getting two strange linking errors: Error500error LNK2019: unresolved external symbol "public: virtual __cdecl uhd::transport::usb_device_handle::~usb_device_handle(void)" (??1usb_device_handle@transport@uhd@@UEAA@XZ) referenced in function "public: virtual void * __cdecl uhd::transport::usb_device_handle::`vector deleting destructor'(unsigned int)" (??_Eusb_device_handle@transport@uhd@@UEAAPEAXI@Z) Error501error LNK2019: unresolved external symbol "public: virtual __cdecl uhd::transport::usb_zero_copy::~usb_zero_copy(void)" (??1usb_zero_copy@transport@uhd@@UEAA@XZ) referenced in function "public: void __cdecl uhd::transport::usb_zero_copy::`vbase destructor'(void)" (??_Dusb_zero_copy@transport@uhd@@QEAAXXZ) in file D:\VS\uhd\host\build\lib\usb_dummy_impl.obj Looks like it's related with boost libs, which I'm not familiar with. I switched to last boost 1.65.1 (started with 1.60 with the sme results), tried UHD 3.10.0.0, 3.10.2.0 and some one in between like 3.10.1.0 - all the same. Ver. 3.9.7 builds OK. BTW, I use the following sequence to build boost: bootstrap b2 toolset=msvc-12.0 address-model=64 b2 toolset=msvc-12.0 address-model=64 --with-test link=shared As I see you have binaries for VC2013 available, obviously it should build correctly. Do you have any idea of what could be the problem here? I use MS Visual Studio 2013 Ultimate with Update 5. Thank you! Vladimir Pavlenko -- This message is subject to the CSIR's copyright terms and conditions, e-mail legal notice, and implemented Open Document Format (ODF) standard. The full disclaimer details can be found at http://www.csir.co.za/disclaimer.html. Please consider the environment before printing this email. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] [ Possible Spam ] Re: 4 Rx channels from an X310
Hi Derek, Thanks for answering my question. That is good to hear, but does this not apply to the BasicRx? When I try to use the subdevice spec "A:A A:B" (i.e. to use the same sampling setup as a a TwinRx) with a BasicRx I get a "uhd::assertion_error". If it is not currently supported could it be fixed by modifying the host-side code? Kind regards,Joshua Sendall >>> Derek Kozel 12/09/2017 18:30 >>> [ This email could possibly be spam. Only open if you are expecting this mail. This sender does not have a SPF record configured for their domain. The purpose of an SPF (Sender policy framework) record is to prevent spammers from sending messages with forged “From” addresses from the originating domain. It also identifies which mail servers are permitted to send email on behalf of your domain. ] Hello Joshua, The default FPGA image now has two DDCs which each have two DSP chains. The message you link to is from 2014 and we've substantially updated the contents of the FPGA since then. Currently the TwinRX is the primary daughtercard making use of these additional DDC chains as the others are 1RX per daughtercard. Regards, Derek On Tue, Sep 12, 2017 at 3:15 AM, Josh Sendall via USRP-users wrote: Hi all, I have been looking through some previous posts on the mailing list, for example [USRP-users] subdev spec for two channels with USRP X310 ( http://http//lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2014-July/010010.html) which suggests that it should not be possible to receive 4 channels (with the standard FPGA image and UHD) on an X300/X310, due to them only having 2 DDC blocks. However I then saw this project ( https://github.com/EttusResearch/gr-doa) (gr-doa), which seems to suggest that, using the standard FPGA image, one can run 4 channels using 2 TwinRx daughter boards. Would that not still require 4 DDC blocks, or can a DDC block be configured to process 2 real streams? Kind regards, Joshua Sendall Joshua Sendall Radar Signal Analyst Defense, Peace, Safety and Security (DPSS) Council for Scientific and Industrial Research (CSIR) Building 44 - Room C 433 CSIR, Meiring Naude Road, Pretoria Tel: 012 841 3575 This message is subject to the CSIR's copyright terms and conditions, e-mail legal notice, and implemented Open Document Format (ODF) standard. The full disclaimer details can be found at http://www.csir.co.za/disclaimer.html. Please consider the environment before printing this email. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com -- This message is subject to the CSIR's copyright terms and conditions, e-mail legal notice, and implemented Open Document Format (ODF) standard. The full disclaimer details can be found at http://www.csir.co.za/disclaimer.html. Please consider the environment before printing this email. <> ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] 4 Rx channels from an X310
Hi all, I have been looking through some previous posts on the mailing list, for example [USRP-users] subdev spec for two channels with USRP X310 ( http://http//lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2014-July/010010.html) which suggests that it should not be possible to receive 4 channels (with the standard FPGA image and UHD) on an X300/X310, due to them only having 2 DDC blocks. However I then saw this project ( https://github.com/EttusResearch/gr-doa) (gr-doa), which seems to suggest that, using the standard FPGA image, one can run 4 channels using 2 TwinRx daughter boards. Would that not still require 4 DDC blocks, or can a DDC block be configured to process 2 real streams? Kind regards, Joshua Sendall Joshua Sendall Radar Signal Analyst Defense, Peace, Safety and Security (DPSS) Council for Scientific and Industrial Research (CSIR) Building 44 - Room C 433 CSIR, Meiring Naude Road, Pretoria Tel: 012 841 3575 -- This message is subject to the CSIR's copyright terms and conditions, e-mail legal notice, and implemented Open Document Format (ODF) standard. The full disclaimer details can be found at http://www.csir.co.za/disclaimer.html. Please consider the environment before printing this email. <> ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
