[USRP-users] b205mini and gpsdo

[carry chen via USRP-users]

hi list，

I plan to buy a gps module ，the gps module have 1pps pin and uart pin. I will 
connect the 1pps pin to b205mini “REF” sma port to Disciplin The local clock. 
And connect uart pin to gpio to read time info.
That is ok?

Thanks!

Best Regards,
Charlies

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[USRP-users] check_fpga_compat signature register readback failed

[carry chen via USRP-users]

Hi,list
today , I find a problem when run usrp b205mini:

b200::check_fpga_compat signature register readback failed

is the board go bad?

Thanks!

Carry
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[USRP-users] send custom data via txstreamer

[carry chen via USRP-users]

 hi,
this days I make some modify in usrp e310 fpga.
I want to recv my custom data and process in fpga.

so I modify the file  xxx/e310/radio.v :
from:
 axi_fifo_2clk #(.WIDTH(65), .SIZE(DATA_FIFO_SIZE)) tx_data_2clk_fifo
 (.reset(bus_rst),
  .i_aclk(bus_clk), .i_tvalid(tx_tvalid_bi), .i_tready(tx_tready_bi), 
.i_tdata({tx_tlast_bi,tx_tdata_bi}),
  .o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), 
.o_tdata({tx_tlast_r,tx_tdata_r}));

to:
wire custom_tvalid;
wire custom_tlast;
wire [63:0] custom_tdata;
   wire custom_tready;
 axi_fifo_2clk #(.WIDTH(65), .SIZE(DATA_FIFO_SIZE)) tx_data_2clk_fifo
 (.reset(bus_rst),
  .i_aclk(bus_clk), .i_tvalid(tx_tvalid_bi), .i_tready(tx_tready_bi), 
.i_tdata({tx_tlast_bi,tx_tdata_bi}),
  .o_aclk(radio_clk), .o_tvalid(custom_tvalid), .o_tready(custom_tready), 
.o_tdata({custom_tlast,custom_tdata}));

  my_module test
  (
 .valid(custom_tvalid),
 .last(custom_tlast),
 .ready(custom_tdata),
 .data(custom_tdata)
  );

  when send one packet with tx_streamer->send() , data is send and recv ok!

  but when I send many packet, It become stuck!!  tx_streamer->send() need many 
seconds to return!!

  is that some flow control when send?

  can I get some tips?

  Thank you!

  Best Regards,
  Carry



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Re: [USRP-users] about rfnoc nocshell

[carry chen via USRP-users]

Thanks Jonathon!

I want to send some data block to radio. I need to use uhd on arm and send the 
data. now I want to put the data block on ps memory, and access the data block 
in pl, so I can send the data block in PL direct!

can I setup  my own datamover on another HP AXI port under uhd fpga framework? 
I use uhd-003012,no rfnoc.


Thanks again!


Best Regards,

Carry


From: Jon Pendlum 
Sent: Thursday, August 9, 2018 3:44:43 AM
To: carry chen
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] about rfnoc nocshell

Hi.

Yes, but you should leave that one alone and setup your own datamover
on another HP AXI port. What do you want to accomplish?

Jonathon

On Sun, Aug 5, 2018 at 11:44 AM, carry chen  wrote:
>
> Thanks Jonathon!
> Does uhd fpga use datamover access PS DDR now?
>
> Best Regards,
> Carry
>
> 
> From: Jon Pendlum 
> Sent: Monday, July 30, 2018 7:57 PM
> To: carry chen
> Cc: usrp-users@lists.ettus.com
> Subject: Re: [USRP-users] about rfnoc nocshell
>
> Hi,
>
> 1) You cannot reduce noc_shell resource usage much. You can try
> putting all your custom logic in just one RFNoC block, that way you do
> not incur the overhead of multiple noc_shell instances.
> 2) Do you mean "Can I access PS DDR memory directly from the FPGA
> fabric?" If so, yes you can via the HP AXI ports. You'll need
> something to interface with the HP AXI port though. Xilinx's AXI
> Datamover or AXI DMA IP blocks are decent choices.
>
> Jonathon
>
> On Fri, Jul 6, 2018 at 3:26 AM, carry chen via USRP-users
>  wrote:
>> hello,list,
>>
>> I have study the rfnoc,I have 2 question:
>> 1. I find nocshell module use large resource, e310 resource is less, so
>> can
>> I adjust some param to reduce the resoure comsume? I only config one
>> radio(1
>> ddc+1 duc),I find use so many resouce
>> 2.Can I share memory between ps and pl direct?
>>
>> Best,Regards,
>> Carry
>>
>> ___
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>>
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Re: [USRP-users] about rfnoc nocshell

[carry chen via USRP-users]

Thanks Jonathon!
Does uhd fpga use datamover access PS DDR now?

Best Regards,
Carry


From: Jon Pendlum 
Sent: Monday, July 30, 2018 7:57 PM
To: carry chen
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] about rfnoc nocshell

Hi,

1) You cannot reduce noc_shell resource usage much. You can try
putting all your custom logic in just one RFNoC block, that way you do
not incur the overhead of multiple noc_shell instances.
2) Do you mean "Can I access PS DDR memory directly from the FPGA
fabric?" If so, yes you can via the HP AXI ports. You'll need
something to interface with the HP AXI port though. Xilinx's AXI
Datamover or AXI DMA IP blocks are decent choices.

Jonathon

On Fri, Jul 6, 2018 at 3:26 AM, carry chen via USRP-users
 wrote:
> hello,list,
>
> I have study the rfnoc,I have 2 question:
> 1. I find nocshell module use large resource, e310 resource is less, so can
> I adjust some param to reduce the resoure comsume? I only config one radio(1
> ddc+1 duc),I find use so many resouce
> 2.Can I share memory between ps and pl direct?
>
> Best,Regards,
> Carry
>
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>
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Re: [USRP-users] usrp e310 one tx one rx

[carry chen via USRP-users]

Thank,
Martin.
I try and can not work!
I need to deep into now.

Best,Regards
Carry

From: USRP-users  on behalf of Martin Braun 
via USRP-users 
Sent: Wednesday, July 25, 2018 5:34:44 AM
To: 'USRP-users@lists.ettus.com'
Subject: Re: [USRP-users] usrp e310 one tx one rx

Link should be:

https://github.com/EttusResearch/fpga/blob/f27926410328883a315d5230146936d2d782bd09/usrp3/top/e300/e310_core.v#L319

On 07/24/2018 02:20 PM, Martin Braun wrote:
> I think you might be fine changing this line:
>
> https://github.com/EttusResearch/fpgadev/blob/f27926410328883a315d5230146936d2d782bd09/usrp3/top/e300/e310_core.v#L319
>
> ...but it's untested and unsupported.
>
> Cheers,
> Martin
>
> On 07/22/2018 04:02 AM, carry chen via USRP-users wrote:
>> Hi,
>>
>> list,
>>
>> I want the usrp e310 run only one tx path and one rx path (to save some
>> fpag resource)
>>
>> how can I modify the host code and fpga code ?
>>
>> I use the uhd version:  ca09fd2bea0128c18eac4b0ff8a9b30fccdf7698
>>
>>fpga version:  63e630a13fde1735b98eab1f401f60f0b354cafb
>>
>>
>> Thanks.
>>
>>
>> Best, Regards,
>>
>> Carry
>>
>>
>>
>> ___
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>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>


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[USRP-users] read/write ddr3 in usrp e310 PL

[carry chen via USRP-users]

Hi,list


I know usrp e310 have a ddr3 in PL part, now I need store some data in ddr3 so

I can do some dsp algo.


So how Can I read/write the ddr3 easy? How many space I can use in ddr3?

Is there some example?


Thanks!


Best, Regards,

Carry
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[USRP-users] usrp e310 one tx one rx

[carry chen via USRP-users]

Hi,

list,

I want the usrp e310 run only one tx path and one rx path (to save some fpag 
resource)

how can I modify the host code and fpga code ?

I use the uhd version:   ca09fd2bea0128c18eac4b0ff8a9b30fccdf7698

   fpga version:  63e630a13fde1735b98eab1f401f60f0b354cafb


Thanks.


Best, Regards,

Carry
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[USRP-users] about rfnoc nocshell

[carry chen via USRP-users]

hello,list,

I have study the rfnoc,I have 2 question:
1. I find nocshell module use large resource, e310 resource is less, so can I 
adjust some param to reduce the resoure comsume? I only config one radio(1 
ddc+1 duc),I find use so many resouce
2.Can I share memory between ps and pl direct?

Best,Regards,
Carry
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[USRP-users] run app on single core in usrp e310

[carry chen via USRP-users]

Hi,

I play usrp e310 this days.

can I run my app with single core and run os on another core?

thank you!


Best, Regards,

Carry
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[USRP-users] newest e310 uhd rfnoc problem

[carry chen via USRP-users]

Hi,

I build the newest uhd rfnoc and fpga rfnoc for e310 this days.

every thing is ok but when I run uhd_usrp_probe, I get some error:

[INFO] [UHD] linux; GNU C++ version 4.9.2; Boost_105700; 
UHD_4.0.0.rfnoc-devel-714-g57466164
[INFO] [E300] Loading FPGA image: 
/home/root/newinstall/usr/share/uhd/images/usrp_e310_fpga_sg3.bit...
[INFO] [E300] FPGA image loaded
[INFO] [E300] Initializing core control (global registers)...

[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1000)
Error: RuntimeError: Can't set GPIO source by GPIO ATR interface.


I build follw by the link:

https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source


uhd version:

"
commit 574661647890deb6427226cc71444feb079ec50f
Author: Martin Braun 
Date:   Mon Apr 16 09:23:16 2018 -0700

Update submodule pointer for rfnoc-devel

"


fpga version:

"

commit 9c8c2ba1d163ec01fea0cf60257051e866ec1f1a
Merge: 1f2965a bc44e37
Author: Martin Braun 
Date:   Mon Apr 9 15:31:44 2018 -0700

Merge branch 'master' into rfnoc-devel


"


I get the source by the command:

git clone -b rfnoc-devel --recursive  https://github.com/EttusResearch/uhd.git


Can I get some tips?


Thanks!


Best Regards,

Carry




[https://avatars0.githubusercontent.com/u/125709?s=400&v=4]

EttusResearch/uhd
github.com
uhd - The USRP™ Hardware Driver Repository







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[USRP-users] e310 rfnoc error

[carry chen via USRP-users]

Hi list:


I play usrp e310 rfnoc this days now!

But I meet some problem, uhd have some runtime error!

like this link desc:

https://www.mail-archive.com/usrp-users@lists.ettus.com/msg03926.html


"

Hi Paul,

Unfortunately, we are aware of this bug and we are following it in our
internal bug tracker. I will come back to you as soon as we have a
fix/workaround for it.

We are sorry for the inconveniences here.

Sincerely,
-Nicolas


"


I know the newest version  have bug.

so how can I get the old version source of uhd rfnoc and fpga rfnoc?

then I can test rfnoc on my e310.

the buildin uhd in e310 is 3.9.xx.


Best Regards,

Carry

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[USRP-users] build uhd rfnoc for e310 get some errors

[carry chen via USRP-users]

Hi,list,

I complie uhd rfnoc version for e310 follow the link:


https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source



but when run on e310, I get some error:

[INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700; 
UHD_4.0.0.rfnoc-devel-409-gec9138eb]
[INFO] [E300] Loading FPGA image: 
/home/root/newinstall/usr/share/uhd/images/usrp_e310_fpga_sg3.bit...
[INFO] [E300] FPGA image loaded
[INFO] [E300] Initializing core control (global registers)...

[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
[INFO] [RFNOC RADIO] Register loopback test passed
[INFO] [RFNOC RADIO] Register loopback test passed
[WARNING] [RFNOC] [0/fosphor_0] defines 2 input buffer sizes, but 1 input ports
[INFO] [AD936X] Performing CODEC loopback test...
[INFO] [AD936X] CODEC loopback test passed
[INFO] [AD936X] Performing CODEC loopback test...
[INFO] [AD936X] CODEC loopback test passed
[INFO] [CORES] Performing timer loopback test...
[INFO] [CORES] Timer loopback test passed
  _
 /
|   Device: E-Series Device
| _
|/
|   |   Mboard: E3XX
|   |   product: 30675
|   |   revision: 6
|   |   serial: F65F2F
|   |   mac-addr: 00:80:2f:16:0b:fd
|   |   FPGA Version: 255.0
|   |   FPGA git hash: f764326-dirty
|   |   RFNoC capable: Yes
|   |
|   |   Time sources:  none, internal, external
|   |   Clock sources: internal
|   |   Sensors: temp, ref_locked
|   | _
|   |/
|   |   |   RX DSP: 0
|   |   |
|   |   |   Freq range: 0.000 to 0.000 MHz
|   | _
|   |/
|   |   |   RX DSP: 1
|   |   |
|   |   |   Freq range: 0.000 to 0.000 MHz
|   | _
|   |/
|   |   |   RX Dboard: A
|   |   |   ID: E310 MIMO XCVR (0x0110)
|   |   |   Serial: 3102B9F
|   |   | _
|   |   |/
|   |   |   |   RX Frontend: A
|   |   |   |   Name: FE-RX2
|   |   |   |   Antennas: TX/RX, RX2
|   |   |   |   Sensors: temp, rssi, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 76.0 step 1.0 dB
|   |   |   |   Bandwidth range: 20.0 to 5600.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   | _
|   |   |/
|   |   |   |   RX Frontend: B
|   |   |   |   Name: FE-RX1
|   |   |   |   Antennas: TX/RX, RX2
|   |   |   |   Sensors: temp, rssi, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 76.0 step 1.0 dB
|   |   |   |   Bandwidth range: 20.0 to 5600.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   | _
|   |   |/
|   |   |   |   RX Codec: A
|   |   |   |   Name: E3x0 RX dual ADC
|   |   |   |   Gain Elements: None
|   | _
|   |/
|   |   |   TX DSP: 0
|   |   |
|   |   |   Freq range: 0.000 to 0.000 MHz
|   | _
|   |/
|   |   |   TX DSP: 1
|   |   |
|   |   |   Freq range: 0.000 to 0.000 MHz
|   | _
|   |/
|   |   |   TX Dboard: A
|   |   |   ID: E310 MIMO XCVR (0x0110)
|   |   |   Serial: 3102B9F
|   |   | _
|   |   |/
|   |   |   |   TX Frontend: A
|   |   |   |   Name: FE-TX2
|   |   |   |   Antennas: TX/RX
|   |   |   |   Sensors: temp, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 89.8 step 0.2 dB
|   |   |   |   Bandwidth range: 20.0 to 5600.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   | _
|   |   |/
|   |   |   |   TX Frontend: B
|   |   |   |   Name: FE-TX1
|   |   |   |   Antennas: TX/RX
|   |   |   |   Sensors: temp, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 89.8 step 0.2 dB
|   |   |   |   Bandwidth range: 20.0 to 5600.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   | _
|   |   |/
|   |   |   |   TX Codec: A
|   |   |   |   Name: E3x0 TX dual DAC
|   |   |   |   Gain Elements: None
|   | _
|   |/
|   |   |   RFNoC blocks on this device:
|   |   |
|   |   |   * Radio_0
|   |   |   * FIFO_0
|   |   |   * Window_0
|   |   |

[USRP-users] b205mini gpio control

[carry chen via USRP-users]

Hi,

I want to control the b205mini gpio pin,let it output high or low signal to 
control external device. so do I need to modify fpga? or use uhd only? is that 
some sample code in uhd?

Best Regards,
Carry
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