[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

https://github.com/asi-sc closed https://github.com/llvm/llvm-project/pull/108406 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

https://github.com/asi-sc updated https://github.com/llvm/llvm-project/pull/108406 >From 0c2925d18e8e4312a16d081c1c97d3298b85e8d4 Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Mon, 2 Sep 2024 13:25:39 +0300 Subject: [PATCH 1/2] [RISCV] Add Syntacore SCR7 processor definition Syntacore S

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

@@ -502,3 +502,28 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=synt

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

https://github.com/asi-sc created https://github.com/llvm/llvm-project/pull/108406 Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core. The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march. Overview: https://syntacore.com/products/scr7 Scheduling model will be added in a subs

[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

https://github.com/asi-sc closed https://github.com/llvm/llvm-project/pull/102285 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

https://github.com/asi-sc updated https://github.com/llvm/llvm-project/pull/102285 >From aeae8cfd59de3e0898e3e70882dc1ef566d6f021 Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Thu, 4 Jul 2024 18:09:26 +0300 Subject: [PATCH] [RISCV] Add Syntacore SCR5 RV32/64 processors definition Syntac

[clang] [RISCV] full support for riscv_rvv_vector_bits attribute (PR #100110)

https://github.com/asi-sc closed https://github.com/llvm/llvm-project/pull/100110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

@@ -378,6 +378,32 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64", FeatureStdExtC], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def SYNTACORE_SCR5_RV32 :

[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

https://github.com/asi-sc created https://github.com/llvm/llvm-project/pull/102285 Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V processor core. Overview: https://syntacore.com/products/scr5 Scheduling model will be added in a subsequent PR. Co-authored-by: Dmitrii Petrov Co

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

https://github.com/asi-sc closed https://github.com/llvm/llvm-project/pull/101321 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

@@ -106,6 +106,7 @@ Changes to the RISC-V Backend * `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill the required alignment space with a sequence of `0x0` bytes (the requested fill value) rather than NOPs. +* Added Syntacore SCR4 CPUs: ``-mcpu=s

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

https://github.com/asi-sc edited https://github.com/llvm/llvm-project/pull/101321 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

https://github.com/asi-sc created https://github.com/llvm/llvm-project/pull/101321 Syntacore SCR4 is a microcontroller-class processor core that has much in common with SCR3. The most significant difference for compilers is F and D extensions support. Overview: https://syntacore.com/products/s

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

https://github.com/asi-sc closed https://github.com/llvm/llvm-project/pull/95953 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

@@ -358,3 +358,21 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-sc

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

@@ -358,3 +358,21 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-sc

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

https://github.com/asi-sc updated https://github.com/llvm/llvm-project/pull/95953 >From 75c4b0d1deb57fb22f9b2446aa8b368c662c38b8 Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Tue, 18 Jun 2024 19:40:54 +0300 Subject: [PATCH 1/2] [RISCV] Add Syntacore SCR3 processor definition Syntacore S

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

https://github.com/asi-sc created https://github.com/llvm/llvm-project/pull/95953 Syntacore SCR3 is a microcontroller-class processor core. Overview: https://syntacore.com/products/scr3 This PR introduces two CPUs: * 'syntacore-scr3-rv32' which is rv32imc * 'syntacore-scr3-rv64' which is rv

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

@@ -0,0 +1,266 @@ +//==- RISCVSchedSyntacoreSCR3.td - Syntacore SCR3 Scheduling Definitions -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Id

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

asi-sc wrote: It'd be great if someone outside of Syntacore would have a quick look at this patch too. https://github.com/llvm/llvm-project/pull/95427 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listi

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

https://github.com/asi-sc updated https://github.com/llvm/llvm-project/pull/95427 >From 1449d6ba48779051f19dcf9160aaa40599e2750e Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Fri, 31 May 2024 16:10:28 +0300 Subject: [PATCH 1/2] [RISCV] Add scheduling model for Syntacore SCR3 Syntacore S

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

https://github.com/asi-sc created https://github.com/llvm/llvm-project/pull/95427 Syntacore SCR3 is a microcontroller-class processor core. Overview: https://syntacore.com/products/scr3 This PR introduces two CPUs: * 'syntacore-scr3-rv32' which is rv32imc * 'syntacore-scr3-rv64' which is rv