On Mon, Mar 31, 2008 at 11:46 AM, Uwe Bonnes
[EMAIL PROTECTED] wrote:
Hello,
has there been any effort to expose more JTAG functionality via the FX2 so
that the USRP FX2 firmware could be used with modified other JTAG software,
like xc3sprog.
As far as I can tell, not without some
On Fri, Mar 28, 2008 at 5:03 AM, Jason Anders [EMAIL PROTECTED] wrote:
Hi all!
Is it possible to set both the Rx-A and the Rx-B (of the BASIC Rx
daughterboard) to ON while at the same time allowing I and Q sampling? How
will this be done?
So a while ago, I tried to put together a little
On Fri, Mar 28, 2008 at 8:06 AM, Jason Anders [EMAIL PROTECTED] wrote:
I would like to ask how to use mpsk_receiver_cc.
The C++ code for the implementation can be found here:
http://gnuradio.org/trac/browser/gnuradio/trunk/gnuradio-core/src/lib/general/gr_mpsk_receiver_cc.cc
It looks
On Thu, Mar 27, 2008 at 5:57 PM, Eric Blossom [EMAIL PROTECTED] wrote:
IIRC Arial == Helvetica. Not sure about Georgia.
According to wikipedia:
http://en.wikipedia.org/wiki/Georgia_(typeface)
Georgia closely resembles Times New Roman.
Brian
On Mon, Mar 24, 2008 at 1:02 AM, Mohammad Hamed Firooz
[EMAIL PROTECTED] wrote:
Hi,
As you may know, BBN guys have developed a receiver for 802.11b. But
due to the USB limitation, they had to cut the spectrum which leads to
low SNR. We have developed a new receiver by doing some operation
On Thu, Mar 6, 2008 at 6:03 PM, W. David Li [EMAIL PROTECTED] wrote:
Hello,
I got this error when connecting a file_descriptor source to an audio
sink in a top_block. Any ideas what might have gone wrong?
I am going to take a guess, but I believe you have exceeded your max
recursion depth.
On Tue, Mar 4, 2008 at 1:27 PM, Manav Rohil [EMAIL PROTECTED] wrote:
thanks for the replies...
So that means if i dont have a USRP, i cannot simulate a packet
transmission/reception entirely in software since the data will never be
modulated to the carrier frequency.
No need for a USRP ...
Would it be of any interest for the Verilog in the USRP to actually
match bit-for-bit a simulation block that can be run on the host
machine?
Basically just float - integer - fixed-point up/down conversion
filtering for the halfband FIR and/or CIC filters and the CORDIC that
occurs?
Just trying
On Wed, Feb 27, 2008 at 9:18 AM, Jose Emilio Gervilla Rega
[EMAIL PROTECTED] wrote:
Hello all,
We are working in OFDM synchronization. When you install GNURadio, there
are among the examples an OFDM system which runs perfectly. But we need to
run other different files that we have found in
On Wed, Feb 27, 2008 at 9:13 AM, Neal Becker [EMAIL PROTECTED] wrote:
Thanks!
I just grabbed webpack and I'm trying it out.
One thing you might like to know:
In my initial testing, it's working on Fedora F8 x86_64. It doesn't want
you to run on x86_64, but with a few minor hacks it's
On Wed, Feb 27, 2008 at 11:43 AM, Jose Emilio Gervilla Rega
[EMAIL PROTECTED] wrote:
Hello all,
I will give you more details about my problem because someone has asked me
for them(thank you):
The OFDM system we are using is which is defined in this link:
On Feb 6, 2008 10:42 AM, Eric Blossom [EMAIL PROTECTED] wrote:
The history mechanism does work as it was designed to do. For a
history setting of N, it effectively preloads the first buffer with
N-1 zeros.
So just to be clear, if we have 2 calls to work() where we set the
history to 5 taps
On Feb 1, 2008 10:48 AM, George Nychis [EMAIL PROTECTED] wrote:
Let me step all the way back and just try to be a little clearer with
what I'm trying to do.
I'm trying to simulate the frequency offset added by the crystal
oscillator in the USRP. 64MHz*20ppm/1e6=1280Hz max, +/- ?
So, I'm
On Jan 30, 2008 9:35 AM, TomasOMaille [EMAIL PROTECTED] wrote:
Hello,
I have been trying to understand the tx and rx data paths through the AD9862
and the FPGA (standard configuration).
RX side:
- The two ADCs of the AD9862 push data onto two 12 bit buses
- After the FPGA MUX the 16
On Jan 28, 2008 10:43 AM, Richard Jaeger [EMAIL PROTECTED] wrote:
I have been playing with a number of the examples - FM NB and WB
receivers, AM receiver, etc.
The sample rate appears to default to 64 MSPS, but I have been unable
to find where that default rate is set.
Where is it defined?
On Jan 23, 2008 7:50 AM, Vincenzo Pellegrini [EMAIL PROTECTED] wrote:
hi,
does gr.fft_vcc implement the FFTW algorithm?
Looking here:
http://gnuradio.org/trac/browser/gnuradio/trunk/gnuradio-core/src/lib/general/gr_fft_vcc.cc#L89
On Jan 17, 2008 2:42 PM, Matt Ettus [EMAIL PROTECTED] wrote:
...
6 Testbenches for any of the above, even if you aren't designing the
filter core itself.
I have put my attempt at a decent testbench here:
http://lebowski.eatcheese.biz/~bpadalino/halfband/
There are some
On Jan 21, 2008 10:07 PM, Jason Anders [EMAIL PROTECTED] wrote:
Hi again!
I have a question regarding the use of gr_float_to_complex block.
Unfortunately, Doxygen didn't show the implementation of such a block. What
I wanted to know is how gr_float_to_complex implements float to complex
On Jan 17, 2008 12:55 PM, Jeff Brower [EMAIL PROTECTED] wrote:
How do you implement FIFOs, SDRAM controller, GbE MAC, etc? Using a
'non-Xilinx'
method?
I don't think there's any SDRAM on the new USRP2, but if there were,
you can still write an SDRAM controller in RTL. DDR, on the other
On Jan 12, 2008 6:01 PM, George Nychis [EMAIL PROTECTED] wrote:
Would any of the FIR filters that already exist in GR be appropriate? I
could then perform the cross-correlation on the output of the block.
If you just give your known coefficients to the filter, then it really
just performs
On Dec 14, 2007 12:51 PM, George Nychis [EMAIL PROTECTED] wrote:
Taking a look at how the legacy code does it...
http://gnuradio.org/trac/browser/gnuradio/branches/developers/gnychis/inband/usrp/fpga/sdr_lib/rx_buffer.v#L137
What do you think about adopting this method? It's using a 16-bit
On Dec 14, 2007 2:54 PM, George Nychis [EMAIL PROTECTED] wrote:
Shouldn't it always be interleaved complex? When is real used?
I think single or vestigial sideband modulations use only the real component.
More info here:
http://en.wikipedia.org/wiki/Single-sideband_modulation
Brian
On Dec 13, 2007 5:07 PM, George Nychis [EMAIL PROTECTED] wrote:
Well, that definitely explains things and why my GMSK receiver can't
decode a transmission ;)
I just called Leo, he's on his way back to China for the break until
mid-January. This is something I don't want to wait on, so I'm
On Dec 10, 2007 3:26 PM, George Nychis [EMAIL PROTECTED] wrote:
In benchmark_rx.py, the samples are unmodified up to the channel filter,
correct?
All samples go through the FPGA's CORDIC and then through the CIC
filter, possibly the halfband filter depending on your configuration.
What phase
On Dec 4, 2007 1:07 PM, George Nychis [EMAIL PROTECTED] wrote:
From some discussion on comp.dsp, it seems as though I'm looking for a
matched filter:
http://groups.google.com/group/comp.dsp/browse_thread/thread/f93d7867f74dbe95#0dc48f2a8ed09e07
Yes, you are describing a matched filter.
If
On Dec 4, 2007 2:00 PM, George Nychis [EMAIL PROTECTED] wrote:
I see, I want to go lower than the PHY layer really...
You can't go lower than the PHY layer. There's a reason it's the
lowest on the stack.
Here's the thing, I don't want the solution to be dependent on the
physical layer. The
On Dec 4, 2007 8:30 PM, Ronald Jetli [EMAIL PROTECTED] wrote:
Hi,
Needed to confirm a few things:
1) Is the global clock frequency for USRP 64Mhz ?
Yes. It's a fully synchronous design with FIFO boundaries where it
talks to the FX2 chip which runs at a different clock speed I believe.
2)
On Dec 4, 2007 8:43 PM, George Nychis [EMAIL PROTECTED] wrote:
So there is no way of getting a generalized matched filter on the USRP?
Is there anything that can be done to get around the hardware
multipliers? If there is absolutely no way, limiting to GMSK, PSK, and
QAM is not that bad.
On Dec 2, 2007 7:38 AM, aamir zeb [EMAIL PROTECTED] wrote:
I wish to participate and contribute in the area od GNU Radio,
But I could not get the clue from where shall I start
May all your questions be answered here:
http://gnuradio.org/trac/wiki
Brian
On Nov 30, 2007 5:01 PM, Ronald Jetli [EMAIL PROTECTED] wrote:
Hi,
I do understand that there are always statements in the base code and the
flow of those base code is clear to me.
It is just this top module, whose logic is not clear to me. I tried writing
a test bench, but that didnt help
On Nov 29, 2007 5:13 PM, Dan Halperin [EMAIL PROTECTED] wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Wuest Brandon-WTVR47 wrote:
I am having a problems with disk writing not being able to keep up with
the high data rate, so I am trying to do a little manipulation of the IQ
data
A few questions:
- What is the current round trip latency for the in-band code?
- Have you tried synchronizing two different USRPs to each other over the air?
- What is the minimum amount of turnaround time you're looking to achieve?
Brian
___
On Nov 27, 2007 10:43 PM, George Nychis [EMAIL PROTECTED] wrote:
To measure the round trip latency we used three USRPs... two in
contention and a third monitoring. The two in contention would exchange
the channel back and forth by reading the RSSI value from the incoming
packets. To spare
On Nov 21, 2007 9:36 PM, C S Nagaraj [EMAIL PROTECTED] wrote:
Dear All,
I'm planning to use the DBSRX with USRP board. After the frequency
translation and filtering I want to process the samples further inside the
FPGA, before transferring it to the host.
If you don't mind me asking, could
On Nov 21, 2007 10:24 PM, C S Nagaraj [EMAIL PROTECTED] wrote:
Hi Brian,
Thanks for the reply.
Well, I have to decide the actual processing what goes inside the FPGA based
on the resource that will be left-over.
To start with, I'll be using only 1RX to obtain the signal at a fixed
On Nov 10, 2007 9:39 AM, Aadil Volkwin [EMAIL PROTECTED] wrote:
Ok,
I still have the problem with the reconstruction though.
When I perform the FFT on the sample set, the plots are not as you would
expect for a pure 250KHz signal?
You're transmitting a 250kHz square source which is the
On 11/9/07, Meenaktchi Venkatachalam [EMAIL PROTECTED] wrote:
Hi,
I was wondering how to calculate SNR. Is there function already a function
that I can use to find SNR?
If you know where your constellation symbols are, and you know where
the IQ symbol really ended up after equalization -
On Nov 7, 2007 9:40 AM, Uwe Bonnes
[EMAIL PROTECTED] wrote:
Hello,
the last day I am banging my head against the problem how the data is
structured for the USB transfer between the FX2 and the PC. Datasheet,
FX2 reference and the web didn't givve me the right clue.
What I understand:
- the
On 10/29/07, Dan Halperin [EMAIL PROTECTED] wrote:
In order for SDRs that think of their FPGA code as software (which I
think has to be where this is going to realize its full power), it seems
likely that we will need completely automated and reasonably fast ways
to rebuild the FPGA on the
Here are some of the thoughts running through my head in no particular order.
You don't have to have the RRC filter for transmit if you don't want
to. The CIC and the reconstruction filter of the DAC should take care
of filtering out a good portion of the extra spectrum.
To achieve the best
On 10/22/07, Nirali Patel [EMAIL PROTECTED] wrote:
Hi,
I am using the TV_RX and USRP to capture the 64 Msps data from the A/D
converter and send that to another downstream board for processing. I am
connecting the signal from the ADC to the debug IO pins of the FPGA to get
to the 16 io_rx[]
On 10/12/07, Jeff Brower [EMAIL PROTECTED] wrote:
I think the biggest concerns with Cyclone I are lack of multipliers and low
amount of
internal mem (26 kbyte for the EPC1C12).
Understandable, but also remember that a CORDIC can perform a
multiplication if you want it pipelined - and if you
On 10/10/07, Andrew Rose [EMAIL PROTECTED] wrote:
In terms of publishing what I did, I was going to put my workarounds on the
wiki, but I don't have an account, and I don't think I can make any
modifications without one.
It hasn't been mentioned in a while, but guest/gnuradio should work
for a
On 10/10/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:
Can you give me an example? I've never worked with verilog code before.
Also- this fix you are proposing- is it a simple scaling of gain that
would be independent of decimation? Because as you can see from the
following figure, the
On 10/10/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:
Well, this seems logical, and if so then we've finally stumbled on the
point of the matter. So what's the fix? Is it a simple matter of
extending the definitions to other decimations in the file Brian cites?
Either that or just do the
On 10/9/07, Robert McGwier [EMAIL PROTECTED] wrote:
...
However, nothing about the gpl prohibits individuals from using xlc to
generate binaries for their own use so long as they do not distribute
the binary.
...
This is more for curiosity than anything, but where do the USRP FPGA
bit files
As another naive note, since sincosf seems to be the dominating
function by a large factor, this website might be worth a read:
http://www.devmaster.net/forums/showthread.php?t=5784
I know there is a fast sine and cosine somewhere for filtering, but I
also thought those caused some issues
On 10/5/07, Meiners, Jason [EMAIL PROTECTED] wrote:
Could someone send me a zipped file of the gr-atsc directory in trunk? I
have had zero luck getting svc to work properly.
http://gnuradio.org/trac/wiki/Download
Please note the FTP links of the released code.
Thanks for your help.
No
On 10/4/07, Tomek [EMAIL PROTECTED] wrote:
Hello!
I´m new to GNU Radio. I´m working on a project now and trying to get it to
compile. I´m using cygwin and followed the Installing GNU Radio with Cygwin
instruction step-by-step. The only problem i hade on the way was with
wxPython because
On 10/3/07, Michael Dickens [EMAIL PROTECTED] wrote:
Maybe it's the use of python 2.5?
Has anyone (on this list, or if you know someone) ever used GRC on
OSX? As I said, I've never tried to until this morning.
This really isn't my forte, but a quick search and I saw this page:
On 10/1/07, Matt Ettus [EMAIL PROTECTED] wrote:
I think 3.3V LVTTL and LVCMOS are really the same.
Matt
According to this:
http://www.interfacebus.com/voltage_LV_threshold.html
They are, indeed, basically the same.
Brian
___
Discuss-gnuradio
On 9/26/07, W. David Li [EMAIL PROTECTED] wrote:
I have USRP board with RFX2400. The question is how GnuRadio should be
configured/compiled to use USRP. Before this I configured/compiled 3.0.4
without USRP (using ./configure, make and make install). ./configure
showed:
The following
On 9/19/07, Dominik Auras [EMAIL PROTECTED] wrote:
Hi!
Does anyone have experiences with GNU Radio and Red Hat Linux? Are there any
known problems?
The BuildGuide generally lists any issues or install procedures here:
http://www.gnuradio.org/trac/wiki/BuildGuide
Red Hat doesn't
On 9/14/07, Michael Dickens [EMAIL PROTECTED] wrote:
I've created an analog repeater that's just:
usrp source - amp - usrp sink
and I'd like to control the bandwidth that's repeated
dynamically ... on the fly via a GUI slider. I have created all of
this, and on init everything works just
On 9/13/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:
Hi,
thank you for answers. I have seen Quartus II and but I don't manage to see
with
Quartus II the content of bigger modules, for example usrp_std. How do I
do to see the content of these big modules, that is however these modules
are
On 9/13/07, Luca Dionisi [EMAIL PROTECTED] wrote:
Hi all
I'm completely new in this list and in this project.
Perhaps someone in this list knows and is willing to
explain me...
What's the difference between a access point and a
wireless network card in a pc/laptop?
I mean, is there a
On 9/12/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:
Hi,
I am a student and I carry out a degree thesis about SDR in particular FPGA. I
have seen some modules of FPGA but I haven't understood however these modules
are interconnected between them.
Could you give me any informations?
If you
On 9/11/07, S Mande [EMAIL PROTECTED] wrote:
Hi,
I scanned the Mailing List Archive and figured out that the code that goes
inside USRP FPGA is Verilog code.
I personally know VHDL and was looking to make some changes to the FPGA
code.
I was wondering if it is possible for the existing
On 9/7/07, Justin Shaw [EMAIL PROTECTED] wrote:
I think I have a misunderstanding regarding tuning the USRP.
I have connected the TX-A directly to RX-A. I am plotting the FFT of
both the transmitted and received signal. I have tuned RX to 0 Hertz
so I expect the positive frequencies to look
Something you may want to try to do is focus on the TX side of things.
RX is generally the harder part of radio communications, and probably
wouldn't work out too well inside of an FPGA that is already pretty
full. TX on the other hand is all just simple permutations, look up
tables, and maybe
On 8/30/07, Ismail Mohamed [EMAIL PROTECTED] wrote:
Hi again,
Recently there has been talk about the I and Q components of the
signal. I understand the analytic signal concept, also the
implementation as shown on:
http://gnuradio.org/trac/wiki/UsrpRfxDiagrams
where it says,
Right idea,
On 8/20/07, Chris Stankevitz [EMAIL PROTECTED] wrote:
Does it come with a debugger? I'd love to get into it, but things like
learning how to debug/compile/etc are what scare me personally.
Sure, check out Icarus Verilog and GTKWave. You basically write a
testbench to stimulate your inputs, and
On 8/15/07, Richard Meston [EMAIL PROTECTED] wrote:
Actually, I'd be very interested in this as well. Especially if it
worked under Windoze. Something that will just configure and grab data
from the USRP into a buffer would be fantastic.
Any ideas anyone?
Currently marked as a work in
On 8/14/07, George Nychis [EMAIL PROTECTED] wrote:
I don't know if $33 is expensive or not for this type of thing. Where
do you purchase your connectors and cables?
I think Universal Radio has some decent stuff, but they may not have
EVERYTHING you're looking for.
On 8/7/07, Reid N Kleckner [EMAIL PROTECTED] wrote:
Hello,
I've written a small Verilog module for the FPGA on the USRP to do phase
recovery. I'd like to test it in isolation before I try it out on the board,
but I'm having major problems feeding Quartus two 16 bit sine and cosine
signals
On 8/7/07, Zhuocheng Yang [EMAIL PROTECTED] wrote:
Hi guys:
I noticed that in the adc_interface, there are registers called rssi_0,
rssi_1, rssi_2, and rssi_3. All of which are 32 bits. However, according to
the header format:
On 8/7/07, Johnathan Corgan [EMAIL PROTECTED] wrote:
It's a digital RSSI value, meaning it's based on the output of the ADC
and not the true RF power at the antenna. Furthermore, it's really a
single pole low pass averaging filter on the absolute value of the ADC
value, with no way to adjust
On 8/3/07, Zhuocheng Yang [EMAIL PROTECTED] wrote:
Hi guys:
Here is the problem. If I receive a packet whose timestamp is out of date, I
trash the packet. If there are packets afterwards that is a continuation of
the first packet, I should trash those as well despite the fact that their
On 8/3/07, George Nychis [EMAIL PROTECTED] wrote:
Second question. For an application to properly timestamp outgoing
packets, the application needs some general idea of the current clock
value on the USRP. At first I was thinking oh well the app can just
send a ping and read the timestamp
On 8/2/07, Zhuocheng Yang [EMAIL PROTECTED] wrote:
Hi Everyone:
This is a follow up of yesterday's start/end of burst issues. I have created
a testbench to test my code. See attachment for details(only 4 files).
I didn't receive an attachment - could you commit to your SVN branch?
Brian
On 8/2/07, George Nychis [EMAIL PROTECTED] wrote:
The mailing list monster probably ate it for good reason!
I committed the files to leos branch:
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test
Other than that, I know nothing about them ;)
On 8/1/07, George Nychis [EMAIL PROTECTED] wrote:
Ok, so on to the code:
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/burst/usrp/fpga/inband_lib/chan_fifo_reader.v
As a general rule, you shouldn't have dangling if-else statements
meaning where there's an if, there's an
On 7/24/07, Michael P Buettner [EMAIL PROTECTED] wrote:
Hello folks. I am currently looking at using the USRP for interaction with RFID
tags. The crux of the problem is that I need to transmit a continuous carrier wave
to power the tag, but I also need very low latency with respect to
On 7/19/07, Dong Li [EMAIL PROTECTED] wrote:
We've checked the interface of USRP, its SMA Female, and nearly all
the antenna's interface for wireless which are sold in Fry's
Electronics is SMA Reverse Plug. So I guess a adapter from SMA Male to
SMA Reverse Jack will connector the USRP's RF end
On 7/18/07, Kim Toms [EMAIL PROTECTED] wrote:
Arrow has designed a new demonstration card for the Cyclone III FGPA from
Altera. I attended one of the seminars yesterday. The board contains many
peripherals, an EP3C25F324 FPGA, 1Gb SD Card, 96x64 pixel bit mapped OLED
display, audio out,
On 7/16/07, Zhuocheng Yang [EMAIL PROTECTED] wrote:
Hi guys:
My name is Zhuocheng Yang, you can call me Leo. I am pretty new to gnuradio,
started working on it a month ago. Since Thibaud has gone back to Switzerland,
I will be taking over his work. I am currently trying to process the control
On 7/16/07, George Nychis [EMAIL PROTECTED] wrote:
So I think what Leo is getting at is how to actually perform the read or
the write to a register for the C/S packets. For instance we have the
read/write register commands where the application says read from
register X or write this data to
On 7/10/07, Roshan Baliga [EMAIL PROTECTED] wrote:
I noticed the excitement yesterday, then found this tidbit at the bottom
of their software page:
(*) GPS position calculation and, also for regulatory reasons, firmware
contained in peripheral chips are the only exceptions. Those components
On 6/28/07, Trond Danielsen [EMAIL PROTECTED] wrote:
Hi,
after having read several papers on the subject, I am still not able
to find the answer I am looking for. I wonder how to calculate the
frequency resolution of the CORDIC algorithm. In an earlier post to
this mailing list it was stated
On 6/28/07, George Nychis [EMAIL PROTECTED] wrote:
I'm beginning to think that the response should be sent back on the TX
port the command was sent on... because what happens when an application
owns more than 1 RX channel? Even if we went by owner, the application
doesn't exactly know which RX
On 6/25/07, George Nychis [EMAIL PROTECTED] wrote:
This is a perfect question for Eric, but unfortunately he is on
vacation. So I'm hoping that maybe Brian or someone can answer who was
involved in the initial design of the inband USB packets :)
I'll do my best to figure it out.
The way we
On 6/21/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:
Is there a software flag in the code I can switch off? If so, where?
http://gnuradio.org/trac/wiki/UsrpFPGA
Under Common Registers:
15 FR_DC_OFFSET_CL_EN DC offset control loop enable
Brian
On 6/18/07, Jeffrey Karrels [EMAIL PROTECTED] wrote:
Another quick question. I can now see that after the amplitude ramp
up that there is a short section of negative phase movement (.7
radians clockwise) prior to the remaining counterclockwise rotations.
Should I expect a full (-pi/2) to start
On 6/18/07, Brian Padalino [EMAIL PROTECTED] wrote:
GMSK has a certain level of ISI built into the waveform. 0.7 radians
is about a pi/2 shift (0.2228 versus 0.25?) which would be pretty darn
close.
Whoops - looks like I've got QPSK on the brain today. Sorry about that.
Not really sure why
On 6/16/07, John Kent [EMAIL PROTECTED] wrote:
Are they using a NIOS processor for the USB interface by any chance ?
No, a Cypress FX2 is used for the USB MAC/PHY. I believe the next
design is going to have an opencores processor within it.
It sounds like the Altera device more closely
On 6/15/07, John Kent [EMAIL PROTECTED] wrote:
I am an amateur radio enthusiast, and am interested in implementing
Digital TV. I believe, reading the GNU Radio web site, that that was one
of the motivations of some of the members here. I have seen some screen
shots of HDTV receiver pictures on
On 6/14/07, micael magpayo [EMAIL PROTECTED] wrote:
Hello GNURadio community,
I'm really interested in the GNURadio project and I want to have a better
understanding of the FPGA code (usrp_std.v etc...). I've been trying to
learn it on my own but some parts are hard to understand when all you
On 6/14/07, S Mande [EMAIL PROTECTED] wrote:
Hi All,
I have worked with VHDL for 3 years and would want to make use my knowledge
to do some research in Software defined Radio.
I have a very different problem from most of the other postings. I am
actually looking for a 'problem'.
For the
On 5/18/07, Brett L. Trotter [EMAIL PROTECTED] wrote:
I'm involved with very lossy links and low signal strengths using gmsk
and dqpsk and would like to add a layer of reed-solomon encoding in
place of the current CRC check.
My plan was to use reed solomon in a standard (255,223) configuration
On 5/17/07, Eng. Firas [EMAIL PROTECTED] wrote:
Hello,
I can give you a precise MATLAB based simulated USRP frequency response. All
what I need is the HBF coefficients. So this is an open invitation to our
dear Matt to give us his designed USRP HBF coefficients or frequency
response.
Reading
On 5/8/07, Jeffrey Karrels [EMAIL PROTECTED] wrote:
Hello.
I have an array in MATLAB that is the IQ data in complex form of a
capture from my hardware. I wish to now feed this to GNURadio. What
format do I export/save this array to file? Are there any example .m
files floating around for this
On 5/8/07, Håvard Espeland [EMAIL PROTECTED] wrote:
We're writing a gmsk radio module with low bitrate (5 kbps) and
continuous constant bitrate transmission using Gnuradio 3.0.3 and USRP.
The code is based on the digital/tx_voice.py example, and I have two
unanswered questions.
By hacking on
On 5/1/07, Dan Halperin [EMAIL PROTECTED] wrote:
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Hey all,
Sorry to bring up painful memories :). I did some calculations to work
out frequency drift of the USRPs, and I wanted to know where I'm going
wrong.
The crystals in the RFX 2400 are spec'ed
When the FX2 detects the have_space pin on the FPGA, does it transfer
1 entire buffered USB packet to the FPGA, then re-check the have_space
pin?
Would it be reasonable to assume a 1 clock delay between the last byte
of one 512-byte packet being written to the FPGA and the first byte of
a second
On 4/23/07, Thibaud Hottelier [EMAIL PROTECTED] wrote:
I don't know :) What kind of problem should I expect when trying to go
from simulation to reality ?
I'd run more simulations where there are a massive number of packets
waiting to be sent, schedule things too close to each other, make the
On 4/22/07, Eng. Firas [EMAIL PROTECTED] wrote:
Thank you Brian, Matt.
If the CIC starts linearly from 4 to 128, and followed by decimate by 2 Half
Band Filter (HBF) Then [CIC+HBF] should give us the following range
[8,10,12,14,...,256], and not the range [2,4,6,8,..,256] , is
this
On 4/22/07, Eng. Firas [EMAIL PROTECTED] wrote:
Dear Matt,
Dear All,
Is the DDC decimate by 2 half band filter built inside the FPGA ? If it is
so, then how much the free available FPGA resources left after building all
the present USPR circuits in it? I mean, is there a free space to modify
On 4/22/07, Thibaud Hottelier [EMAIL PROTECTED] wrote:
Brian Padalino wrote:
I have just refactored the code so that the fifos are out of the
readers. I also added samples format handling (only 16 bits interleaved
complex so far). I am looking forward to testing this; George told me he
On 4/21/07, Thibaud Hottelier [EMAIL PROTECTED] wrote:
Ok, I move the FIFOs outside next time I refactor this.
Perfect.
Yes, it makes much more sense. In the current design, the strobes are
generated by a separated block; would it be more logical to make the
strobes be generated by the
On 4/20/07, Thibaud Hottelier [EMAIL PROTECTED] wrote:
Hi,
I moved all my small testing blocks from ModelSim to the Quartus source
tree. I am writing the glue code between the modules so we should have
the basic Tx functionality working relatively soon. But before that, I
would like to simulate
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