https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/93267
musttail does not often possible to be generated on PPC targets as when calling
to a function defined in another module, PPC needs to restore the TOC pointer.
To restore the TOC pointer, compiler needs to
@@ -3833,6 +3833,11 @@ def note_cannot_use_trivial_abi_reason : Note<
"it is polymorphic|"
"it has a base of a non-trivial class type|it has a virtual base|"
"it has a __weak field|it has a field of a non-trivial class type}1">;
+def warn_ppc_musttail_maybe_ignored: Warni
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/93267
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>From 751d80c61f0e42daa3796a8270e186153dd9413f Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 22 May 2024 02:37:04 -0400
Subject: [PATCH 1/3] [PowerPC] Support -fpatchable-function-entry
For now only
https://github.com/chenzheng1030 commented:
> So PPC64 can use ELFv2 for Triple::OpenBSD. We probably want to diagnose this
> OS for PPC64, since with ELFv2 we might emit separate local and global entry
> points which means only certain values can be passed to
> -fpatchable-function-entry opti
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s
--check-prefixes=CHECK,PPC32
chenzheng1030 wrote:
Thank you, changed the triple. Little endian is not going to be supported in
this patch.
https://github.com/llvm/llvm-proje
@@ -6681,7 +6681,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
StringRef S0 = A->getValue(), S = S0;
unsigned Size, Offset = 0;
if (!Triple.isAArch64() && !Triple.isLoongArch() && !Triple.isRISCV() &&
-!Triple.isX86())
+!Triple.
https://github.com/chenzheng1030 edited
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@@ -0,0 +1,4 @@
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -fsyntax-only -verify %s
+
+// expected-error@+1 {{'patchable_function_entry' attribute is not yet
supported on AIX}}
+__attribute__((patchable_function_entry(0))) void f();
chenzheng1030 wrote:
@@ -6,15 +6,20 @@
// RUN: %clang -target loongarch64 %s -fpatchable-function-entry=1,0 -c -###
2>&1 | FileCheck %s
// RUN: %clang -target riscv32 %s -fpatchable-function-entry=1,0 -c -### 2>&1
| FileCheck %s
// RUN: %clang -target riscv64 %s -fpatchable-function-entry=1,0 -c
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s
--check-prefixes=CHECK,PPC32
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu %s -o - | FileCheck %s
--check-prefixes=CHECK,PPC64
+
+define void @f0() {
+; CHECK-LABEL: f0:
+; CHECK-NOT: nop
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/92997
>From 7c1e44455a343cef3c5ab0da22c9971888cf Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 22 May 2024 02:37:04 -0400
Subject: [PATCH 1/3] [PowerPC] Support -fpatchable-function-entry
For now only
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/93267
>From 17505893b2b48969512e3c2e8433a6446429f65e Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Thu, 23 May 2024 22:59:48 -0400
Subject: [PATCH 1/2] [PowerPC] Diagnose musttail instead of crash inside
backe
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/93267
>From 17505893b2b48969512e3c2e8433a6446429f65e Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Thu, 23 May 2024 22:59:48 -0400
Subject: [PATCH 1/2] [PowerPC] Diagnose musttail instead of crash inside
backe
chenzheng1030 wrote:
Patch updated...
https://github.com/llvm/llvm-project/pull/93267
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Author: Chen Zheng
Date: 2024-05-29T21:52:55-04:00
New Revision: 2b1d1c51f6e321267cc86e9db7808298c59caf0e
URL:
https://github.com/llvm/llvm-project/commit/2b1d1c51f6e321267cc86e9db7808298c59caf0e
DIFF:
https://github.com/llvm/llvm-project/commit/2b1d1c51f6e321267cc86e9db7808298c59caf0e.diff
LO
chenzheng1030 wrote:
PPC buildbot fails at another place with above fix:
https://lab.llvm.org/buildbot/#/builders/230/builds/29066
Commit 2b1d1c51f6e321267cc86e9db7808298c59caf0e to fix the failure.
https://github.com/llvm/llvm-project/pull/81545
___
@@ -743,6 +743,20 @@ bool Sema::checkMustTailAttr(const Stmt *St, const Attr
&MTA) {
CallerType.Func = CallerDecl->getType()->getAs();
}
+ if (Context.getTargetInfo().getTriple().isPPC()) {
+if (Context.getTargetInfo().getTriple().isOSAIX())
+ return Diag(St->
https://github.com/chenzheng1030 deleted
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@@ -743,6 +743,20 @@ bool Sema::checkMustTailAttr(const Stmt *St, const Attr
&MTA) {
CallerType.Func = CallerDecl->getType()->getAs();
}
+ if (Context.getTargetInfo().getTriple().isPPC()) {
+if (Context.getTargetInfo().getTriple().isOSAIX())
+ return Diag(St->
@@ -743,6 +743,20 @@ bool Sema::checkMustTailAttr(const Stmt *St, const Attr
&MTA) {
CallerType.Func = CallerDecl->getType()->getAs();
}
+ if (Context.getTargetInfo().getTriple().isPPC()) {
+if (Context.getTargetInfo().getTriple().isOSAIX())
+ return Diag(St->
https://github.com/chenzheng1030 commented:
Are there backend cases that shows with -disable-red-zone, the final assembly
is still correct?
https://github.com/llvm/llvm-project/pull/94581
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chenzheng1030 wrote:
> No. `-disable-red-zone` does nothing but add `noredzone` IR attribute to
> functions. We need to add cases to test for `noredzone` behavior on PPC (arm
> and x86 have).
Yeah, go ahead to add some backend tests first to make sure we have good
functionality for `noredzone
https://github.com/chenzheng1030 approved this pull request.
The small LIT cases seem all good. Based on that, the patch LGTM.
If possible, can you run some big applications with `-mno-redzone` to double
confirm the functionality? I am not so sure about its quality since the option
seems not b
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/96109
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@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-unknown-unknown -verify %s
chenzheng1030 wrote:
nit: can you also add run lines for AIX 32 and 64 bit?
https://github.com/llvm/llvm-project/pull/96109
https://github.com/chenzheng1030 approved this pull request.
LGTM except a nit.
https://github.com/llvm/llvm-project/pull/96109
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>From 6047403b41bdeef8cd16294f0538150b8c58f6ea Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Thu, 23 May 2024 22:59:48 -0400
Subject: [PATCH 1/3] [PowerPC] Diagnose musttail instead of crash inside
backe
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/93267
>From 6047403b41bdeef8cd16294f0538150b8c58f6ea Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Thu, 23 May 2024 22:59:48 -0400
Subject: [PATCH 1/3] [PowerPC] Diagnose musttail instead of crash inside
backe
@@ -743,6 +743,20 @@ bool Sema::checkMustTailAttr(const Stmt *St, const Attr
&MTA) {
CallerType.Func = CallerDecl->getType()->getAs();
}
+ if (Context.getTargetInfo().getTriple().isPPC()) {
+if (Context.getTargetInfo().getTriple().isOSAIX())
+ return Diag(St->
Author: Chen Zheng
Date: 2022-12-25T21:01:02-05:00
New Revision: b1d7010caa4394e7f5b41c627702f6acabe0cec5
URL:
https://github.com/llvm/llvm-project/commit/b1d7010caa4394e7f5b41c627702f6acabe0cec5
DIFF:
https://github.com/llvm/llvm-project/commit/b1d7010caa4394e7f5b41c627702f6acabe0cec5.diff
LO
chenzheng1030 wrote:
> Is it possible that we fix the hack implementation with some future version
> (I will open an issue and work on it afterwards)? How about let's move on
> with current approach?
> @amy-kwan @stephenpeckham @bzEq @chenzheng1030 Appreciate your comments.
> Thank you!
I am
chenzheng1030 wrote:
The code formatting check fails.
https://github.com/llvm/llvm-project/pull/66316
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https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/68476
Extend `PPCTargetInfo::getGCCAddlRegNames()` to aix as well. The definition
should be common between Linux PPC and AIX PPC.
I also use "abi" as the ABI name for AIX ABI. This aligns with LLVM
PPCSubtarget
https://github.com/chenzheng1030 edited
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>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/2] [AIX] recognize vsr in inline asm for AIX
---
clang/lib/B
@@ -807,6 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs o
@@ -2,6 +2,10 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | F
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
This is what I
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/68476
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https://github.com/chenzheng1030 approved this pull request.
Make sense to me. Thanks.
https://github.com/llvm/llvm-project/pull/68681
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@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
- else
-return TargetInfo::getGCCAddlRegNames();
+ return llvm::ArrayRef(G
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
FP and VMX reg
https://github.com/chenzheng1030 edited
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@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
@hubert-reinte
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/68476
>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/3] [AIX] recognize vsr in inline asm for AIX
---
clang/lib/B
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
Done.
https:/
https://github.com/chenzheng1030 closed
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Author: Chen Zheng
Date: 2023-04-14T06:24:57-04:00
New Revision: 4b0a25375e9006ef82cc51119ff223a28bb15646
URL:
https://github.com/llvm/llvm-project/commit/4b0a25375e9006ef82cc51119ff223a28bb15646
DIFF:
https://github.com/llvm/llvm-project/commit/4b0a25375e9006ef82cc51119ff223a28bb15646.diff
LO
Author: Chen Zheng
Date: 2023-06-04T21:37:48-04:00
New Revision: 4b27ad735c8da7cd21a7ea58614ebd4d3c940a89
URL:
https://github.com/llvm/llvm-project/commit/4b27ad735c8da7cd21a7ea58614ebd4d3c940a89
DIFF:
https://github.com/llvm/llvm-project/commit/4b27ad735c8da7cd21a7ea58614ebd4d3c940a89.diff
LO
Author: Chen Zheng
Date: 2023-06-05T04:00:26-04:00
New Revision: 225cf64e03b4e394c32e95fe1d6414e6e16be094
URL:
https://github.com/llvm/llvm-project/commit/225cf64e03b4e394c32e95fe1d6414e6e16be094
DIFF:
https://github.com/llvm/llvm-project/commit/225cf64e03b4e394c32e95fe1d6414e6e16be094.diff
LO
Author: Chen Zheng
Date: 2023-06-05T05:02:38-04:00
New Revision: b447dc5a4704bef8ced95495aa8d9ea477a26814
URL:
https://github.com/llvm/llvm-project/commit/b447dc5a4704bef8ced95495aa8d9ea477a26814
DIFF:
https://github.com/llvm/llvm-project/commit/b447dc5a4704bef8ced95495aa8d9ea477a26814.diff
LO
https://github.com/chenzheng1030 approved this pull request.
LGTM. Thanks for adding this support.
https://github.com/llvm/llvm-project/pull/97524
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https://github.com/llvm/llvm-project/pull/99511
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@@ -672,6 +685,8 @@ def : ProcessorModel<"pwr7", P7Model,
ProcessorFeatures.P7Features>;
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
def : ProcessorModel<"pwr10", P10Model, ProcessorF
https://github.com/chenzheng1030 commented:
Basically you need to handle P11 for all the places where P10 is handled, seems
you are missing below places:
1: we need handling in `LoadOpcodesForSpill` and `StoreOpcodesForSpill` for
P11. Even for now P11 may already use the model of P10, we need a
https://github.com/chenzheng1030 commented:
We also need more tests like:
1: `llvm/test/CodeGen/PowerPC/check-cpu.ll`
2: at least one test in the backend like
`llvm/test/CodeGen/PowerPC/p10-constants.ll`?
https://github.com/llvm/llvm-project/pull/99511
__
@@ -84,6 +85,7 @@
#define AIX_PPC8_VALUE 0x0001
#define AIX_PPC9_VALUE 0x0002
#define AIX_PPC10_VALUE 0x0004
+#define AIX_PPC11_VALUE 0x0008
chenzheng1030 wrote:
Where did you get this value? Is it documented somewhere? From the latest AIX
7.3
@@ -103,6 +105,7 @@ PPC_CPU("ppc476",SYS_CALL,44,BUILTIN_PPC_FALSE,0)
PPC_CPU("power8",SYS_CALL,45,USE_SYS_CONF,AIX_PPC8_VALUE)
PPC_CPU("power9",SYS_CALL,46,USE_SYS_CONF,AIX_PPC9_VALUE)
PPC_CPU("power10",SYS_CALL,47,USE_SYS_CONF,AIX_PPC10_VALUE)
+PPC_CPU("power11",SYS_CALL,48,U
chenzheng1030 wrote:
ping : )
Sorry, I may commit this directly if I don't get any further comments. I have
follow up patches based on this one. Thanks.
https://github.com/llvm/llvm-project/pull/97541
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https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/99511
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https://github.com/chenzheng1030 approved this pull request.
LGTM except one nit. Thanks very much for adding this support.
https://github.com/llvm/llvm-project/pull/99511
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@@ -3485,9 +3485,11 @@ unsigned PPCInstrInfo::getSpillTarget() const {
// With P10, we may need to spill paired vector registers or accumulator
// registers. MMA implies paired vectors, so we can just check that.
bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.paire
Author: Chen Zheng
Date: 2024-07-23T01:53:21-04:00
New Revision: ee07547487a3502f7436968bbfc243b054c14071
URL:
https://github.com/llvm/llvm-project/commit/ee07547487a3502f7436968bbfc243b054c14071
DIFF:
https://github.com/llvm/llvm-project/commit/ee07547487a3502f7436968bbfc243b054c14071.diff
LO
chenzheng1030 wrote:
ee07547487a3502f7436968bbfc243b054c14071 should be able to fix the `No
available targets are compatible with triple "powerpc64-ibm-aix"` error.
https://github.com/llvm/llvm-project/pull/99888
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Author: Chen Zheng
Date: 2024-07-23T02:00:28-04:00
New Revision: b830790547c304aa2a771ce0706b337ea5ec7a02
URL:
https://github.com/llvm/llvm-project/commit/b830790547c304aa2a771ce0706b337ea5ec7a02
DIFF:
https://github.com/llvm/llvm-project/commit/b830790547c304aa2a771ce0706b337ea5ec7a02.diff
LO
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/97541
>From abe45fe2c6540534bfbd2f452240cc73b273e905 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH] [PowerPC] add TargetParser for PPC target For now only focus
o
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/97541
>From 3b7cd8f6fc046ed28f9e329ba0f26156477c0a17 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH] [PowerPC] add TargetParser for PPC target For now only focus
o
https://github.com/chenzheng1030 commented:
```
def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true",
"Enable classic FPU instructions",
[FeatureHardFloat]>;
def FeatureAltivec : SubtargetFeature<"altivec",
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/97541
>From 95b653b6a8f65c04eda610761e52772cb4f8ba35 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH] [PowerPC] add TargetParser for PPC target For now only focus
o
https://github.com/chenzheng1030 closed
https://github.com/llvm/llvm-project/pull/97541
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Author: Chen Zheng
Date: 2024-07-25T10:13:45-04:00
New Revision: daf9d7f3881e4ffd1fd5988dc1b6223c733b6bef
URL:
https://github.com/llvm/llvm-project/commit/daf9d7f3881e4ffd1fd5988dc1b6223c733b6bef
DIFF:
https://github.com/llvm/llvm-project/commit/daf9d7f3881e4ffd1fd5988dc1b6223c733b6bef.diff
LO
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/100450
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@@ -0,0 +1,26 @@
+// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr10 -msoft-float -S
-emit-llvm %s -o - | FileCheck %s -check-prefix=CHECKSOFT
+// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr10 -S -emit-llvm %s
-o - | FileCheck %s -check-prefix=CHECKNOSOFT
+
https://github.com/chenzheng1030 commented:
Compared with `llvm/lib/Target/PowerPC/PPC.td`, seems still miss below implicit
flag:
`crypto`
```
def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
"Enable POWER8 Crypto instructions",
@@ -0,0 +1,26 @@
+// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr10 -msoft-float -S
-emit-llvm %s -o - | FileCheck %s -check-prefix=CHECKSOFT
+// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr10 -S -emit-llvm %s
-o - | FileCheck %s -check-prefix=CHECKNOSOFT
+
@@ -562,7 +562,7 @@ void AIX::addClangTargetOptions(
CC1Args.push_back("-fno-sized-deallocation");
if (Args.hasFlag(options::OPT_ferr_pragma_mc_func_aix,
- options::OPT_fno_err_pragma_mc_func_aix, false))
+ options::OPT_fno_err_pragma_
@@ -562,7 +562,7 @@ void AIX::addClangTargetOptions(
CC1Args.push_back("-fno-sized-deallocation");
if (Args.hasFlag(options::OPT_ferr_pragma_mc_func_aix,
- options::OPT_fno_err_pragma_mc_func_aix, false))
+ options::OPT_fno_err_pragma_
https://github.com/chenzheng1030 commented:
LGTM. Please wait for @AaronBallman 's approval. Thanks
https://github.com/llvm/llvm-project/pull/101336
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https://github.com/llvm/llvm-project/pull/100450
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https://github.com/chenzheng1030 commented:
We still miss many implications in `PPCTargetInfo::setFeatureEnabled()`. This
patch fixes the implications for `-msoft-float`. But implications like
`-mno-power8-altivec` for `-crypto` is still not handled.
Let's leave them for now and make this patc
@@ -690,6 +698,19 @@ bool PPCTargetInfo::initFeatureMap(
return false;
}
+ if (llvm::is_contained(FeaturesVec, "-hard-float")) {
chenzheng1030 wrote:
After another look, I still think this should be done in
https://github.com/llvm/llvm-project/blob/ma
@@ -0,0 +1,58 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
@@ -0,0 +1,58 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/101390
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@@ -0,0 +1,75 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
@@ -0,0 +1,58 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
https://github.com/chenzheng1030 approved this pull request.
LGTM. Thanks for the offline discussion @lei137
https://github.com/llvm/llvm-project/pull/101390
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https://github.com/chenzheng1030 approved this pull request.
LGTM. Thanks for making the fix.
https://github.com/llvm/llvm-project/pull/100450
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@@ -439,14 +443,12 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
// FIXME: The following are not yet generated here by Clang, but are
//generated by GCC:
//
- // _SOFT_FLOAT_
// __RECIP_PRECISION__
// __APPLE_ALTIVEC__
// __RE
@@ -402,9 +402,16 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__VEC__", "10206");
Builder.defineMacro("__ALTIVEC__");
}
- if (HasSPE) {
+ if (HasSPE)
Builder.defineMacro("__SPE__");
+ if (HasSPE || FloatABI == SoftFlo
https://github.com/chenzheng1030 approved this pull request.
LGTM now. Thanks very much for the fix.
https://github.com/llvm/llvm-project/pull/106012
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