preames wrote:
Why? There has only ever been one version of the features array, and that has
not yet been published. Why do we need a version check here at all?
https://github.com/llvm/llvm-project/pull/110098
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https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/109651
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@@ -10319,8 +10319,10 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D,
DeclContext *DC,
// Handle attributes.
ProcessDeclAttributes(S, NewFD, D);
const auto *NewTVA = NewFD->getAttr();
- if (NewTVA && !NewTVA->isDefaultVersion() &&
- !Context.getTargetInfo
@@ -11027,13 +11029,27 @@ static bool CheckMultiVersionValue(Sema &S, const
FunctionDecl *FD) {
}
if (TVA) {
-llvm::SmallVector Feats;
-TVA->getFeatures(Feats);
-for (const auto &Feat : Feats) {
- if (!TargetInfo.validateCpuSupports(Feat)) {
-S.Di
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/99040
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https://github.com/preames approved this pull request.
LGTM
(I only did a quick pass on this version assuming mostly unchanged from prior.
Wanted to explicitly chime in with support for the priority syntax.)
https://github.com/llvm/llvm-project/pull/85786
_
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/85786
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preames wrote:
@BeMg Can you rebase over commit
[d1e28e2](https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59)?
https://github.com/llvm/llvm-project/pull/85786
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ht
preames wrote:
I've gone ahead and merged this into main. We have missed the branch creation,
so without further action this will not be included in 19.x. We need to ensure
the constructor change for compiler-rt lands, and then backport them together
if we choose to.
https://github.com/ll
https://github.com/preames closed
https://github.com/llvm/llvm-project/pull/99700
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LGTM
https://github.com/llvm/llvm-project/pull/99898
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@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/99700
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https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/4] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_su
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/3] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_su
@@ -1020,3 +1020,64 @@ std::string
RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+struct RISCVExtBit {
+ const StringRef ext;
+ uint64
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/2] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_su
preames wrote:
I have posted a cut down version of this which implements
__builtin_cpu_supports and __builtin_cpu_init. I posted an early draft to
avoid potentially duplicated work. If we're going to get any part of this in
for the release branch, we don't have much time. See
https://githu
https://github.com/preames created
https://github.com/llvm/llvm-project/pull/99700
This implements the __builtin_cpu_init and __builtin_cpu_supports builtin
routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.co
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
https://github.com/preames requested changes to this pull request.
At a high level, I think this is a quite a ways from being ready to land.
There's both code style issues (mostly false generality), and missing bits of
the user interface on the clang side. I do not think this has any real ser
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClones
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
@@ -119,6 +119,51 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RI
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/85786
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@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/99070
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preames wrote:
All of the dependent pieces have landed. For ease of future reference:
* https://github.com/llvm/llvm-project/pull/90266 is the attributes emission
(off by default).
* https://github.com/llvm/llvm-project/pull/97347 is the LLD change.
* https://github.com/llvm/llvm-project/pull/8
Author: Philip Reames
Date: 2024-07-09T10:45:56-07:00
New Revision: 90d79e258ee9c6935ffeac405b3e9b74542068aa
URL:
https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa
DIFF:
https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa.diff
@@ -290,8 +290,24 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
&Args,
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "nativ
https://github.com/preames approved this pull request.
LGTM w/minor comments
https://github.com/llvm/llvm-project/pull/94352
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@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "nat
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/94352
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preames wrote:
Once https://github.com/llvm/llvm-project/pull/90266 lands with the attributes
off by default, I think we should move forward with relanding this. We do need
one change though - our TSO lowering unconditionally uses the A6S ABI variant -
right? - so we need to adjust the attrib
preames wrote:
Chatted with @patrick-rivos on the status of TSO. The following is my summary:
* psABI changes have landed which change the default for WMO to what we used to
call the "A6/A7 compatibility table". The TSO change which landed to psABI
defines a mapping which is compatible with t
Author: Philip Reames
Date: 2024-06-24T08:32:28-07:00
New Revision: f985a8826bfa4ca3d23e654185de35e30ea6dc79
URL:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79
DIFF:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79.diff
preames wrote:
> I think @preames told me he was keeping this experimental for a reason.
Yes, revert pending.
The concern here is that there are multiple possible ABIs here, and at the
point I implemented this, the ABI chosen in my initial set of patches was
compatible with the then current W
preames wrote:
Given the concern about breaking configurations w/no-integrated-as and older
binutils, can someone summarize here which versions of binutils are known to
work/not work after this change? This will likely become the key search result
for such breakage, and having it well documen
@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX :
RISCVProcessorModel<"syntacore-scr1-max",
FeatureStdExtC],
[TuneNoDefaultUnroll]>;
+def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacor
preames wrote:
> Will this core have active support on the LLVM side?
I can't speak for the vendor, but I'll say that I'm interested in having this
supported upstream. This looks to be a reasonable rva22 dev board w/V1.0, and
having in tree support seems worthwhile. I've ordered one of these
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/94564
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@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
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@@ -8,7 +8,8 @@
// CHECK: entry:
// CHECK-NEXT: %retval = alloca i32
// CHECK-NEXT: store i32 0, ptr %retval
-// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32
+// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a
+// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
@@ -8,7 +8,8 @@
// CHECK: entry:
// CHECK-NEXT: %retval = alloca i32
// CHECK-NEXT: store i32 0, ptr %retval
-// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32
+// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a
+// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/88538
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LGTM
https://github.com/llvm/llvm-project/pull/88954
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@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
preames wrote:
You do
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/preames commented:
After this was discussed at the sync-up call today, I believe we're in
agreement on direction here. This is close to being ready and is just pending
some code cleanup.
https://github.com/llvm/llvm-project/pull/76357
_
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
preames wrote:
Very minor, but I believe you can use std::pair here instead.
https://github.com/llvm/llvm-project/pull/76357
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c
Author: Philip Reames
Date: 2024-03-13T10:19:42-07:00
New Revision: 13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c
URL:
https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c
DIFF:
https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c.diff
preames wrote:
I agree with @asb's framing above. Assuming this doesn't commit us to
something which is hard to forward version for some reason, I support
addressing this in a target specific manner for the moment.
https://github.com/llvm/llvm-project/pull/80760
_
@@ -3878,6 +3883,130 @@ static Align computeCommonAlignment(ArrayRef
VL) {
return CommonAlignment;
}
+/// Check if \p Order represents reverse order.
+static bool isReverseOrder(ArrayRef Order) {
+ unsigned Sz = Order.size();
+ return !Order.empty() && all_of(enumerate(Or
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef
VL, const Value *VL0,
std::optional Diff =
getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE);
// Check that the sorted loads are consecutive.
- if (static_cast(*Diff) == VL.si
https://github.com/preames commented:
These comments are trying to be helpful in pointing out bits which might be
simplified or split off, but my track record with SLP reviews is not great.
Feel free to ignore any or all of these.
https://github.com/llvm/llvm-project/pull/80310
@@ -30,7 +30,7 @@ define void @test() {
; CHECK-SLP-THRESHOLD: bb:
; CHECK-SLP-THRESHOLD-NEXT:[[TMP0:%.*]] = insertelement <4 x ptr> poison,
ptr [[COND_IN_V]], i32 0
; CHECK-SLP-THRESHOLD-NEXT:[[TMP1:%.*]] = shufflevector <4 x ptr>
[[TMP0]], <4 x ptr> poison, <4
@@ -17,7 +17,7 @@ define i16 @test() {
; CHECK-NEXT:[[TMP4:%.*]] = call <2 x i16>
@llvm.masked.gather.v2i16.v2p0(<2 x ptr> [[TMP3]], i32 2, <2 x i1> , <2 x i16> poison)
; CHECK-NEXT:[[TMP5:%.*]] = extractelement <2 x i16> [[TMP4]], i32 0
; CHECK-NEXT:[[TMP6:%.*]] =
@@ -397,27 +241,12 @@ define void @test3([48 x float]* %p, float* noalias %s) {
; CHECK-NEXT: entry:
; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [48 x float], ptr
[[P:%.*]], i64 0, i64 0
; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr
[[
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef
VL, const Value *VL0,
std::optional Diff =
getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE);
// Check that the sorted loads are consecutive.
- if (static_cast(*Diff) == VL.si
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https://github.com/llvm/llvm-project/pull/80310
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@@ -7,7 +7,7 @@ define i32 @test(ptr noalias %p, ptr noalias %addr) {
; CHECK-NEXT: entry:
; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr
[[ADDR:%.*]], i32 0
; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr>
poison, <8 x i32> ze
preames wrote:
FYI - https://github.com/llvm/llvm-project/pull/80360 adds testing
infrastructure to exercise the TTI hooks.
https://github.com/llvm/llvm-project/pull/80310
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@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp
: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
"'Smepmp' (Enhanced Physical Memory Protection)", []>;
+def FeatureStdExtSsccptr
+: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
+
https://github.com/preames closed
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preames wrote:
> It has been approved to be pursued as a fast track extension
> (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698).
> It has not yet been approved by the chairs.
Works for me. I've edited the PR description to include this information so
tha
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@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp
: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
"'Smepmp' (Enhanced Physical Memory Protection)", []>;
+def FeatureStdExtSsccptr
+: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
+
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp
: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
"'Smepmp' (Enhanced Physical Memory Protection)", []>;
+def FeatureStdExtSsccptr
+: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
+
https://github.com/preames approved this pull request.
LGTM w/comments addressed.
https://github.com/llvm/llvm-project/pull/79399
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https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/79399
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preames wrote:
I think we need some kind of official documentation to merge this. I went
looking to see if I could find mention of this extension in e.g. ARC notes, and
didn't find it. @mehnadnerd can you provide some kind of link or reference to
some RVI source indicating the status of this
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/79911
>From 3344e42d05875269b680b9626cd6cd093e88d81e Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH 1/2] [RISCV][MC] MC layer support for the experimental zalasr
extension
--
https://github.com/preames approved this pull request.
LGTM as well.
https://github.com/llvm/llvm-project/pull/79811
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preames wrote:
Not actively working on this. Anyone interested is welcome to pick up the
patch.
https://github.com/llvm/llvm-project/pull/74770
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https://github.com/preames closed
https://github.com/llvm/llvm-project/pull/74770
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https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/77573
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@@ -96,6 +96,8 @@ on support follow.
``Svnapot`` Assembly Support
``Svpbmt`` Supported
``V``Supported
+ ``Za128rs`` Supported
preames wrote:
I think these may warrant an explanatory note after the table. See what
https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/77645
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https://github.com/preames approved this pull request.
LGTM
We should explore options for merging the option processing code for options
supported by both clang and flang, but that's explicitly future work.
https://github.com/llvm/llvm-project/pull/77588
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