https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75571
>From 2e31cbd1a0b5b9c1689f664c6c261cabbc656f2a Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Fri, 15 Dec 2023 16:11:02 +0800
Subject: [PATCH 1/2] [X86][AVX10] Allow 64-bit mask register used without
EVEX51
phoebewang wrote:
One more reason I can think of is with KNL/KNM removal, we can simplify
supporting widen 128/256-bit vector to 512-bit without AVX512VL feature since
all reset targets support AVX512VL. The test cases can be simplified too.
https://github.com/llvm/llvm-project/pull/75580
https://github.com/phoebewang closed
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phoebewang wrote:
> Can you give me a better idea of the stages you intend to follow with this.
> The patch title suggests removing all KNL/KNM handling but the patch itself
> looks to be just about the KNL/KNM specific features.
>
> Removing the (incomplete) KNL/KNM specific features (ER/PF/e
@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===
phoebewang wrote:
adx -> adc
https://github.com/llvm/llvm-project/pull/75711
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@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===
phoebewang wrote:
adx -> adc
https://github.com/llvm/llvm-project/pull/75992
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/75992
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@@ -92,136 +92,11 @@ __INLINE unsigned char
}
#endif
-/* Intrinsics that are also available if __ADX__ is undefined. */
-
-/// Adds unsigned 32-bit integers \a __x and \a __y, plus 0 or 1 as indicated
-///by the carry flag \a __cf. Stores the unsigned 32-bit sum in the mem
@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
phoebewang wrote:
Sorry, just noticed this
@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
phoebewang wrote:
I think comment is good.
phoebewang wrote:
Thanks @MaxEW707 ! I don't have other comments now. Do you need help to merge
it for you?
https://github.com/llvm/llvm-project/pull/75992
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https://github.com/llvm/llvm-project/pull/75156
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/2] [X86] Add ABI handling for fp128
Fixes #74601
---
clang/li
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
I decided not to report error for `-sse` after investigating the current
diagnosis machinism.
We didn't repo
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
Yes, e.g, `llvm/test/CodeGen/X86/{soft-fp,x87}.ll`, though I doubt if they can
work in reality since they ar
phoebewang wrote:
> I also think we need a policy regarding what test coverage we need for
> various avx512 features (when should we assume avx512vl etc.)
Considering the new evolution in AVX10, we should switch testing model from
`avx512xxx ± avx512vl` to `avx512xxx + avx512vl ±
evex512`.
I
phoebewang wrote:
> Making avx512f the only case where avx512vl can be disabled doesn't seem like
> too much of a stretch to me - we'd be merely making all avx512 extension
> features depend on avx512vl.
Agreed.
https://github.com/llvm/llvm-project/pull/75580
_
phoebewang wrote:
Ping @RKSimon
https://github.com/llvm/llvm-project/pull/75156
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https://github.com/llvm/llvm-project/pull/76901
>From ff9b72bdb5442a037d4325619de66e25ad211586 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 1 Jan 2024 15:13:38 +0800
Subject: [PATCH] [X86][BF16][WIP] Try to use `f16` for lowering
---
llvm/lib/Tar
https://github.com/phoebewang ready_for_review
https://github.com/llvm/llvm-project/pull/76901
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https://github.com/llvm/llvm-project/pull/75156
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/3] [X86] Add ABI handling for fp128
Fixes #74601
---
clang/li
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75156
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/4] [X86] Add ABI handling for fp128
Fixes #74601
---
clang/li
phoebewang wrote:
> Add a Release notes entry? I always forget exactly what we need to do for ABI
> fixes/tweaks
Goot point! Done.
https://github.com/llvm/llvm-project/pull/75156
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@@ -1097,7 +1097,7 @@ def : Pat <
multiclass f16_fp_Pats {
// f16_to_fp patterns
def : GCNPat <
-(f32 (f16_to_fp i32:$src0)),
+(f32 (any_f16_to_fp i32:$src0)),
phoebewang wrote:
Should we replace more `f16_to_fp` to `any_f16_to_fp` in this file and
@@ -2621,6 +2642,29 @@ SDValue
DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
}
+// Explicit operation to reduce precision. Reduce the value to half precision
+// and promote it back to the legal typ
@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
; X86-NEXT:vmovss %xmm0, (%esp)
; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 = mem[0],zero,zer
@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
; X86-NEXT:vmovss %xmm0, (%esp)
; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 = mem[0],zero,zer
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/76901
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phoebewang wrote:
Thanks @FreddyLeaf !
https://github.com/llvm/llvm-project/pull/76901
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@@ -3347,10 +3348,37 @@ void MachineVerifier::verifyLiveRangeSegment(const
LiveRange &LR,
OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
}
+ bool IsEHa = MF->getMMI().getModule()->getModuleFlag("eh-asynch");
while (true) {
assert(LiveInts->isL
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F
@@ -18,7 +18,7 @@ This test serves two purposes:
The list of warnings below should NEVER grow. It should gradually shrink to 0.
-CHECK: Warnings without flags (65):
phoebewang wrote:
The comment says we should not increase it.
https://github.com/llvm/llvm-
@@ -3347,10 +3348,37 @@ void MachineVerifier::verifyLiveRangeSegment(const
LiveRange &LR,
OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
}
+ bool IsEHa = MF->getMMI().getModule()->getModuleFlag("eh-asynch");
while (true) {
assert(LiveInts->isL
@@ -18,7 +18,7 @@ This test serves two purposes:
The list of warnings below should NEVER grow. It should gradually shrink to 0.
-CHECK: Warnings without flags (65):
phoebewang wrote:
Maybe it's not a good example. The test is to prevent adding warnings with
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75156
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/5] [X86] Add ABI handling for fp128
Fixes #74601
---
clang/li
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/75156
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https://github.com/phoebewang approved this pull request.
Looks great, thanks!
https://github.com/llvm/llvm-project/pull/83447
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@@ -0,0 +1,247 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686 --relocation-model=pic -enable-tlsdesc |
FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 --reloc
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/8] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/8] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/83136
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@@ -3014,6 +3014,11 @@ Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF,
Address VAListAddr,
ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
/*isNamedArg*/false);
+ // Empty records are ignored for parameter pas
phoebewang wrote:
Checked both pr77036.cpp and pr77036.c get the same result, so looks like a
right fix. But I want to wait @efriedma-quic to sign off.
https://github.com/llvm/llvm-project/pull/77907
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@@ -207,6 +207,8 @@ _mm256_div_ps(__m256 __a, __m256 __b)
/// Compares two 256-bit vectors of [4 x double] and returns the greater
///of each pair of values.
///
+///If either value in a comparison is NaN, returns the value from \a __b.
phoebewang wrote
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/85862
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@@ -2099,9 +2099,11 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_add_epi64(__m128i __a,
}
/// Adds, with saturation, the corresponding elements of two 128-bit
-///signed [16 x i8] vectors, saving each sum in the corresponding element
of
-///a 128-bit result ve
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/82422
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@@ -2099,9 +2099,11 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_add_epi64(__m128i __a,
}
/// Adds, with saturation, the corresponding elements of two 128-bit
-///signed [16 x i8] vectors, saving each sum in the corresponding element
of
-///a 128-bit result ve
@@ -1845,6 +1845,12 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Fea
phoebewang wrote:
You may also need to transfer "apxf" feature into subfeatures here
https://github.com/llvm/llvm-project/blob/main/clang/lib/Basic/Targets/X86.cpp#L106
https://github.com/llvm/llvm-project/pull/80636
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@@ -2099,9 +2099,11 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_add_epi64(__m128i __a,
}
/// Adds, with saturation, the corresponding elements of two 128-bit
-///signed [16 x i8] vectors, saving each sum in the corresponding element
of
-///a 128-bit result ve
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/82422
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/83136
None
>From 421a5e4c0a6d7beda71118a36650e72c3d6f2377 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH] [X86] Add Support for X86 TLSDESC Relocations
---
clang/
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH] [X86] Add Support for X86 TLSDESC Relocations
---
clang/lib/Dr
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/2] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
@@ -18515,17 +18515,17 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
return LowerGlobalOrExternal(Op, DAG, /*ForCall=*/false);
}
-static SDValue
-GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
- SDValue *InG
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
phoebewang wrote:
Done
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-pc-linu
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/83316
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/3] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-pc-linu
@@ -2180,7 +2180,8 @@ _mm256_cvtepi32_pd(__m128i __a)
return (__m256d)__builtin_convertvector((__v4si)__a, __v4df);
}
-/// Converts a vector of [8 x i32] into a vector of [8 x float].
+/// Converts a vector of [8 x i32] into a vector of [8 x float]. Rounds inexact
+///re
@@ -2211,7 +2213,12 @@ _mm256_cvtpd_ps(__m256d __a)
return (__m128)__builtin_ia32_cvtpd2ps256((__v4df) __a);
}
-/// Converts a vector of [8 x float] into a vector of [8 x i32].
+/// Converts a vector of [8 x float] into a vector of [8 x i32]. Rounds inexact
+///results a
phoebewang wrote:
This is a turbulent change to both upstream and downstream tests without any
profit as far as I can tell.
I did a similar change for 64-bit a few years ago:
https://reviews.llvm.org/D129647
In comparison, this patch is not to solve a specific problem. It should not
show any
phoebewang wrote:
Ping~
https://github.com/llvm/llvm-project/pull/83136
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/87149
We have many problems to use CodeView for a win32-elf target, e.g., #87140 and
`error: .seh_* directives are not supported on this target`.
Fixes: #87140
>From 745b2acb9dafbb54b00353f71dee464b3617c13a Mon Se
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/87149
>From 16fea4659909423319f0107b2a4d5bcc31185299 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Sat, 30 Mar 2024 17:29:06 +0800
Subject: [PATCH] [Win32][ELF] Make CodeView a DebugInfoFormat only for COFF
form
Author: Phoebe Wang
Date: 2024-04-03T16:10:19+08:00
New Revision: cd7517859eef14d8b38cec2d52c0625a58c645a2
URL:
https://github.com/llvm/llvm-project/commit/cd7517859eef14d8b38cec2d52c0625a58c645a2
DIFF:
https://github.com/llvm/llvm-project/commit/cd7517859eef14d8b38cec2d52c0625a58c645a2.diff
L
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/87987
This relands #87149.
The previous commit exposed failures on some targets. The reason is only a few
targets support COFF ObjectFormatType on Windows:
https://github.com/llvm/llvm-project/blob/main/llvm/lib/T
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/87987
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https://github.com/llvm/llvm-project/pull/88101
Fixes #62449
>From 66c4383e58cab7cf893edfa3f3507be166116fa6 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 9 Apr 2024 16:08:55 +0800
Subject: [PATCH] [SEH] Ignore async exception flag when the environm
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/87987
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Author: Phoebe Wang
Date: 2024-04-10T14:40:07+08:00
New Revision: 299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6
URL:
https://github.com/llvm/llvm-project/commit/299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6
DIFF:
https://github.com/llvm/llvm-project/commit/299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6.diff
L
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/88245
This is a second try to reland https://github.com/llvm/llvm-project/pull/87149.
The previous commit exposed failures on some targets. The reason is only a few
targets support COFF ObjectFormatType on Windows:
@@ -2,12 +2,20 @@
// RUN: %clang_cc1 -E -triple i386 -dM -o - -fcf-protection=branch %s |
FileCheck %s --check-prefix=BRANCH
// RUN: %clang_cc1 -E -triple i386 -dM -o - -fcf-protection=full %s |
FileCheck %s --check-prefix=FULL
// RUN: not %clang_cc1 -emit-llvm-only -triple
@@ -2,12 +2,20 @@
// RUN: %clang_cc1 -E -triple i386 -dM -o - -fcf-protection=branch %s |
FileCheck %s --check-prefix=BRANCH
// RUN: %clang_cc1 -E -triple i386 -dM -o - -fcf-protection=full %s |
FileCheck %s --check-prefix=FULL
// RUN: not %clang_cc1 -emit-llvm-only -triple
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/88736
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https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/88736
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/4] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-pc-linu
https://github.com/phoebewang deleted
https://github.com/llvm/llvm-project/pull/83136
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/5] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/6] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/6] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-pc-linu
@@ -18515,20 +18515,20 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
return LowerGlobalOrExternal(Op, DAG, /*ForCall=*/false);
}
-static SDValue
-GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
- SDValue *InG
@@ -34,6 +34,60 @@ __m128 test_mm_andnot_ps(__m128 A, __m128 B) {
return _mm_andnot_ps(A, B);
}
+__m128 test_mm_cmp_ps_eq_oq(__m128 a, __m128 b) {
+ // CHECK-LABEL: test_mm_cmp_ps_eq_oq
+ // CHECK: fcmp oeq <4 x float> %{{.*}}, %{{.*}}
+ return _mm_cmp_ps(a, b, _CMP_EQ_OQ
phoebewang wrote:
> I assume that's what you're doing in the place I asked for a comment is
> trying to avoid redundantly generating TLSDESC accesses for
> _TLS_MODULE_BASE_. I see that we don't generate multiple accesses for
> _TLS_MODULE_BASE_ in the test cases, but I thought that was only s
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/7] [X86] Add Support for X86 TLSDESC Relocations
---
clang/li
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-pc-linu
@@ -18522,13 +18522,21 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain,
GlobalAddressSDNode *GA,
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
SDLoc dl(GA);
- SDValue TGA = DAG.getTargetGlobalAdd
@@ -18543,7 +18552,19 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain,
GlobalAddressSDNode *GA,
MFI.setHasCalls(true);
SDValue Glue = Chain.getValue(1);
- return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
+ SDValue Ret = DAG.getCopyFromReg(Chain, dl, ReturnRe
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/84136
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@@ -1405,11 +1413,12 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_cvtss_sd(__m128d __a,
/// Converts the two double-precision floating-point elements of a
///128-bit vector of [2 x double] into two signed 32-bit integer values,
-///returned in the lower 64 bits
@@ -1405,11 +1413,12 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_cvtss_sd(__m128d __a,
/// Converts the two double-precision floating-point elements of a
///128-bit vector of [2 x double] into two signed 32-bit integer values,
-///returned in the lower 64 bits
phoebewang wrote:
Gentle ping~
https://github.com/llvm/llvm-project/pull/83136
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