The clocks should be adjusted after display configuration changed.
Otherwise, the socclk and memclk may be forced on an unnecessary higher
level.
Change-Id: I0170e968ba1f64d15d4238b658eefc307adc2642
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 13 ++---
1
>Still has risk for s3, we would better not put PG disabling (gfxoff) behind of
>CG
>disabling, even here is SMC clockgating. It is to avoid any MMU using when
>gfx is in "off" state.
I think logically we need to power on/off GFX ip through SMU, so first ungate
SMU block first.
Currently, it
On Tue, Jun 05, 2018 at 07:51:17PM +0800, Rex Zhu wrote:
> v3: 1. Delete the dead gfx off code in powerplay late_init.
> 2. Revert v2.
> 3. call smu to power on gfx at the begin of ip_suspend/device_fini
> 4. only power off gfx ip in the end of gfx power gate function
> v2: Delete the
On 2018-06-04 03:35 PM, Lyude Paul wrote:
> So, unfortunately I recently made the discovery that in the upstream
> kernel, the only reason that amdgpu is not currently suffering from
> issues with runtime PM putting the GPU into suspend while it's driving
> displays is due to the fact that on most
This isn't the first time I've had to argue to myself why the '++' was
safe.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_fence.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/v3d/v3d_fence.c b/drivers/gpu/drm/v3d/v3d_fence.c
index bfe31a89668b..6265e9ab4a13
Since our seqno value comes from a counter associated with the GPU
ring, not the entity (aka client), they'll be completed out of order.
There's actually no need for this code at all, since we don't have
enable_signaling() and thus DMA_FENCE_SIGNALED_BIT will be set before
we could be called.
Between creation and queueing of a job, you need to prevent any other
job from being created and queued. Otherwise the scheduler's fences
may be signaled out of seqno order.
Signed-off-by: Eric Anholt
Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D
V3.x+")
---
ccing
On 05.06.2018 15:17, Andrey Grodzovsky wrote:
From: David Panariti
SQ can generate interrupts and installs the ISR to
handle the SQ interrupts.
Add parsing SQ data in interrupt handler.
Signed-off-by: David Panariti
Signed-off-by: Andrey Grodzovsky
---
Everything in the flush code path (i.e. waiting for SW queue
to become empty) names with *_flush()
and everything in the release code path names *_fini()
This patch also effect the amdgpu and etnaviv drivers which
use those functions.
Signed-off-by: Andrey Grodzovsky
Suggested-by: Christian
Everything in the flush code path (i.e. waiting for SW queue
to become empty) names with *_flush()
and everything in the release code path names *_fini()
Signed-off-by: Andrey Grodzovsky
Suggested-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
Signed-off-by: Tom St Denis
---
src/lib/umr_read_pm4_stream.c | 49 ++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/src/lib/umr_read_pm4_stream.c b/src/lib/umr_read_pm4_stream.c
index b17f232a5381..9da804fc6793 100644
---
From: David Panariti
SQ can generate interrupts on EDC/ECC errors and this struct controls
how the interrupt is handled. The guts are filled in in the
gf_v_.c files.
Signed-off-by: David Panariti
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git
From: David Panariti
SQ can generate interrupts and installs the ISR to
handle the SQ interrupts.
Add parsing SQ data in interrupt handler.
Signed-off-by: David Panariti
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 110 +-
1
From: David Panariti
ISR will DRM_ERROR ECC error message.
Signed-off-by: David Panariti
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 81 +++
2 files changed, 82 insertions(+)
diff --git
Enable PG state after CG enabled.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 -
3 files changed, 29 insertions(+), 9
v3: 1. Delete the dead gfx off code in powerplay late_init.
2. Revert v2.
3. call smu to power on gfx at the begin of ip_suspend/device_fini
4. only power off gfx ip in the end of gfx power gate function
v2: Delete the dead gfx off code in ip_suspend.
gfx off should be controlled by
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, June 05, 2018 1:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amd/pp: Enable powergate_gfx on Raven
>
>
Comment inline
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, June 05, 2018 1:22 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 4/5] drm/amd/pp: Add gfx pg support in smu through
>
> /* skip CG for VCE/UVD, it's handled specially */
The comment should be fixed as this is for pg not cg.
With that fixed, the patch is Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, June
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang, Ray
> Sent: Tuesday, June 05, 2018 6:11 PM
> To: Huang, Ray ; Deucher, Alexander
> ; Koenig, Christian
> ; amd-gfx@lists.freedesktop.org
> Cc: Dan Carpenter
>
This patch replaces usage of mutex with spin_lock
to avoid sleep in atomic context.
Below is the stack trace:
BUG: sleeping function called from invalid context at kernel/locking/mutex.c:**
in_atomic(): 1, irqs_disabled(): 1, pid: 5, name: kworker/u4:0
CPU: 1 PID: 5 Comm: kworker/u4:0 Tainted: G
On 2018-06-05 11:48 AM, Christian König wrote:
> Just a copy leftover from radeon.
>
> Signed-off-by: Christian König
Reviewed-by: Michel Dänzer
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X
On 2018-06-05 11:48 AM, Christian König wrote:
> And wire it up as well.
>
> Signed-off-by: Christian König
Did you run
make htmldocs
or another documentation target, check that it doesn't print any
warnings about amdgpu_mn.c, and look at the generated documentation?
> diff --git
Ping.
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Huang
Rui
Sent: Friday, May 18, 2018 10:50 AM
To: Deucher, Alexander ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Dan Carpenter
Subject: [PATCH] drm/amd/powerplay:
And wire it up as well.
Signed-off-by: Christian König
---
Documentation/gpu/amdgpu.rst | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 74 ++
2 files changed, 67 insertions(+), 16 deletions(-)
diff --git a/Documentation/gpu/amdgpu.rst
Just a copy leftover from radeon.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 134 -
1 file changed, 67 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
On 06/05/2018 04:54 PM, Christian König wrote:
Am 05.06.2018 um 10:47 schrieb Zhang, Jerry (Junwei):
On 06/05/2018 04:45 PM, Christian König wrote:
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list
Am 05.06.2018 um 10:47 schrieb Zhang, Jerry (Junwei):
On 06/05/2018 04:45 PM, Christian König wrote:
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list because it is
possible
that we need to split up
On 06/05/2018 04:45 PM, Christian König wrote:
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list because it is possible
that we need to split up huge pages for them.
Signed-off-by: Christian König
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list because it is possible
that we need to split up huge pages for them.
Signed-off-by: Christian König
Does this need to go to stable?
Yes, good point.
The patch possibly cause ASIC hung during S3. GFXOFF should be disabled as the
first step when suspend, and then enabled again as the last step when resume.
Otherwise, any mmio access will result to aisc hung.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Rex Zhu
v2: Delete the dead gfx off code in ip_suspend.
gfx off should be controlled by GFX IP.
Powerplay only export interface to gfx ip.
This logic is same as uvd/vce cg/pg.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 6 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
On 06/05/2018 04:20 PM, zhoucm1 wrote:
On 2018年06月05日 16:14, Christian König wrote:
Am 05.06.2018 um 10:09 schrieb Junwei Zhang:
From: Christian König
(comments: I cannot receive amdgfx mail recently and reply the mail directly,
so send it out with my update v2, tested with Unigine Heaven,
On 2018年06月05日 16:14, Christian König wrote:
Am 05.06.2018 um 10:09 schrieb Junwei Zhang:
From: Christian König
(comments: I cannot receive amdgfx mail recently and reply the mail
directly,
so send it out with my update v2, tested with Unigine Heaven,
glmark2, gputest,
some cases from
Am 05.06.2018 um 10:09 schrieb Junwei Zhang:
From: Christian König
(comments: I cannot receive amdgfx mail recently and reply the mail directly,
so send it out with my update v2, tested with Unigine Heaven, glmark2, gputest,
some cases from vulkan PRT test)
v2: store bo_va as well
We need to
From: Christian König
(comments: I cannot receive amdgfx mail recently and reply the mail directly,
so send it out with my update v2, tested with Unigine Heaven, glmark2, gputest,
some cases from vulkan PRT test)
v2: store bo_va as well
We need to put the lose ends on the invalid list because
gfx off should be controlled by GFX IP.
Powerplay only export interface to gfx ip.
This logic is same as uvd/vce cg/pg.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
2 files changed, 6
Enable PG state after CG enabled.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 -
3 files changed, 29 insertions(+), 9
Hi,
I've got a system with an AMD Ryzen 5 2400G with Radeon Vega Graphics
that is connected to a Dell U3011 Monitor with a native resolution of
2560x1600 via DisplayPort. The OS is OpenSuse Tumbleweed with Kernel
4.16.12. I was used to switch off the monitor with the power button when
I'm
The original issue on these laptops was about _PR3, not audio controller
prevents gfx auto suspending.
Commit 444d95f0eeef ("Partially revert: drm/amdgpu: add atpx quirk
handling (v2)") breaks these laptops:
[ 29.572055] [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop for
more than
Patch #1 ~ 4 are Reviewed-by: Hawking Zhang
Patch #5
The patch will break recent gfxoff fix from Ray where he leveraged
pp_set_powergating_state to enable gfxoff. If we didn't control gfxoff in smc
power gating function, we have to add a new gfx function which then call into
amdgpu_pp
Updated.
Thanks,
Ray
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, June 05, 2018 3:28 PM
To: Zhang, Hawking ; Huang, Ray ;
amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kuehling, Felix
; Huang, Ray ; Koenig, Christian
Subject: RE: [PATCH v2] drm/amdgpu: fix CG
+ amdgpu_device_ip_set_powergating_state(adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_CG_STATE_GATE);
There is typo that AMD_CG_STATE_GATE should be AMD_PG_STATE_GATE. Please
correct
On 06/05/2018 02:20 PM, Christian König wrote:
Hi Jerry,
Am 05.06.2018 um 03:50 schrieb Zhang, Jerry (Junwei):
[SNIP]
Can you check if the problem also vanishes when you disable the following
optimization in amdgpu_vm_update_ptes?
/* We don't need to update PTEs for huge
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Huang Rui
Sent: 2018年6月5日 11:02
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kuehling, Felix
; Huang, Ray ; Koenig, Christian
; Zhang, Hawking
Subject: [PATCH v2] drm/amdgpu: fix
Am 05.06.2018 um 05:01 schrieb Huang Rui:
After defer the execution of clockgating enabling, at that time, gfx already
enter into "off" state. Howerver, clockgating enabling will use MMIO to access
the gfx registers, then get the gfx hung.
So here we should move the gfx powergating and gfxoff
Hi Jerry,
Am 05.06.2018 um 03:50 schrieb Zhang, Jerry (Junwei):
[SNIP]
Can you check if the problem also vanishes when you disable the
following
optimization in amdgpu_vm_update_ptes?
/* We don't need to update PTEs for huge pages */
if (entry->huge)
Am 04.06.2018 um 21:35 schrieb Lyude Paul:
So, unfortunately I recently made the discovery that in the upstream
kernel, the only reason that amdgpu is not currently suffering from
issues with runtime PM putting the GPU into suspend while it's driving
displays is due to the fact that on most
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