'pstate' here (int) is with different data type from the 1st patch of this
series(uint32_t there).
Please check whether that can cause any potential issues.
With that confirmed, the patch is reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Liu,
> Shaoyun
> Sent:
Acked-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Liu,
> Shaoyun
> Sent: Tuesday, April 09, 2019 10:55 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Always enable memory sharing within
> same XGMI hive
>
> ping
>
> On 2019-04-08 6:32
Reviewed-by: Evan Quan
However, if this is for vega20, please be noticed that vega20 still takes old
powerplay routines at default.
Regards,
Evan
> -Original Message-
> From: amd-gfx On Behalf Of Liu,
> Shaoyun
> Sent: Saturday, April 06, 2019 12:02 AM
> To:
On Tue, Apr 09, 2019 at 02:04:11PM -0400, Mathieu Desnoyers wrote:
> - On Apr 9, 2019, at 1:55 PM, paulmck paul...@linux.ibm.com wrote:
> [...]
> > The current state is not horrible, so my thought would be to give it
> > some time to see if better thoughts arise.
> >
> > Either way,
On Tue, Apr 09, 2019 at 11:56:03AM -0400, Mathieu Desnoyers wrote:
> - On Apr 9, 2019, at 11:40 AM, Joel Fernandes, Google
> j...@joelfernandes.org wrote:
>
> > On Mon, Apr 08, 2019 at 01:24:47PM -0400, Mathieu Desnoyers wrote:
> >> - On Apr 8, 2019, at 11:46 AM, paulmck
- On Apr 9, 2019, at 11:40 AM, Joel Fernandes, Google
j...@joelfernandes.org wrote:
> On Mon, Apr 08, 2019 at 01:24:47PM -0400, Mathieu Desnoyers wrote:
>> - On Apr 8, 2019, at 11:46 AM, paulmck paul...@linux.ibm.com wrote:
>>
>> > On Mon, Apr 08, 2019 at 10:49:32AM -0400, Mathieu
On Tue, Apr 09, 2019 at 12:45:25PM -0400, Mathieu Desnoyers wrote:
> - On Apr 9, 2019, at 12:40 PM, paulmck paul...@linux.ibm.com wrote:
>
> > On Tue, Apr 09, 2019 at 11:56:03AM -0400, Mathieu Desnoyers wrote:
> >> - On Apr 9, 2019, at 11:40 AM, Joel Fernandes, Google
> >>
- On Apr 9, 2019, at 12:40 PM, paulmck paul...@linux.ibm.com wrote:
> On Tue, Apr 09, 2019 at 11:56:03AM -0400, Mathieu Desnoyers wrote:
>> - On Apr 9, 2019, at 11:40 AM, Joel Fernandes, Google
>> j...@joelfernandes.org
>> wrote:
>>
>> > On Mon, Apr 08, 2019 at 01:24:47PM -0400, Mathieu
On Tue, Apr 09, 2019 at 11:56:03AM -0400, Mathieu Desnoyers wrote:
> - On Apr 9, 2019, at 11:40 AM, Joel Fernandes, Google
> j...@joelfernandes.org wrote:
>
> > On Mon, Apr 08, 2019 at 01:24:47PM -0400, Mathieu Desnoyers wrote:
> >> - On Apr 8, 2019, at 11:46 AM, paulmck
- On Apr 9, 2019, at 1:55 PM, paulmck paul...@linux.ibm.com wrote:
[...]
> The current state is not horrible, so my thought would be to give it
> some time to see if better thoughts arise.
>
> Either way, cleanup_srcu_struct() keeps its current checks for callbacks
> still being in flight,
From: Joshua Aberback
Add a fast_validate parameter in dc_validate_global_state for future use
Change-Id: If7a7ea618ba85bdddc8ee4419cd01e2fae3fda93
Signed-off-by: Joshua Aberback
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
From: Nicholas Kazlauskas
[Why]
Surface scaling info updates can affect bandwidth and blocks. We need
to be checking these with global validation to avoid underflow or
corruption.
[How]
Drop the state->allow_modeset early exit in
dm_determine_update_type_for_commit. Most of those should be
From: Nicholas Kazlauskas
[Why]
As long as we have at least one non-cursor plane enabled on a CRTC then
the CRTC itself can remain enabled.
This will allow for commits where there's an overlay plane enabled but
no primary plane enabled.
[How]
Remove existing primary plane fb != NULL checks and
From: Nicholas Kazlauskas
[Why]
DM thinks that the update type should be full whenever a stream or
plane is added or removed (including recreations).
This won't match in the case where DC thinks what looks like a fast
update to DM is actually a medium or full - like scaling changes that
affect
From: Nicholas Kazlauskas
[Why]
We currently don't do DC validation for medium or full updates where
the plane state isn't created. There are some medium and full updates
that can cause bandwidth or clock changes to occur resulting in
underflow or corruption.
We need to be able to fill surface
From: Joshua Aberback
[Why]
We used this change to investigate the performance of bandwidth validation,
it will be useful to have if we need to investigate further.
[How]
We use performance counter tick numbers to profile performance, they live
at dc->debug.bw_val_profile (set .enable in
From: Jun Lei
[why]
there are some scaling capabilities such as fp16 which are known to be
unsupported
on a given ASIC. exposing these static capabilities allows much simpler
implementation
for OS interfaces which require to report such static capabilities to reduce the
number of dynamic
From: Nicholas Kazlauskas
[Why]
Hardware can support video surfaces and DC tells us which planes are
suitable via DC plane caps.
[How]
The supported formats array will now vary based on what DC tells us,
so create an array and fill it dynamically based on plane types and
caps.
Ideally we'd
From: Nicholas Kazlauskas
[Why]
Planes have downscaling limits and upscaling limits per format and DM
is expected to validate these using DC caps. We should fail atomic
check validation if we aren't capable of doing the scaling.
[How]
We don't currently create store which DC plane maps to which
From: Nicholas Kazlauskas
[Why]
DC expects the surface memory address to identify the surface.
This doesn't work with what we're doing with the temporary surfaces,
it will always assume this is a full update because the surface
isn't in the current context.
[How]
Use the surface directly. This
From: Anthony Koo
[Why]
Unlike external DP panels, internal eDP does not perform
verify link caps because the panel connection is fixed.
So if GOP enabled the eDP at boot, we can retain its
trained link settings to optimize.
[How]
Read the lane count and link rate by reading this
information
From: Nicholas Kazlauskas
[Why]
We need DC's color space to match the color encoding and color space
specified by userspace to correctly render YUV surfaces.
[How]
Add the DRM color properties when the DC plane supports NV12.
Change-Id: Ie3eb9800a9a7954d05f691b277e7ca5a25164d5d
Signed-off-by:
From: Nicholas Kazlauskas
[Why]
Plane scaling parameters are not correctly filled or updated when
performing fast updates.
They're filled when creating the dc plane state and during atomic check.
While the atomic check code path happens for the plane even during fast
updates, the issue is that
From: David Francis
[Why]
On some compositors, with two monitors attached, VT terminal
switch can cause a graphical issue by the following means:
There are two streams, one for each monitor. Each stream has one
plane
current state:
M1:S1->P1
M2:S2->P2
The user calls for a
From: Nicholas Kazlauskas
[Why]
Pitch was only calculated based on format whenever the plane state
was recreated. This could result in surface corruption due to the
incorrect pitch being programmed when the surface pitch changed during
commits where state->allow_modeset = false.
[How]
From: Nicholas Kazlauskas
[Why]
The overlay will be incorrectly placed *below* the primary plane for
commits with state->allow_modeset = true because the primary plane
won't be removed and recreated in the same commit.
[How]
Add the should_reset_plane helper to determine if the plane should be
From: Samson Tam
[Why]
DM doesn't need to know which link cap is being retrieved ( verified
or preferred ). Let DC figure it out.
[How]
Change name.
Change-Id: I5585ac7dcdf58216b2942f7ab6758c5d15719d0d
Signed-off-by: Samson Tam
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Yongqiang Sun
Change-Id: Ibe60745eaaea72d694ceb9d22936eae0abae5674
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
From: David Francis
[Why]
dc_stream_get_crtc_position can return false.
This was unhandled in delay_cursor_until_vupdate
[How]
If dc_stream_get_crtc_position returns false, something
is weird. Don't delay.
Change-Id: Id0fc61792aaa248594deb46d9984bcb3fb78559c
Signed-off-by: David Francis
From: Aric Cyr
Change-Id: I2e35170195717fa417ddaeb372efe2908722d4a9
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
Summary Of changes
*add color properties
*fixes for determining update type
*eDP link setting on detect
Anthony Koo (1):
drm/amd/display: Read eDP link settings on detection
Aric Cyr (1):
drm/amd/display: 3.2.26
David Francis (2):
drm/amd/display: Handle get crtc position error
On 4/9/19 10:50 AM, Christian König wrote:
> Am 08.04.19 um 18:08 schrieb Andrey Grodzovsky:
>> Also reject TDRs if another one already running.
>>
>> Signed-off-by: Andrey Grodzovsky
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 94
>> +-
>> 1 file
On Mon, Apr 08, 2019 at 01:24:47PM -0400, Mathieu Desnoyers wrote:
> - On Apr 8, 2019, at 11:46 AM, paulmck paul...@linux.ibm.com wrote:
>
> > On Mon, Apr 08, 2019 at 10:49:32AM -0400, Mathieu Desnoyers wrote:
> >> - On Apr 8, 2019, at 10:22 AM, paulmck paul...@linux.ibm.com wrote:
> >>
On 2019-03-22 10:11 a.m., Nicholas Kazlauskas wrote:
> [Why]
> DC provides a few visual confirmation debug options that can be
> dynamically changed at runtime to help debug surface programming issues
> but we don't have any way to access it from userspace.
>
> [How]
> Add the
Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.
Change-Id: I713419c57b854082f6f739f1d32a055c7115e620
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
ping
On 2019-04-05 12:01 p.m., Liu, Shaoyun wrote:
> Driver need to call SMU to set xgmi pstate
>
> Change-Id: Iad7fd0e3b3155e45be8fe9119686c5bafa3c176c
> Signed-off-by: shaoyunl
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 13 -
> 1 file changed, 12 insertions(+), 1
ping
On 2019-04-05 12:01 p.m., Liu, Shaoyun wrote:
> XGMI pstate is controlled by SMU, driver need this interface to communicate
> with SMU
>
> Change-Id: I3a30797332557725d48d392bea0c9d59e2d0e427
> Signed-off-by: shaoyunl
> ---
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4
>
ping
On 2019-04-08 6:32 p.m., Liu, Shaoyun wrote:
> XGMI Memory sharing will be disbaled by default for security reason after
> boot up, it depends on driver to enable the memory sharing
>
> Change-Id: Ib516066eecfb877f84f1460a4d659abea44adb02
> Signed-off-by: shaoyunl
> ---
>
Am 08.04.19 um 18:08 schrieb Andrey Grodzovsky:
Also reject TDRs if another one already running.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 94 +-
1 file changed, 67 insertions(+), 27 deletions(-)
diff --git
Am 08.04.19 um 18:08 schrieb Andrey Grodzovsky:
For later driver's reference to see if the fence is signaled.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/scheduler/sched_main.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git
On 2019-03-25 3:27 p.m., Nicholas Kazlauskas wrote:
> The extra ; in the macro definition creates an empty statement
> preventing any variable declarations from occuring after
> any use of to_dm_plane_state(...).
>
> Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Leo Li
> ---
>
On 2019-03-22 9:59 a.m., Nicholas Kazlauskas wrote:
> The brace initialization used here generates warnings on some
> compilers. For example, on GCC 4.9:
>
> [...] In function ‘dm_determine_update_type_for_commit’:
> [...] error: missing braces around initializer [-Werror=missing-braces]
>
> -Original Message-
> From: Pinky [mailto:j...@seznam.cz]
> Sent: Monday, April 08, 2019 8:42 PM
> To: Huang, Ray
> Cc: Alex Deucher ; Deucher, Alexander
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on
> raven series"
>
> *
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Wang, Kevin(Yang)
> Sent: Monday, April 08, 2019 4:43 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Feng, Kenneth
> ; Wang, Kevin(Yang)
> Subject: [PATCH 1/2] drm/amd/powerplay:
> -Original Message-
> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
> Sent: Monday, April 08, 2019 9:13 PM
> To: Zhang, Jerry ; Huang, Ray
> ; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Subject: [PATCH 1/2] drm/ttm: fix out-of-bounds read in
> -Original Message-
> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
> Sent: Monday, April 08, 2019 9:13 PM
> To: Zhang, Jerry ; Huang, Ray
> ; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Subject: [PATCH 2/2] drm/ttm: fix start page for huge page
Reviewed-by: Evan Quan
> -Original Message-
> From: Pan, Xinhui
> Sent: Tuesday, April 09, 2019 4:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Quan, Evan
>
> Subject: [PATCH] drm/amdgpu: Add a check to avoid panic because of
> unexpected irqs
>
> IP initialize
v2: use one transfer ioctl
Signed-off-by: Chunming Zhou
---
xf86drm.c | 33 +
xf86drm.h | 6 ++
2 files changed, 39 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index 66e0c985..d57c4218 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4280,6 +4280,21 @@
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu.h| 22 ++
amdgpu/amdgpu_cs.c | 16
2 files changed, 38 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index b5bd3ed9..2350835b 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1670,6
v2: drop export/import
Signed-off-by: Chunming Zhou
---
xf86drm.c | 44
xf86drm.h | 6 ++
2 files changed, 50 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index 18ad7c58..66e0c985 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4279,3 +4279,47
Signed-off-by: Chunming Zhou
---
include/drm/amdgpu_drm.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index e3a97da4..ab53f2e0 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -528,6 +528,8 @@ struct
v2: adapt to new one transfer ioctl
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu-symbol-check | 3 ++
amdgpu/amdgpu.h| 51
amdgpu/amdgpu_cs.c | 68 ++
3 files changed, 122 insertions(+)
diff --git
v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
amdgpu/amdgpu-symbol-check | 2 ++
amdgpu/amdgpu.h| 39 ++
amdgpu/amdgpu_cs.c | 23
v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
fix some warnings
v3: add export/import and cpu signal testing cases
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
tests/amdgpu/Makefile.am | 3 +-
tests/amdgpu/amdgpu_test.c | 11 ++
v2: drop not implemented IOCTLs and flags
v3: add transfer/signal ioctls
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
include/drm/drm.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/include/drm/drm.h b/include/drm/drm.h
index
IP initialize ras in late_init, because of the BUGs of PSP or any
other components, driver receives unexpected irqs. It is ok to add such
check anyway.
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++-
On 4/8/19 9:13 PM, Christian König wrote:
When ttm_put_pages() tries to figure out whether it's dealing with
transparent hugepages, it just reads past the bounds of the pages array
without a check.
v2: simplify the test if enough pages are left in the array (Christian).
Series is Reviewed-by:
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