>>> If we are trying to debug a reproducible hang, probably best to just to
>>> disable gfxoff before messing with it to remove that as a factor.
Agree
>> Otherwise, the method included in this patch is the proper way to
>> disable/enable GFXOFF dynamically.
Sounds not doable, because we cannot
>>>RREG32_KIQ and WREG32_KIQ
If you are using RREG32_KIQ it is always go through KIQ no matter GFX is "on"
state or not
-邮件原件-
发件人: Huang, Ray
发送时间: 2020年2月21日 23:23
收件人: Liu, Monk
抄送: StDenis, Tom ; Alex Deucher ;
amd-gfx list
主题: Re: 回复: [PATCH] drm/amd/amdgpu: disable GFXOFF
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Joseph Gravenor
From: Liu, Zhan
Sent: Monday, February 10, 2020 4:08 PM
To: amd-gfx@lists.freedesktop.org ; Liu, Zhan
; Gravenor, Joseph
Subject: [PATCH] drm/amd/display: Add aconnector
This change disables programming of GCVM_L2_CNTL* regs on VF.
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
On Fri, Feb 21, 2020 at 1:45 PM Tom St Denis wrote:
>
> Write a 32-bit value of zero to disable GFXOFF and write a 32-bit
> value of non-zero to enable GFXOFF.
>
> Signed-off-by: Tom St Denis
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 56 +
> 1 file changed, 56
Write a 32-bit value of zero to disable GFXOFF and write a 32-bit
value of non-zero to enable GFXOFF.
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 56 +
1 file changed, 56 insertions(+)
diff --git
[AMD Official Use Only - Internal Distribution Only]
That's fine to me.
-David
From: Koenig, Christian
Sent: Friday, February 21, 2020 11:33 PM
To: Deucher, Alexander ; Christian König
; Zhou, David(ChunMing)
; He, Jacob ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Add a
Probably simpler just to do on/off and let userspace determine timing
but other than that ya sounds good.
Works for me as long as we only expose it through debugfs for root.
Otherwise there is always the risk of userspace forgetting to turn it on
again.
Christian.
Am 21.02.20 um 17:06
Probably simpler just to do on/off and let userspace determine timing
but other than that ya sounds good.
For things like umr's --top which runs indefinitely having a timer
wouldn't work. Similarly, --waves can take a long time depending on
activity and the asic.
Tom
On 2020-02-21
From: Yongqiang Sun
[Why]
In some display configuration like 1080P monitor playing a 1080P video,
if user use ALT+F4 to exit Movie and TV, there is a chance clocks are
same only water mark changed. Current clock optimization machanism will
result in water mark keeps high after exit Movie and TV
From: George Shen
[Why]
Underflow sometimes occurs during transition into MPO with stutter
enabled.
[How]
When transitioning into MPO, disable stutter. Re-enable stutter within
one frame.
Signed-off-by: George Shen
Signed-off-by: Tony Cheng
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
From: Jaehyun Chung
[Why]
System will crash when trying to access local sink in
core_link_enable_stream in MST case.
[How]
Access patches directly from stream.
Signed-off-by: Jaehyun Chung
Reviewed-by: Aric Cyr
Reviewed-by: Ashley Thomas
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
From: Dmytro Laktyushkin
Need to assign surface size rather than viewport size for surface size
dml variable.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 8
From: Sung Lee
[WHY]
Currently clock table struct is very far down in the bounding box struct
making it hard to find while debugging, especially when using the
dal3dbgext.
[HOW]
Move it up so it is the first struct defined, and therefore much easier
to find and access.
Signed-off-by: Sung Lee
From: Yu-ting Shen
[Why]
when changing display clock, SMU need to use power up DFS and use
DENTIST to ramp DFS DID to switch target frequency before switching back
to bypass.
[How]
fixed the minimum display clock to 100MHz, it's W/A the same with PCO.
Signed-off-by: Yu-ting Shen
Reviewed-by:
From: Peikang Zhang
[Why]
DalMPVisualConfirm does not support FreeSync 2 ARGB2101010 which causes
black visual confirm bar when playing HDR video on FreeSync 2 display in
full screen mode
[How]
Added pink color for DalMPVisualConfirm on FreeSync 2 ARGB2101010
surface
Signed-off-by: Peikang
From: Michael Strauss
[WHY]
RV2 and variants are indistinguishable by hw internal rev alone, need to
be distinguishable in order to correctly set max vlevel. Previous
detection change incorrectly checked for hw internal rev.
[HOW]
Use pci revision to check if RV2 or low power variant Correct a
From: Sung Lee
[WHY]
Not programming dto with same values causes test failures in DCN2 diags
DPP tests.
[HOW]
This reverts commit 6f4c8c3022bcdad362b89953a43644e943608f9f.
Signed-off-by: Sung Lee
Reviewed-by: Yongqiang Sun
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
From: Dmytro Laktyushkin
Update dcn20_populate_dml_pipes_from_context to correctly handle odm
when no surface is provided.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 26
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 -
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 -
From: Alvin Lee
[Why]
We need to update TTU properly if DRAMClockChangeWatermark changes. If
TTU < DRAMClockChangeWatermark, we pstate won't be allowed and we will
hang in some PSR cases.
[How]
Update TTU if DramClockChangeWatermark value increases (only if TTU was
dependent on the watermark
Ok how about this:
We add a debugfs file which when read returns the GFXOFF status and when
written with a number disabled GFXOFF for N seconds with 0 meaning forever.
Umr gets a new commandline option to write to that file before reading
registers.
This way the user can still disable it
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes and improvements on:
- DML
- ddc
- i2c
- tx mask
- link training
* DMCUB improvements
* Clks optimizations
Alvin Lee (3):
drm/amd/display: Update TX masks correctly
drm/amd/display: Disable PG
From: Dmytro Laktyushkin
Currently there is a minor error in scaling filter coefficients
caused by truncation to fit the HW registers.This error accummulates
with increased taps, but has gone unnoticed due to vast majority of
scaling being done with only 4 taps.
Scaling filters are now updated
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
From: Wyatt Wood
[Why]
We want to be able to enable PSR on DMCUB, and fallback to
DMCU when necessary.
[How]
Add infrastructure to enable and disable PSR on DMCUB.
Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
From: Nicholas Kazlauskas
[Why]
If we're doing backdoor load then do it entirely ourselves without
invoking any of the frontdoor path to avoid potential issues with
outdated tOS.
[How]
Check the load type and don't pass it to base if we don't want it
loaded.
Signed-off-by: Nicholas Kazlauskas
From: Bhawanpreet Lakha
when the rxstatus split was done the index was incorrect. This
lead to HDMI repeater authentication failure for HDCP2.X So fix it
Fixes: 302169003733 ("drm/amd/display: split rxstatus for hdmi and dp")
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Wenjing Liu
Acked-by:
From: Martin Leung
[Why]
Previously implemented early_cr_pattern was link level but the whole
asic should be affected.
[How]
- change old link flag to dc level
- new bit in dc->work_arounds set by DM
Signed-off-by: Martin Leung
Reviewed-by: Joshua Aberback
Acked-by: Rodrigo Siqueira
From: Hersen Wu
Signed-off-by: Hersen Wu
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git
From: Anthony Koo
[Why]
There are some structures and functions meant only to be used in the
scope of that single rn_clk_mgr c file.
[How]
Make structs and funcs static if only meant to be used within
rn_clk_mgr
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
From: Peikang Zhang
[Why]
Unused VMIDs were not evicted correctly
[How]
1. evict_vmids() logic was fixed;
2. Added boundary check for add_ptb_to_table() and
clear_entry_from_vmid_table() to avoid crash caused by array out of
boundary;
3. For mod_vmid_get_for_ptb(), vimd is changed from
From: Roman Li
[Why]
We need DMCU for features like PSR and ABM.
[How]
Add path to dmcu firmware binary and load it for Navi12.
Signed-off-by: Roman Li
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7
From: Aric Cyr
[Why]
Since the i2c payload allocation can fail need to check return codes
[How]
Clean up i2c payload allocations and check for errors
Signed-off-by: Aric Cyr
Reviewed-by: Joshua Aberback
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
From: Vladimir Stempen
[Why]
Currently DAL programs negative slope for the last point of output
transfer function curve.
[How]
Applying a check for the last PWL point for RGB values not to be
smaller than previous. If smaller, initialize the last point values
to a sum of previous PWL value and
From: Alvin Lee
[Why]
Bugs occur when TX interrupt comes in when no USB-C on board.
[How]
Check PHY for USB-C before enabling TX interrupt in DMCU FW.
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
From: Aric Cyr
[Why]
When calculating nominal refresh rates, don't round.
Only the VSIF needs to be rounded.
[How]
Revert rounding change for nominal and just round when forming the
FreeSync VSIF.
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Acked-by: Harry
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
From: Nicholas Kazlauskas
[Why]
Firmware state helps to debug sequence issues and hangs for DMCUB
commands and we don't have an easy mechanism to dump it from the driver.
[How]
Add a debugfs entry to dump the current firmware state.
Example usage:
cat
From: David Galiffi
[Why]
A software workaround is required for all vendor-built cards on platform.
[How]
When performing DP link training, we must send TPS1 before DPCD:100h is
written with the proper bit rate value. This change must be applies in
ALL cases when LT happens.
Signed-off-by:
From: Jaehyun Chung
[Why]
Some displays clear ignore MSA bit on mode change, which cause
blackscreen when programming variable vtotals. Ignore MSA bit needs
programming needs to be delayed or re-set to be retained.
[How]
Create patch to delay programming ignore MSA bit after unblanking
stream.
From: Nicholas Kazlauskas
[Why]
When we execute the first command for ASIC_INIT for command table
offloading we can hit a timing scenario such that the interrupts
for the inbox wptr haven't been enabled yet and the first command
is ignored until the second command is sent.
[How]
This happens
From: Anthony Koo
[Why]
Make panel backlight and power on/off functions into
hardware specific function pointers
[How]
Add function pointers for panel related hw functions
- is_panel_powered_on
- is_panel_backlight_on
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Rodrigo
From: Hersen Wu
Signed-off-by: Hersen Wu
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git
From: Samson Tam
[Why]
Add optimization to allow pstate change support when all displays
are off in DCN2.
[How]
Add clk_mgr_helper_get_active_plane_cnt() to sum plane_count for all
valid stream_status[]. If plane_count is 0, then there are no active
or virtual streams present. Use plane_count
From: Alvin Lee
[Why]
According to HW team, PG is dropped for NV12, but programming
the registers will still cause power to be consumed, so don't
program for NV12.
[How]
Set function pointer to NULL if NV12
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Acked-by:
[AMD Public Use]
Not at the moment. But we could add a debugfs file which just wraps
amdgpu_gfx_off_ctrl(). That said, maybe we just add a delay here or a use a
timer to delay turning gfxoff back on again so that we aren't turning it on and
off so rapidly.
Alex
On Fri, Feb 21, 2020 at 11:27:10PM +0800, Christian König wrote:
> Am 21.02.20 um 16:23 schrieb Huang Rui:
> > On Fri, Feb 21, 2020 at 11:18:07PM +0800, Liu, Monk wrote:
> >> Better not use KIQ, because when you use debugfs to read register you
> >> usually hit a hang, and by that case KIQ
Do we have a way to disable GFXOFF on the fly?
If not maybe it would be a good idea to add a separate debugfs file to
do this.
Christian.
Am 21.02.20 um 16:39 schrieb Deucher, Alexander:
[AMD Public Use]
If we are trying to debug a reproducible hang, probably best to just
to disable
[AMD Public Use]
If we are trying to debug a reproducible hang, probably best to just to disable
gfxoff before messing with it to remove that as a factor. Otherwise, the
method included in this patch is the proper way to disable/enable GFXOFF
dynamically.
Alex
This silences the following coccinelle warning:
"WARNING: sum of probable bitmasks, consider |"
Signed-off-by: Chen Zhou
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.c:
In function hubp21_set_vm_system_aperture_settings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.c:343:23:
warning: variable mc_vm_apt_default set but not used
[-Wunused-but-set-variable]
It is never used, so remove it.
I would just do this as part of the vm_flush() callback on the ring.
E.g. check if the VMID you want to flush is reserved and if yes enable SPM.
Maybe pass along a flag or something in the job to make things easier.
Christian.
Am 21.02.20 um 16:31 schrieb Deucher, Alexander:
[AMD Public
[AMD Public Use]
We already have the RESERVE_VMID ioctl interface, can't we just use that
internally in the kernel to update the rlc register via the ring when we
schedule the relevant IB? E.g., add a new ring callback to set SPM state and
then set it to the reserved vmid before we schedule
Am 21.02.20 um 16:23 schrieb Huang Rui:
On Fri, Feb 21, 2020 at 11:18:07PM +0800, Liu, Monk wrote:
Better not use KIQ, because when you use debugfs to read register you usually
hit a hang, and by that case KIQ probably already die
If CP is busy, the gfx should be in "on" state at that time,
On Fri, Feb 21, 2020 at 11:18:07PM +0800, Liu, Monk wrote:
> Better not use KIQ, because when you use debugfs to read register you usually
> hit a hang, and by that case KIQ probably already die
If CP is busy, the gfx should be in "on" state at that time, we needn't use KIQ.
Thanks,
Ray
>
>
Better not use KIQ, because when you use debugfs to read register you usually
hit a hang, and by that case KIQ probably already die
-邮件原件-
发件人: amd-gfx 代表 Huang Rui
发送时间: 2020年2月21日 22:34
收件人: StDenis, Tom
抄送: Alex Deucher ; amd-gfx list
主题: Re: [PATCH] drm/amd/amdgpu: disable
On Fri, Feb 21, 2020 at 10:35:33PM +0800, StDenis, Tom wrote:
>
> On 2020-02-21 9:34 a.m., Huang Rui wrote:
> > On Wed, Feb 19, 2020 at 10:09:46AM -0500, Tom St Denis wrote:
> >> I got some messages after a while:
> >>
> >> [ 741.788564] Failed to send Message 8.
> >> [ 746.671509] Failed to
On 2020-02-21 9:34 a.m., Huang Rui wrote:
On Wed, Feb 19, 2020 at 10:09:46AM -0500, Tom St Denis wrote:
I got some messages after a while:
[ 741.788564] Failed to send Message 8.
[ 746.671509] Failed to send Message 8.
[ 748.749673] Failed to send Message 2b.
[ 759.245414] Failed to send
On Wed, Feb 19, 2020 at 10:09:46AM -0500, Tom St Denis wrote:
> I got some messages after a while:
>
> [ 741.788564] Failed to send Message 8.
> [ 746.671509] Failed to send Message 8.
> [ 748.749673] Failed to send Message 2b.
> [ 759.245414] Failed to send Message 7.
> [ 763.216902] Failed
Hi
Am 19.02.20 um 14:53 schrieb Nirmoy Das:
> Calculate GEM VRAM bo's offset within vram-helper without depending on
> bo->offset
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/drm_gem_vram_helper.c | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff
That would probably be a no-go, but we could enhance the kernel driver
to update the RLC_SPM_VMID register with the reserved VMID.
Handling that in userspace is most likely not working anyway, since the
RLC registers are usually not accessible by userspace.
Regards,
Christian.
Am 20.02.20
On 2/19/20 2:53 PM, Nirmoy Das wrote:
Calculate GPU offset within vmwgfx driver itself without depending on
bo->offset
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Tested-by: Thomas Hellstrom
Acked-by: Thomas Hellstrom
___
amd-gfx
Hi,
On 2/19/20 2:53 PM, Nirmoy Das wrote:
With this patch series I am trying to remove GPU address dependency in
TTM and moving GPU address calculation to individual drm drivers.
For future reference, could you please add a motivation for the series?
for example cleanup, needed because,
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