Reviewed-by Andrey Grodzovsky
Andrey
From: amd-gfx on behalf of Emily.Deng
Sent: 07 October 2020 21:35
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu: Remove warning for virtual_display
Remove the virtual_display warning in drm
Remove the virtual_display warning in drm_crtc_vblank_off when
dev->num_crtcs is null.
Signed-off-by: Emily.Deng
Change-Id: I755150a32478d8c128eed7ed98a71175d2b3aefc
---
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
From: Tao Zhou
Update driver if version from 0x5 to 0x6 for dimgrey_cavefish, per PMFW 59.04.0.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
From: James Zhu
Enable VCN3.0 PG and CG for dimgrey_cavefish
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/a
From: Tao Zhou
Increase fw_name string size so longer chip name can be stored.
v2: define macro for the length of psp fw name.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdg
From: Tao Zhou
Set athub/mmhub PG flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu
From: Bhawanpreet Lakha
Handle CAVE_DIMGREY_CAVEFISH in amdgpu_dm
v2: fix rebase typo (Alex)
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 ++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/
From: Tao Zhou
Remove gpu_info fw support for dimgrey_cavefish, gpu info can be got
from ip discovery.
Signed-off-by: Tao Zhou
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff
From: Tao Zhou
General psp support for dimgrey_cavefish.
v2: remove the checks for asd load and reroute ih.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 13 +++
From: James Zhu
Enable vcn3.0 ip block for dimgrey_cavefis.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
inde
From: Tao Zhou
Set mc CG and LS flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/d
From: Tao Zhou
Set ih CG flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/a
From: Tao Zhou
Add gc golden setting for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Tested-by: Chengming Gui
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/drive
From: Tao Zhou
Support both back and front door loading for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: James Zhu
Enable jpeg3.0 ip block for dimgrey_cavefish.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
in
From: Tao Zhou
Add check before reroute ih setting, it's not supported by some ASICs.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/
From: Tao Zhou
Update driver if version according to PMFW with version 0x003B0100.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Chengming Gui
Signed-off-by: Chengming Gui
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 7a1ff80cf
From: Tao Zhou
Per PMFW 59.7.0.
Signed-off-by: Tao Zhou
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/pm/inc/s
From: Bhawanpreet Lakha
- add DCN302 resource, irq service, dmub loader,
- handle DC_VERSION_DCN_3_02
- define DCN302 power gating functions
- handle DCN302 in GPIO files
- define I2C regs
- add CONFIG_DRM_AMD_DC_DCN3_02 guard
v2: rebase fixes (Alex)
Signed-off-by: Joshua Aberback
Signe
From: Tao Zhou
Per PMFW 59.5.0.
v2: refine subject and commit message, fix typo
Signed-off-by: Tao Zhou
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/p
From: Tao Zhou
Set hdp CG and LS flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/
From: Tao Zhou
Add psp and smu block for dimgrey_cavefish with psp firmware load type.
Signed-off-by: Tao Zhou
Reviewed-by:Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/
From: Tao Zhou
Update driver if version from 0x4 to 0x5 for dimgrey_cavefish, per PMFW 59.02.0.
Signed-off-by: Tao Zhou
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
From: James Zhu
Add firmware support for dimgrey_cavefish.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm
From: Tao Zhou
Same as navy_flounder, the athub ip of dimgrey_cavefish is v2.1.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1
From: James Zhu
Enable JPEG3.0 PG and CG for dimgrey_cavefish.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/am
From: Tao Zhou
Enable GFX MGCG, CGCG and 3DCG for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/dri
From: James Zhu
Enable VCN DPG mode for dimgrey_cavefish.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/am
From: Chengming Gui
Add KFD support for dimgrey cavefish.
v2: rebase (Alex)
Signed-off-by: Chengming Gui
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 +++
.../dr
From: Tao Zhou
Same as sienna_cichlid, dimgrey_cavefish supports WAIT_REG_MEM packet.
Signed-off-by: Tao Zhou
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v
From: Tao Zhou
A longer chip name needs more space.
v2: define macro for the length of smu fw name
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h| 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
From: Tao Zhou
Enable gmc block for dimgrey_cavefish, same as sienna_cichlid.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/nv.c| 1 +
2 files cha
From: Tao Zhou
Reuse sienna_cichlid pp table for dimgrey_cavefish.
v2: update related comment.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
dri
From: Tao Zhou
The athub version for dimgrey_cavefish is v2.1.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 8
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 1 +
2 files changed, 5 insertions(+), 4 deletions
From: Tao Zhou
Add virtual ip block for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/dri
From: Tao Zhou
Add chip type for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h| 1 +
2 files changed, 2 insertions(
From: Tao Zhou
Add support for dimgrey_cavefish cp/rlc firmware.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/d
From: Tao Zhou
The gfx version of dimgrey_cavefish is 10.3, identical to sienna_cichlid,
follow the way
of sienna_cichlid.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +
1 f
From: Tao Zhou
Enable gfx block for dimgrey_cavefish, same as navy_flounder.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4
drivers/gpu/drm/amd/amdgpu/nv.c| 1 +
2 files c
From: Tao Zhou
Add ip offset definition for dimgrey_cavefish and initialize it.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile |2 +-
.../amd/amdgpu/dimgrey_cavefish_reg_init.c
From: Tao Zhou
Same as navy_flounder.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers
From: Tao Zhou
Enable sdma block for dimgrey_cavefish, same as sienna_cichlid.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c| 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 11 +--
From: Tao Zhou
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2, the
same as sienna_cichlid.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/d
From: Tao Zhou
Load gpu info firmware for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/am
From: Tao Zhou
Same as navy_flounder.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
b/dri
This series adds initial support for Dimgrey Cavefish.
Bhawanpreet Lakha (2):
drm/amd/display: Add support for DCN302 (v2)
drm/amd/display: Add DCN302 support in amdgpu_dm (v2)
Chengming Gui (2):
drm/amdkfd: Support dimgrey_cavefish KFD (v2)
drm/amdkfd: Add kfd2kgd_funcs for dimgrey_cavef
From: Tao Zhou
Same as navy_flounder.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/am
From: Tao Zhou
Set gfx clock gating for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v
From: Tao Zhou
Add external id and set clock gating for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/a
From: Tao Zhou
Enable ih block for dimgrey_cavefish, same as navy_flounder.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/nv.c| 1 +
2 files chang
From: Tao Zhou
Same as navi series.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/driv
From: Tao Zhou
Use direct load for dimgrey_cavefish.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Reviewed-by: Jiansong Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgp
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Use a f
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Use a f
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Refacto
Hi all,
This series aims to replace one-element arrays with flexible-array
members.
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The
This is a skeleton implementation to invite comments and generate
discussion around the idea of introducing a bpf-cgroup program type to
control ioctl access. This is modelled after
BPF_PROG_TYPE_CGROUP_DEVICE. The premise is to allow system admins to
write bpf programs to block some ioctl access
[AMD Public Use]
Reviewed-by: Kent Russell
Kent
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, October 6, 2020 9:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu: prevent spurious warning
>
> The def
On Wed, Oct 7, 2020 at 3:25 PM Christian König wrote:
>
> Am 07.10.20 um 15:20 schrieb Thomas Zimmermann:
> > Hi
> >
> > Am 07.10.20 um 15:10 schrieb Daniel Vetter:
> >> On Wed, Oct 7, 2020 at 2:57 PM Thomas Zimmermann
> >> wrote:
> >>> Hi
> >>>
> >>> Am 02.10.20 um 11:58 schrieb Daniel Vetter:
Am 07.10.20 um 15:20 schrieb Thomas Zimmermann:
Hi
Am 07.10.20 um 15:10 schrieb Daniel Vetter:
On Wed, Oct 7, 2020 at 2:57 PM Thomas Zimmermann wrote:
Hi
Am 02.10.20 um 11:58 schrieb Daniel Vetter:
On Wed, Sep 30, 2020 at 02:51:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 30, 2020 at 2:34
Hi
Am 07.10.20 um 15:10 schrieb Daniel Vetter:
> On Wed, Oct 7, 2020 at 2:57 PM Thomas Zimmermann wrote:
>>
>> Hi
>>
>> Am 02.10.20 um 11:58 schrieb Daniel Vetter:
>>> On Wed, Sep 30, 2020 at 02:51:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 30, 2020 at 2:34 PM Christian König
wrote:
On Wed, Oct 7, 2020 at 2:57 PM Thomas Zimmermann wrote:
>
> Hi
>
> Am 02.10.20 um 11:58 schrieb Daniel Vetter:
> > On Wed, Sep 30, 2020 at 02:51:46PM +0200, Daniel Vetter wrote:
> >> On Wed, Sep 30, 2020 at 2:34 PM Christian König
> >> wrote:
> >>>
> >>> Am 30.09.20 um 11:47 schrieb Daniel Vetter
Hi
Am 02.10.20 um 11:58 schrieb Daniel Vetter:
> On Wed, Sep 30, 2020 at 02:51:46PM +0200, Daniel Vetter wrote:
>> On Wed, Sep 30, 2020 at 2:34 PM Christian König
>> wrote:
>>>
>>> Am 30.09.20 um 11:47 schrieb Daniel Vetter:
On Wed, Sep 30, 2020 at 10:34:31AM +0200, Christian König wrote:
>>
From: Nikola Cornij
[Why] Can be used for debug purposes
[How] Add max target bpp override field and related handling
Signed-off-by: Nikola Cornij
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++-
driv
From: Taimur Hassan
[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.
[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.
Signed-off-by: Taimur Hassan
Acked-by: Aurabindo Pillai
From: Ashley Thomas
[Why]
Some sink devices wish to have access to the minimum
HBlank supported by the ASIC.
[How]
Make the ASIC minimum HBlank available in Source
Device information address 0x340.
Signed-off-by: Ashley Thomas
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/core/dc
From: Eryk Brol
This reverts commit 39edb76689b8c9e41b1b9e2557da4897a405221b.
Reason for revert: Patch introduces performance issues and might
cause memory consistency problems with multiple connectors.
Signed-off-by: Eryk Brol
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm
From: Alvin Lee
[Why]
If full pstate is not supported, we should set WM set A
to 0 to prevent any hangs
[How]
If pstate is not supported, set watermark set A to 0
Signed-off-by: Alvin Lee
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
1 file chan
From: Reza Amini
[why]
So we can track VSC SDP errors from display
[how]
Define the bit, and use it in driver logic
Signed-off-by: Reza Amini
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --gi
From: Stylon Wang
[Why]
When restoring connector state we relies on drm_connector->status
to check if the connector with matching crtc is connected.
But that status is only updated later when user space calls
DRM_IOCTL_MODE_GETCONNECTOR and then calls fillsmodes().
This causes connectors being in
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC 3.2.107
* Firmware release 0.0.37
* DCN21 power optimization for video playback
* Bounding box updates
* Bug fixes for DP/HDMI hotplug, DSC debugfs, watermarks etc
--
Alvin Lee (1):
drm/amd/display: Set WM
From: Anthony Koo
| [Header Changes]
|- Add GPINT to change timestamping mode for traces
Signed-off-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/di
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index dca2b4998b3a..06ec07d692d7 100644
--- a
From: Dmytro Laktyushkin
[WHY & HOW]
Enable ODM Combine + Fullscreen MPO on DCN2.1
For lower power consumption in video use cases.
Signed-off-by: Dmytro Laktyushkin
Signed-off-by: Sung Lee
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 8 ++
.../drm/amd/d
From: Dmytro Laktyushkin
[Why&How]
Create a separate dcn21_fast_validate_bw function for dcn21.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 3 +
.../drm/amd/display/d
From: Sung Lee
[WHY]
DF PState and Voltage State are coupled such that one cannot be
raised without raising the other. This uses more power than
is necessary in high bandwidth scenarios.
[HOW]
Add logic to create a new bounding box state that allows for
DF PState to be low while Voltage State is
Acked-by: Nirmoy Das
On 10/6/20 8:05 AM, Shashank Sharma wrote:
This patch adds a return value check and an error message to
highlight the DAC setup failure case during encoder DPMS
operation.
Cc: Alex Deucher
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/atombios_encoders.
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