Am 07.04.21 um 21:04 schrieb Alex Deucher:
On Wed, Apr 7, 2021 at 3:23 AM Dave Airlie wrote:
On Wed, 7 Apr 2021 at 06:54, Alex Deucher wrote:
On Fri, Apr 2, 2021 at 12:22 PM Christian König
wrote:
Hey Alex,
the TTM and scheduler changes should already be in the drm-misc-next
branch (not
On Wed, 7 Apr 2021 16:30:01 -0400
Alex Deucher wrote:
> On Tue, Apr 6, 2021 at 10:13 AM Carlis wrote:
> >
> > From: Xuezhi Zhang
> >
> > Fix the following coccicheck warning:
> > drivers/gpu/drm/amd/pm//amdgpu_pm.c:1940:8-16:
> > WARNING: use scnprintf or sprintf
> > drivers/gpu/drm/amd/pm//amd
Hi Andrey,
Am 07.04.21 um 21:44 schrieb Andrey Grodzovsky:
On 2021-04-07 6:28 a.m., Christian König wrote:
Hi Andrey,
Am 06.04.21 um 23:22 schrieb Andrey Grodzovsky:
Hey Christian, Denis, see bellow -
On 2021-04-06 6:34 a.m., Christian König wrote:
Hi Andrey,
well good question. My job
Am 08.04.21 um 10:22 schrieb Christian König:
Hi Andrey,
Am 07.04.21 um 21:44 schrieb Andrey Grodzovsky:
On 2021-04-07 6:28 a.m., Christian König wrote:
Hi Andrey,
Am 06.04.21 um 23:22 schrieb Andrey Grodzovsky:
Hey Christian, Denis, see bellow -
On 2021-04-06 6:34 a.m., Christian Köni
[AMD Public Use]
Hi Peng Ju,
Before merging your patches, it's suggested to conduct a full test in BM mode
as well to avoid regression, as register access is changed.
Another problem is, it seems the subject of patch 2, 4 and 5 is the same. Can
you please modify it respectively a bit to be mor
ASPM can be verified funtionally on navi1x.
And can be enabled for the benefit of the power consumption
without the performance hurt.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
[AMD Public Use]
* The ASPM function is not fully enabled and verified on
* Navi yet. Temporarily skip this until ASPM enabled.
*/
The comments needs to be adjusted as well?
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Kenneth Feng
Sent: Thursday, Apr
[AMD Public Use]
Hi Guchun
The patches have been tested on NV12 with:
1. bare metal load/unload with new and old register access path
2. SRIOV load/unload with new and old register access path
3. TDR, benchmark etc. with new register access path on AWS project.
About " An
[AMD Public Use]
Thanks. I will remove the comments.
-Original Message-
From: Chen, Guchun
Sent: Thursday, April 8, 2021 5:55 PM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth
Subject: RE: [PATCH] drm/amd/pm: enable ASPM on navi1x
[AMD Public Use]
* The ASPM fun
On Thu, Apr 01, 2021 at 06:56:09AM +1000, Dave Airlie wrote:
> I think this is due to this pull, on arm32.
>
> /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:
> In function ‘dmub_srv_hw_init’:
> /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/amd/am
From: pengzhou
In SRIOV environment, KMD should access MMHUB registers
with RLCG if MMHUB indirect access bit enabled.
Change MMHUB register access from MMIO to RLCG.
Signed-off-by: pengzhou
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 3
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 38 ---
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 36
1 file changed, 18 insertions(+), 18 deletions(
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 4 +-
drivers/g
use psp to program IH_RB_CNTL* if indirect access
for ih enabled in SRIOV environment.
Signed-off-by: Victor
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +--
drivers/gpu/drm/amd/amdgpu/nv.c| 2 +-
2 files changed, 18 insertions(+), 3 dele
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 38 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 205 +
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 78 ++
1 file changed, 42 insertions(+), 36 deletions(
Am 08.04.21 um 09:13 schrieb Christian König:
Am 07.04.21 um 21:04 schrieb Alex Deucher:
On Wed, Apr 7, 2021 at 3:23 AM Dave Airlie wrote:
On Wed, 7 Apr 2021 at 06:54, Alex Deucher
wrote:
On Fri, Apr 2, 2021 at 12:22 PM Christian König
wrote:
Hey Alex,
the TTM and scheduler changes should
On Thu, Apr 01, 2021 at 04:40:33PM +0300, Jani Nikula wrote:
> On Fri, 26 Mar 2021, Lyude Paul wrote:
> > Since it's been asked quite a few times on some of the various DP
> > related patch series I've submitted to use the new DRM printk helpers,
> > and it technically wasn't really trivial to do
On Wed, Apr 07, 2021 at 04:25:51PM +0800, Du, Xiaojian wrote:
> This patch is to add the callback to get vbios bootup values for
> vangogh, it will get the bootup values of gfxclk, mclk, socclk and so
> on.
>
> Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/s
On Thu, 08 Apr 2021, Daniel Vetter wrote:
> I think Dave caught up on pulls to drm-next, so after a backmerge of that
> to drm-misc-next I think should be all fine to apply directly, no need for
> topic branch.
Yup. We've done the backmerges to drm-intel-next and drm-intel-gt-next,
and are all in
On Tue, Apr 06, 2021 at 11:08:55AM +0200, Thomas Zimmermann wrote:
> Implement mmap via struct drm_gem_object_functions.mmap for amdgpu,
> radeon and nouveau. This allows for using common DRM helpers for
> the mmap-related callbacks in struct file_operations and struct
> drm_driver. The drivers hav
No functional changes, just cleaning up some leftovers and improve
documentation.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 173 ++-
1 file changed, 93 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.
Avoid the forward define, fix coding style, add documentation.
No functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 169 +++-
1 file changed, 90 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_m
Hi
Am 08.04.21 um 13:19 schrieb Daniel Vetter:
On Tue, Apr 06, 2021 at 11:08:55AM +0200, Thomas Zimmermann wrote:
Implement mmap via struct drm_gem_object_functions.mmap for amdgpu,
radeon and nouveau. This allows for using common DRM helpers for
the mmap-related callbacks in struct file_operat
On Thu, Apr 08, 2021 at 01:38:59PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 08.04.21 um 13:19 schrieb Daniel Vetter:
> > On Tue, Apr 06, 2021 at 11:08:55AM +0200, Thomas Zimmermann wrote:
> > > Implement mmap via struct drm_gem_object_functions.mmap for amdgpu,
> > > radeon and nouveau. This al
Both patches are Reviewed-by: Nirmoy Das
On 4/8/21 1:29 PM, Christian König wrote:
No functional changes, just cleaning up some leftovers and improve
documentation.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 173 ++-
1 file changed, 93
On Thu, Apr 8, 2021 at 6:28 AM Christian König
wrote:
>
> Am 08.04.21 um 09:13 schrieb Christian König:
> > Am 07.04.21 um 21:04 schrieb Alex Deucher:
> >> On Wed, Apr 7, 2021 at 3:23 AM Dave Airlie wrote:
> >>> On Wed, 7 Apr 2021 at 06:54, Alex Deucher
> >>> wrote:
> On Fri, Apr 2, 2021 at
On Thu, Apr 8, 2021 at 6:03 AM Daniel Vetter wrote:
>
> On Thu, Apr 01, 2021 at 06:56:09AM +1000, Dave Airlie wrote:
> > I think this is due to this pull, on arm32.
> >
> > /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:
> > In function ‘dmub_srv_hw_in
From: Jiange Zhao
Add MB_REQ_MSG_READY_TO_RESET response when VF get FLR notification.
When guest received FLR notification from host, it would
lock adapter into reset state. There will be no more
job submission and hardware access after that.
Then it should send a response to host that it has p
From: Jiange Zhao
Add MB_REQ_MSG_READY_TO_RESET response when VF get FLR notification.
When guest received FLR notification from host, it would
lock adapter into reset state. There will be no more
job submission and hardware access after that.
Then it should send a response to host that it has p
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:941:13: warning:
‘dm_dmub_trace_high_irq’ defined but not used [-Wunused-function]
941 | static void dm_dmub_trace_high_irq(void *interrupt_params)
| ^~
Fixes: 83b39e1fc3ea ("drm/amd/display: Log D
Given the number of call-sites being modified in this patch series,
would it be easier (and more maintainable) to change the behaviour or
the regular register macros and add NO_RLC versions for the exceptions,
similar to NO_KIQ?
Regards,
Felix
Am 2021-04-08 um 6:21 a.m. schrieb Peng Ju Zhou:
>
On Mon, Apr 05, 2021 at 09:45:55PM -0400, Felix Kuehling wrote:
> Rebased on upstream. Dropped already upstream patch
> "drm/amdgpu: reserve fence slot to update page table".
>
> Added more fixes:
> - Fixed kernel test robot warnings about static functions
> - Fixed a kernel test robot warning abo
On 2021-04-08 8:41 a.m., Shaokun Zhang wrote:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:941:13: warning:
‘dm_dmub_trace_high_irq’ defined but not used [-Wunused-function]
941 | static void dm_dmub_trace_high_irq(void *interrupt_params)
| ^~
Am 2021-04-08 um 11:02 a.m. schrieb Jason Gunthorpe:
> On Mon, Apr 05, 2021 at 09:45:55PM -0400, Felix Kuehling wrote:
>> Rebased on upstream. Dropped already upstream patch
>> "drm/amdgpu: reserve fence slot to update page table".
>>
>> Added more fixes:
>> - Fixed kernel test robot warnings about
From: Joshua Aberback
[Why]
Update SR Exit Latency to fix screen flickering caused due to OTG
underflow
Signed-off-by: Joshua Aberback
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dri
[AMD Official Use Only - Internal Distribution Only]
Hi Jay,
Could you please add few details on the root cause, in the [Why/How] section?
Thanks,
Bindu
From: Aurabindo Pillai
Sent: Thursday, April 8, 2021 11:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Pilla
On 2021-04-08 4:32 a.m., Christian König wrote:
Am 08.04.21 um 10:22 schrieb Christian König:
Hi Andrey,
Am 07.04.21 um 21:44 schrieb Andrey Grodzovsky:
On 2021-04-07 6:28 a.m., Christian König wrote:
Hi Andrey,
Am 06.04.21 um 23:22 schrieb Andrey Grodzovsky:
Hey Christian, Denis, see
[AMD Official Use Only - Internal Distribution Only]
Hi Bindu,
The value is recommended by the hardware team. Since a non-recommended value
was being used, that itself is the root cause. I will add this to commit
message.
--
Thanks & Regards,
Aurabindo Pillai
From: Joshua Aberback
[Why&How]
Update SR Exit Latency to fix screen flickering caused due to OTG
underflow. This is the recommended value given by the hardware IP team.
Signed-off-by: Joshua Aberback
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +
On 2021-04-08 1:10 p.m., Aurabindo Pillai wrote:
From: Joshua Aberback
[Why&How]
Update SR Exit Latency to fix screen flickering caused due to OTG
underflow. This is the recommended value given by the hardware IP team.
Signed-off-by: Joshua Aberback
Acked-by: Aurabindo Pillai
Reviewed-by:
Thank you Harry.
On 2021-04-08 1:46 p.m., Harry Wentland wrote:
On 2021-04-08 1:10 p.m., Aurabindo Pillai wrote:
From: Joshua Aberback
[Why&How]
Update SR Exit Latency to fix screen flickering caused due to OTG
underflow. This is the recommended value given by the hardware IP team.
Signed-of
On 2021-04-07 5:49 p.m., Rodrigo Siqueira wrote:
Our driver supports overlay planes, and as expected, some userspace
compositor takes advantage of these features. If the userspace is not
enabling the cursor, they can use multiple planes as they please.
Nevertheless, we start to have constraint
JFYI too - there was a legitimate looking CI failure on intel with this series,
so don't be surprised if I have to respin a patch or two (I should be able to
get it asap as I finally just cleared most of the stuff on my plate off for a
while)
On Thu, 2021-04-08 at 14:13 +0300, Jani Nikula wrote:
>
Am 08.04.21 um 18:08 schrieb Andrey Grodzovsky:
On 2021-04-08 4:32 a.m., Christian König wrote:
Am 08.04.21 um 10:22 schrieb Christian König:
[SNIP]
Beyond blocking all delayed works and scheduler threads we also
need to guarantee no IOCTL can access MMIO post device unplug OR
in flight I
From: Mark Yacoub
On reporting back the frame number of the CRCs through
drm_crtc_add_crc_entry(), send back the vblank count at the time the frame
CRC starts calculating rather than when the CRCs are ready to be
reported.
Tested by running IGT module: kms_plane::capture_crc()
Cc: Harry Wentlan
Applied. Thanks.
Alex
On Thu, Apr 8, 2021 at 11:09 AM Harry Wentland wrote:
>
> On 2021-04-08 8:41 a.m., Shaokun Zhang wrote:
> > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:941:13:
> > warning: ‘dm_dmub_trace_high_irq’ defined but not used [-Wunused-function]
> >941 | stat
Applied. Thanks!
Alex
On Wed, Apr 7, 2021 at 2:23 AM wrote:
>
> From: Yingjie Wang
>
> In radeon_dp_mst_detect(), We should check whether or not @connector
> has been unregistered from userspace. If the connector is unregistered,
> we should return disconnected status.
>
> Fixes: 9843ead08f18
On 2021-04-08 2:58 p.m., Christian König wrote:
Am 08.04.21 um 18:08 schrieb Andrey Grodzovsky:
On 2021-04-08 4:32 a.m., Christian König wrote:
Am 08.04.21 um 10:22 schrieb Christian König:
[SNIP]
Beyond blocking all delayed works and scheduler threads we also
need to guarantee no IOCTL
[AMD Official Use Only - Internal Distribution Only]
Hi Felix
That is a great idea, I will try it.
--
BW
Pengju Zhou
-Original Message-
From: Kuehling, Felix
Sent: Thursday, April 8, 2021 10:58 PM
To: Zhou, Peng Ju
From: Yingjie Wang
In dm_dp_mst_detect(), We should check whether or not @connector
has been unregistered from userspace. If the connector is unregistered,
we should return disconnected status.
Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
Signed-off-by: Yingjie Wang
---
drive
Hello,
(There are so many maintainers for kfd_iommu.c I feel like I'm spamming.)
When compiling for Linux version 5.11.12 using the AMDGPU GPU driver
with HSA_AMD enabled, I get the below set of errors. To work around this,
I need to change AMD_IOMMU_V2 from M to Y. This bug doesn't affect linux
k
This should have been fixed by this commit in amd-staging-drm-next:
https://lore.kernel.org/patchwork/patch/1392368/
commit b8aff1f3a0b3d8434f8ccf5d3017137c29aca77b
Author: Felix Kuehling
Date: Mon Mar 8 22:15:42 2021 -0500
drm/amdkfd: fix build error with AMD_IOMMU_V2=m
Using '
Am 08.04.21 um 22:39 schrieb Andrey Grodzovsky:
On 2021-04-08 2:58 p.m., Christian König wrote:
Am 08.04.21 um 18:08 schrieb Andrey Grodzovsky:
On 2021-04-08 4:32 a.m., Christian König wrote:
Am 08.04.21 um 10:22 schrieb Christian König:
[SNIP]
Beyond blocking all delayed works and schedu
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