On 2021-09-24 15:58, Alex Deucher wrote:
> On Thu, Sep 23, 2021 at 11:43 AM Harry Wentland
> wrote:
>>
>> On 2021-09-21 14:06, Alex Deucher wrote:
>>> So we can track grab the appropriate DCE info out of the
>>> IP discovery table. This is a separare IP from DCN.
>>>
>>
>> I've never looked a
On Thu, Sep 23, 2021 at 11:43 AM Harry Wentland wrote:
>
> On 2021-09-21 14:06, Alex Deucher wrote:
> > So we can track grab the appropriate DCE info out of the
> > IP discovery table. This is a separare IP from DCN.
> >
>
> I've never looked at the HWID stuff before. Do I understand it correctly
On Thu, Sep 23, 2021 at 06:04:34PM -0400, Mukul Joshi wrote:
> On Aldebaran, GPU driver will handle bad page retirement
> for GPU memory even though UMC is host managed. As a result,
> register a bad page retirement handler on the mce notifier
> chain to retire bad pages on Aldebaran.
>
> Signed-o
On Thu, Sep 23, 2021 at 08:14:15PM +0200, Borislav Petkov wrote:
> On Thu, Sep 23, 2021 at 05:23:21PM +, Yazen Ghannam wrote:
> > Shouldn't the error still be reported to EDAC for decoding and counting? I
> > think users want this.
>
> You know what happens with users getting ECCs reported, ri
From: George Shen
[Why]
Recently debugging efforts have involved setting/checking the
X.Y value used during payload allocation. Current output for
Y was calculated with incorrect bitshift. Y value is also not
human readable.
[How]
Refactor logging into separate function. Fix Y calculation error
From: Charlene Liu
[why]
pci deviceid not passed to dal dc, without proper break,
dcn2.x falls into dcn3.x code path
[how]
pass in pci deviceid, and break once dal_version initialized.
Reviewed-by: Zhan Liu
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/am
From: George Shen
[Why/How]
Theoretically rare corner case where ceil(Y) results in rounding
up to an integer. If this happens, the 1 should be carried over to
the X value.
Reviewed-by: Wenjing Liu
Acked-by: Anson Jacob
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn1
From: Wenjing Liu
[why]
There is a chance verified link cap can be greater than max link cap.
This causes software hang because we cannot power up PHY with link rate
that cannot handle.
The change is to guard verfieid link cap from becoming larger than max link cap
our PHy can support.
Reviewed-
From: Josip Pavic
[Why]
Stack variable params.backlight_ramping_override is uninitialized, so it
contains junk data
[How]
Initialize the variable to false
Reviewed-by: Roman Li
Acked-by: Anson Jacob
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 fi
From: Qingqing Zhuo
[Why]
DC should be used in place of DAL in
upstream.
[How]
Replace dal with dc in function names.
Reviewed-by: Rodrigo Siqueira
Acked-by: Anson Jacob
Signed-off-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
drivers/gpu/drm/amd
From: Michael Strauss
[WHY]
Blnd, 3dlut, and shaper LUT select registers are double buffered, however
their accompanying LUT memory shutdown registers are not. As a result,
shutting down LUT memory immediately after setting a block to bypass causes
corruption as bypass only happens at next Vupdat
From: Aric Cyr
This version brings along following fixes:
- Fixes to backlight, LUT, PPS, MST
- Use correct vpg for 128b/132b encoding
- Improved logging for VCP
- Replace referral of dal with dc
Acked-by: Anson Jacob
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 f
From: Anthony Koo
Acked-by: Anson Jacob
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
inde
From: Ilya
[Why]
This change is needed for DCN2 to make use of the immediate_update
flag. With this flag, update to PPS will be immediate, rather than
always taking place on dig_update signal.
[How]
Set AFMT_GENERIC7_FRAME/IMMEDIATE_UPDATE bits depending on flag
value.
Reviewed-by: Wenjing Liu
From: Oliver Logush
Reviewed-by: Charlene Liu
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Oliver Logush
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 6 --
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
From: Jimmy Kizito
[Why]
MST streams share the same link and should share the same encoder.
The current availability check may erroneously determine that an
encoder is unavailable for MST streams.
[How]
When checking for link encoder availability, check if an encoder
in use shares a link with th
From: Meenakshikumar Somasundaram
[Why]
Link encoder in the link could be null for certain links.
[How]
If link encoder in the link is null then get the link encoder
from the stream.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Meenakshikumar Somasundaram
---
drivers/gpu/drm/am
From: Wenjing Liu
[why]
option 1: disallow different lanes to have different lane settings
option 2: dpcd lane settings will always use the same hw lane settings
even if it doesn't match requested lane adjust
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../gpu/
From: Wenjing Liu
[why]
As DP features expands, we have encountered many situations where we
must configure a different DPCD lane setting from hw lane settings we output.
The change is to decouple hw lane settings from dpcd lane settings to provide
flexibility to configure dpcd and hw individuall
From: Wenjing Liu
[why]
This is one of the major steps to decouple hw lane settings
from dpcd lane settings.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++--
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 38 +
From: Wenjing Liu
[why]
Decouple lane settings decision logic all to its own function.
The function takes in lane adjust array and link training settings
and decide what hw lane setting and dpcd lane setting should be used.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
From: Wenjing Liu
[why]
Unify the code which handles the conversion between hw lane setting
and dpcd lane setting.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 113 ++
.../gpu/drm/amd/display/dc/inc/
From: Wenjing Liu
[why]
To support per lane lane setting adjustment, we need to change cur_lane_setting
to an array one for each lane as the first step.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 +++
From: Eric Yang
[Why]
To prevent unnecessary wake up of DMCUB when ABM is enabled without PSR
enabled, driver will notify DMCUB to stop ABM's vertical interrupts
if vsync is disabled and steady state is reached.
[How]
Send inbox message to notify ABM pause based on vsync on/off
Reviewed-by: Nic
From: David Galiffi
[Why]
Requested feature to assist with Thermal, Acoustic, Power, and
Performance tuning.
[How]
Add a debug field that will override calculated minimum DRAM clock,
if the debug value is larger than the calculate value.
Reviewed-by: Alvin Lee
Acked-by: Anson Jacob
Signed-off
From: Michael Strauss
[WHY]
AFMT is unused for DP audio, so powering it on for DP is unnecessary.
[HOW]
APG block should be powered down instead, however HW defaults to shutdown
state when not enabled so no further work is required.
Reviewed-by: Wenjing Liu
Acked-by: Anson Jacob
Signed-off-by
From: Anthony Koo
Acked-by: Anson Jacob
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
inde
From: Wenjing Liu
[why]
128b/132b uses the vpg instance assigned to hpo dp stream encoder.
The current vpg used is assigned to dio stream encoder.
This is incorrect and cause display black screen because the
actual vpg is powered off.
Reviewed-by: Michael Strauss
Acked-by: Anson Jacob
Signed-o
This DC patchset brings improvements in multiple areas. In summary, we
have:
- Fixes to backlight, LUT, PPS, MST
- Use correct vpg for 128b/132b encoding
- Improved logging for VCP
- Replace referral of dal with dc
Anthony Koo (2):
drm/amd/display: [FW Promotion] Release 0.0.85
On 9/24/21 4:51 AM, Borislav Petkov wrote:
On Fri, Sep 24, 2021 at 12:41:32PM +0300, Kirill A. Shutemov wrote:
On Thu, Sep 23, 2021 at 08:21:03PM +0200, Borislav Petkov wrote:
On Thu, Sep 23, 2021 at 12:05:58AM +0300, Kirill A. Shutemov wrote:
Unless we find other way to guarantee RIP-relative
On Fri, Sep 24, 2021 at 12:41:32PM +0300, Kirill A. Shutemov wrote:
> On Thu, Sep 23, 2021 at 08:21:03PM +0200, Borislav Petkov wrote:
> > On Thu, Sep 23, 2021 at 12:05:58AM +0300, Kirill A. Shutemov wrote:
> > > Unless we find other way to guarantee RIP-relative access, we must use
> > > fixup_poi
On Thu, Sep 23, 2021 at 08:21:03PM +0200, Borislav Petkov wrote:
> On Thu, Sep 23, 2021 at 12:05:58AM +0300, Kirill A. Shutemov wrote:
> > Unless we find other way to guarantee RIP-relative access, we must use
> > fixup_pointer() to access any global variables.
>
> Yah, I've asked compiler folks a
[AMD Official Use Only]
>-Original Message-
>From: Christian König
>Sent: Friday, September 24, 2021 2:37 PM
>To: Yu, Lang ; Koenig, Christian
>; amd-gfx@lists.freedesktop.org
>Cc: Kuehling, Felix ; Huang, Ray
>
>Subject: Re: [PATCH] drm/kfd: fix ttm_bo_release warning
>
>Am 24.09.21 um
In ras poison mode, page retirement will be handled by the irq handler of the
module which consumes corrupted data.
v2: rename ras_process_cb to ras_poison_consumption_handler.
move the handler's implementation from ASIC specific file to common
file.
Signed-off-by: Tao Zhou
---
drivers/gpu/
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