Re: [linux-next:master] BUILD REGRESSION 8cb8311e95e3bb58bd84d6350365f14a718faa6d

On Wed, May 25, 2022 at 03:20:06PM -0700, Andrew Morton wrote: > On Wed, 25 May 2022 23:07:35 +0100 Jessica Clarke wrote: > > > This is i386, so an unsigned long is 32-bit, but i_blocks is a blkcnt_t > > i.e. a u64, which makes the shift without a cast of the LHS fishy. > > Ah, of course,

Re: [linux-next:master] BUILD REGRESSION 8cb8311e95e3bb58bd84d6350365f14a718faa6d

On Wed, 25 May 2022 23:07:35 +0100 Jessica Clarke wrote: > This is i386, so an unsigned long is 32-bit, but i_blocks is a blkcnt_t > i.e. a u64, which makes the shift without a cast of the LHS fishy. Ah, of course, thanks. I remember 32 bits ;) ---

Re: [linux-next:master] BUILD REGRESSION 8cb8311e95e3bb58bd84d6350365f14a718faa6d

On Thu, 26 May 2022 05:35:20 +0800 kernel test robot wrote: > tree/branch: > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master > branch HEAD: 8cb8311e95e3bb58bd84d6350365f14a718faa6d Add linux-next > specific files for 20220525 > > Err

Re: [PATCH] drm/amdkfd: don't add DOORBELL and MMIO BOs to validate list

On 2022-05-25 06:37, Christian König wrote: Am 25.05.22 um 11:25 schrieb Lang Yu: On 05/25/ , Christian König wrote: Am 25.05.22 um 10:43 schrieb Lang Yu: DOORBELL and MMIO BOs never move once created. No need to validate them after that. Yeah, but you still need to make sure their page

Re: [linux-next:master] BUILD REGRESSION 8cb8311e95e3bb58bd84d6350365f14a718faa6d

Add linux-next >> specific files for 20220525 >> >> Error/Warning reports: >> >> ... >> >> Unverified Error/Warning (likely false positive, please contact us if >> interested): > > Could be so. > >> mm/shmem.c:1948 shmem_g

[PATCH 14/43] drm/amd: Add GFX11 modifiers support to AMDGPU (v3)

From: Aurabindo Pillai GFX11 IP introduces new tiling mode. Various combinations of DCC settings are possible and the most preferred settings must be exposed for optimal use of the hardware. add_gfx11_modifiers() is based on recommendation from Marek for the preferred tiling modifier that are

[linux-next:master] BUILD REGRESSION 8cb8311e95e3bb58bd84d6350365f14a718faa6d

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 8cb8311e95e3bb58bd84d6350365f14a718faa6d Add linux-next specific files for 20220525 Error/Warning reports: https://lore.kernel.org/linux-mm/202204291924.vtgzmeri-...@intel.com https

[PATCH 14/43] drm/amd: Add GFX11 modifiers support to AMDGPU (v2)

From: Aurabindo Pillai GFX11 IP introduces new tiling mode. Various combinations of DCC settings are possible and the most preferred settings must be exposed for optimal use of the hardware. add_gfx11_modifiers() is based on recommendation from Marek for the preferred tiling modifier that are

Re: [PATCH] amdgpu: amdgpu_device.c: Removed trailing whitespace

Applied. Thanks! Alex On Wed, May 25, 2022 at 4:38 PM Mitchell Augustin wrote: > > Removed trailing whitespace from end of line in amdgpu_device.c > > Signed-off-by: Mitchell Augustin > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- > 1 file changed, 2 insertions(+), 2

[PATCH] amdgpu: amdgpu_device.c: Removed trailing whitespace

Removed trailing whitespace from end of line in amdgpu_device.c Signed-off-by: Mitchell Augustin --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Re: [PATCH 14/43] drm/amd: Add GFX11 modifiers support to AMDGPU

On Wed, May 25, 2022 at 12:20 PM Alex Deucher wrote: > From: Aurabindo Pillai > > GFX11 IP introduces new tiling mode. Various combinations of DCC > settings are possible and the most preferred settings must be exposed > for optimal use of the hardware. > > add_gfx11_modifiers() is based on

[PATCH v3 6/7] drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover

We removed the wrapper that was queueing the recover function into reset domain queue who was using this name. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |

[PATCH v3 7/7] drm/amdgpu: Stop any pending reset if another in progress.

We skip rest requests if another one is already in progress. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 27 ++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

[PATCH v3 5/7] drm/amdgpu: Add work_struct for GPU reset from kfd.

We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31

[PATCH v3 4/7] drm/amdgpu: Add work_struct for GPU reset from debugfs

We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 19 +-- 2 files changed, 19 insertions(+), 2 deletions(-) diff

[PATCH v3 2/7] drm/amdgpu: Cache result of last reset at reset domain level.

Will be read by executors of async reset like debugfs. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 -- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-)

[PATCH v3 3/7] drm/admgpu: Serialize RAS recovery work directly into reset domain queue.

Save the extra usless work schedule. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index

[PATCH v3 1/7] Revert "workqueue: remove unused cancel_work()"

This reverts commit 6417250d3f894e66a68ba1cd93676143f2376a6f. amdpgu need this function in order to prematurly stop pending reset works when another reset work already in progress. Signed-off-by: Andrey Grodzovsky Reviewed-by: Lai Jiangshan Reviewed-by: Christian König ---

[PATCH v3 0/7] Fix multiple GPU resets in XGMI hive.

Problem: During hive reset caused by command timing out on a ring extra resets are generated by triggered by KFD which is unable to accesses registers on the resetting ASIC. Fix: Rework GPU reset to actively stop any pending reset works while another in progress. v2: Switch from generic list as

Re: [PATCH] drm/amdgpu: make program_imu_rlc_ram static

Applied. Thanks! Alex On Wed, May 25, 2022 at 5:37 AM Jiapeng Chong wrote: > > This symbol is not used outside of imu_v11_0.c, so marks it > static. > > Fixes the following w1 warning: > > drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:302:6: warning: no previous > prototype for ‘program_imu_rlc_ram’

Re: [PATCH 00/14] drm/kms: Stop registering multiple /sys/class/backlight devs for a single display

On 5/18/22 03:44, Jani Nikula wrote: On Tue, 17 May 2022, Hans de Goede wrote: Hi All, As mentioned in my RFC titled "drm/kms: control display brightness through drm_connector properties": https://lore.kernel.org/dri-devel/0d188965-d809-81b5-74ce-7d30c49fe...@redhat.com/ The first step

[PATCH 26/43] drm/amd/display: Add additional guard for FCLK pstate message for DCN321

From: Dillon Varone Signed-off-by: Fangzhi Zuo Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH 40/43] drm/amd/display: Updates for OTG and DCCG clocks

From: Samson Tam Use DTBCLK for valid pixel clock generation Signed-off-by: Samson Tam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 5 - drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h |

[PATCH 22/43] drm/amd/display: disable idle optimizations

From: Aurabindo Pillai Disable idle optimizations until SMU can handle them to prevent DMUB timeout and subsequent system freeze Signed-off-by: Aurabindo Pillai Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 + 1 file changed, 1

[PATCH 17/43] drm/amd/display: Use DTBCLK for valid pixel clock

From: Eric Bernstein Use DTBCLK for valid pixel clock generation Signed-off-by: Eric Bernstein Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 15 +-- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h| 17 + 2

[PATCH 43/43] drm/amd/display: Drop unnecessary guard from DC resource

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c

[PATCH 41/43] drm/amd/display: Implement DTBCLK ref switching on dcn32

From: Alvin Lee [WHY & HOW] Implements DTB ref clock switching with reg key default to OFF. Refactors dccg DTBCLK logic to not store redundant state information dccg. Also removes duplicated functions that should be inherited from other dcn versions. Signed-off-by: Alvin Lee Signed-off-by:

[PATCH 35/43] drm/amd/display: update disp pattern generator routine for DCN30

From: Aurabindo Pillai Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 33 ++- 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

[PATCH 31/43] drm/amd/display: do not override CURSOR_REQ_MODE when SubVP is not enabled

From: Samson Tam [Why] HUBP_UNBOUNDED_REQ_MODE and CURSOR_REQ_MODE are normally set together. In hubp32_prepare_subvp_buffering() call, CURSOR_REQ_MODE is set based on whether SubVP is enabled or not. For non MPO case, both REQ_MODE registers are set to 1. But since SubVP is not enabled, then

[PATCH 30/43] drm/amd/display: change dsc image width cap for dcn32 and dcn321

From: Dillon Varone Set appropriate caps for DCN3.2.x. Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 3 +++ 2 files changed, 6 insertions(+) diff --git

[PATCH 36/43] drm/amd/display: cleaning up smu_if to add future flexibility

From: Martin Leung This commit cleans up code that uses old variables and adds some SMU interfaces for future flexibility. Signed-off-by: Martin Leung Signed-off-by: Alex Deucher --- .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 19 +++--- .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 7

[PATCH 25/43] drm/amd/display: Ensure that DMCUB fw in use is loaded by DC and not VBIOS

From: Dillon Varone [Why?] On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads DMUB, and driver does not reload as it appears to be initialized already. [How?] Add a check for the DAL_FW bit to ensure that loaded FW is from driver and not VBIOS. Signed-off-by: Fangzhi

[PATCH 24/43] drm/amd/display: use updated clock source init routine

From: Charlene Liu [why] Use correct clock source initialization routine for DCN32/321 Signed-off-by: Charlene Liu Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-

[PATCH 29/43] drm/amd/display: Disable DTB Ref Clock Switching in dcn32

From: Dillon Varone [How & Why] To be enabled once PMFW supports it. Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 drivers/gpu/drm/amd/display/dc/dc.h | 1 - 2 files changed, 4

[PATCH 20/43] drm/amd/display: Implement WM table transfer for DCN32/DCN321

From: Alvin Lee Add support for watermark table transfers. Signed-off-by: Alvin Lee Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 7 +++ 1 file changed, 7 insertions(+) diff --git

[PATCH 42/43] drm/amd/display: Add ODM seamless boot support

From: Duncan Ma Revised validation logic when marking for seamless boot. Init resources accordingly when Pre-OS has ODM enabled. Reset ODM when transitioning Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set odm accordingly upon commit. Signed-off-by: Duncan Ma

[PATCH 13/43] drm/amd/display: add DCN32 to IP discovery table

From: Aurabindo Pillai [Why] Add DCN32 to IP discovery to enable automatic initialization of AMDGPU Display Manager Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 ++ 1 file changed, 2 insertions(+)

[PATCH 38/43] drm/amd/display: Introduce new update_clocks logic

From: Jun Lei [why] DCN has sidebands to control some clocks, it is useful for clk_mgr to always update the clocks it explicitly controls rather than skip them because it enables more configurations to work without SMU [how] only skip handling clocks where SMU manages the frequency for clocks

[PATCH 27/43] drm/amd/display: Halve DTB Clock Value for DCN32

From: Fangzhi Zuo VBIOS default clock value was halved, so the hardcoded dtb value should be halved as well. dtb clock should come from SMU eventually, but now dtb clock switching is not fully supported yet in SMU. Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on SMU

[PATCH 37/43] drm/amd/display: Match dprefclk with clk registers

From: Samson Tam Update base.dprefclk_khz to match result from dcn32_dump_clk_registers() Signed-off-by: Samson Tam Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git

[PATCH 34/43] drm/amd/display: set link fec status during init for DCN32

From: Jingwen Zhu We can now enable FEC. Signed-off-by: Jingwen Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

[PATCH 33/43] drm/amd/display: add new pixel rate programming

From: Jun Lei [why] New dividers in DCCG need to be programmed depending on encoder/stream type since pixels per clock in OTG/DIO is different DIO also needs additional programming depending on pixels per clock Signed-off-by: Jun Lei Signed-off-by: Alex Deucher Signed-off-by: Rodrigo

[PATCH 21/43] drm/amd/display: add missing interrupt handlers for DCN32/DCN321

From: Aurabindo Pillai Signed-off-by: Aurabindo Pillai Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- .../display/dc/irq/dcn32/irq_service_dcn32.c | 65 ++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git

[PATCH 39/43] drm/amd/display: FCLK P-state support updates

From: Chaitanya Dhere [Why] Previously we used to send FCLK P-state enable messages upon each call to update_clocks based on dml output. This resulted in increased message transactions between DC and PMFW. [How] Update the code to check safe_to_lower status and send the message based on dml

[PATCH 28/43] drm/amd/display: set dram speed for all states

From: Dillon Varone [WHY?] If higher states have memory speed set to 0 MT/s currently they do not get set to the highest value which can cause validation failures. [HOW?] Set unpopulated higher states to max value. Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher ---

[PATCH 32/43] drm/amd/display: Remove W/A for ODM memory pins

From: Alvin Lee [Description] By default we can now set ODM_MEM_VBLANK_PWR_MODE=1 Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +- 2 files changed, 2

[PATCH 14/43] drm/amd: Add GFX11 modifiers support to AMDGPU

From: Aurabindo Pillai GFX11 IP introduces new tiling mode. Various combinations of DCC settings are possible and the most preferred settings must be exposed for optimal use of the hardware. add_gfx11_modifiers() is based on recommendation from Marek for the preferred tiling modifier that are

[PATCH 18/43] drm/amd/display: Add guard for FCLK pstate message to PMFW for DCN321

From: Dillon Varone [WHY?] DCN321 does not support FCLK DPM, and thus it should not send messages to PMFW regarding it. Signed-off-by: Dillon Varone Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 ++- 1 file changed, 2

[PATCH 15/43] drm/amd/display: Fix USBC link creation

From: Dillon Varone [Description] Add USBC connector ID to align with new VBIOS parsing. Add seperate DCN321 link encoder due to different PHY version affecting DP ALT related registers. Signed-off-by: Dillon Varone Acked-by: Jerry Zuo Signed-off-by: Alex Deucher ---

[PATCH 16/43] drm/amd/display: Add missing instance for clock source register

From: Alvin Lee [Description] Need to add inst 5 for clk_src_regs because there are 5 PHY instances in DCN32 & DCN321. Signed-off-by: Alvin Lee Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3 ++-

[PATCH 23/43] drm/amd/display: Select correct DTO source

From: Dillon Varone [WHY] Change criteria for setting DTO source value, and always set it regardless of the signal type. Signed-off-by: Dillon Varone Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce/dce_clock_source.c | 27 +++ 1 file

[PATCH 19/43] drm/amd/display: Various DML fixes to enable higher timings

From: Dillon Varone Fixes to enable higher rate timings for DCN3.2.x. Signed-off-by: Dillon Varone Signed-off-by: Chaitanya Dhere Signed-off-by: Nevenko Stupar Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn32/dcn32_hubbub.c | 4 +--

[PATCH 11/43] drm/amd/display: Add dependant changes for DCN32/321

From: Aurabindo Pillai [Why] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/Makefile | 2 +

[PATCH 12/43] drm/amd/display: Add DM support for DCN32/DCN321

From: Aurabindo Pillai Add Display Manager specific changes for DCN3.2.x. DM handles the interaction between the core DC modesetting code and the drm modesetting infrastructure. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher ---

[PATCH 07/43] drm/amd/display: add GPIO changes for DCN32/321

From: Aurabindo Pillai Add support for the GPIO changes for DCN3.2.x. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/gpio/Makefile | 8 +- .../display/dc/gpio/dcn32/hw_factory_dcn32.c | 255 +

[PATCH 09/43] drm/amd/display: add CLKMGR changes for DCN32/321

From: Aurabindo Pillai Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by: Aurabindo Pillai Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 35 +

[PATCH 05/43] drm/amd/display: Add DMCUB source files and changes for DCN32/321

From: Aurabindo Pillai DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 31 ++

[PATCH 03/43] drm/amd/display: Add DCN32/321 version identifiers

From: Aurabindo Pillai Add DCN3.2 asic identifiers. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 ++ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 8

[PATCH 06/43] drm/amd/display: add dcn32 IRQ changes

From: Aurabindo Pillai Add DCN3.2.x interrupt support. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +- .../display/dc/irq/dcn32/irq_service_dcn32.c | 367 ++

[PATCH 02/43] drm/amd: Add atomfirmware.h definitions needed for DCN32/321

From: Aurabindo Pillai Add new structures for DCN 3.2.x. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 209 ++--- 1 file changed, 187 insertions(+), 22 deletions(-) diff --git

[PATCH 01/43] drm/amd/display: remove stale config guards

From: Aurabindo Pillai Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c | 2 -- 2 files changed, 4 deletions(-) diff --git

[PATCH 00/43] Add support for DCN 3.2

These patches add support for DCN (Display Core Next) version 3.2.x. Patch 4 adds new register headers and is too big for the mailing list. Alvin Lee (4): drm/amd/display: Add missing instance for clock source register drm/amd/display: Implement WM table transfer for DCN32/DCN321

Re: [PATCH 00/14] drm/kms: Stop registering multiple /sys/class/backlight devs for a single display

On Wed, May 18, 2022 at 01:12:33PM +0300, Jani Nikula wrote: > On Wed, 18 May 2022, Hans de Goede wrote: > > Hi, > > > > On 5/18/22 10:44, Jani Nikula wrote: > >> On Tue, 17 May 2022, Hans de Goede wrote: > >>> Hi All, > >>> > >>> As mentioned in my RFC titled "drm/kms: control display

Re: [RFC PATCH v2 00/27] DRM.debug on DYNAMIC_DEBUG, add trace events

On Mon, May 16, 2022 at 04:56:13PM -0600, Jim Cromie wrote: > DRM.debug API is 23 macros, issuing 10 exclusive categories of debug > messages. By rough count, they are used 5140 times in the kernel. > These all call drm_dbg or drm_devdbg, which call drm_debug_enabled(), > which checks bits in

Re: [PATCH] drm/amdgpu: Adjust logic around GTT size (v3)

Reviewed-by: Marek Olšák Marek On Fri, May 20, 2022 at 11:09 AM Alex Deucher wrote: > Certain GL unit tests for large textures can cause problems > with the OOM killer since there is no way to link this memory > to a process. This was originally mitigated (but not necessarily > eliminated)

RE: [PATCH 0/8] May 24, 2022

[AMD Official Use Only - General] Hi all, This week this patchset was tested on the following systems: HP Envy 360, with Ryzen 5 4500U Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U Sapphire Pulse RX5700XT Reference AMD RX6800 Engineering board with Ryzen 9 5900H These systems were

[PATCH] drm/amdgpu: make program_imu_rlc_ram static

This symbol is not used outside of imu_v11_0.c, so marks it static. Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:302:6: warning: no previous prototype for ‘program_imu_rlc_ram’ [-Wmissing-prototypes]. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong ---

Re: [PATCH v3 02/13] mm: handling Non-LRU pages returned by vm_normal_pages

Alex Sierra writes: > With DEVICE_COHERENT, we'll soon have vm_normal_pages() return > device-managed anonymous pages that are not LRU pages. Although they > behave like normal pages for purposes of mapping in CPU page, and for > COW. They do not support LRU lists, NUMA migration or THP. > >

答复: [PATCH Review v3 2/2] drm/amdgpu: print umc correctable error address

[AMD Official Use Only - General] [AMD Official Use Only - General] 发件人: Lazar, Lijo 日期: 星期三, 2022年5月25日 下午8:38 收件人: Yang, Stanley , amd-gfx@lists.freedesktop.org , Zhang, Hawking , Zhou1, Tao , Quan, Evan 主题: Re: [PATCH Review v3 2/2] drm/amdgpu: print umc correctable error address On

Re: [PATCH Review v3 2/2] drm/amdgpu: print umc correctable error address

On 5/25/2022 11:40 AM, Stanley.Yang wrote: Changed from V1: remove unnecessary same row physical address calculation Changed from V2: move record_ce_addr_supported to umc_ecc_info struct Signed-off-by: Stanley.Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 ++

Re: [PATCH Review v3 1/2] drm/amdgpu/pm: support mca_ceumc_addr in ecctable

On 5/25/2022 11:40 AM, Stanley.Yang wrote: SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Changed from V1: remove ecc_table_v2 and unnecessary table id, define union struct include

Re: [PATCH] drm/amdkfd: don't add DOORBELL and MMIO BOs to validate list

Am 25.05.22 um 13:37 schrieb Lang Yu: On 05/25/ , Christian König wrote: Am 25.05.22 um 11:25 schrieb Lang Yu: On 05/25/ , Christian König wrote: Am 25.05.22 um 10:43 schrieb Lang Yu: DOORBELL and MMIO BOs never move once created. No need to validate them after that. Yeah, but you still

Re: [PATCH] drm/amdkfd: don't add DOORBELL and MMIO BOs to validate list

Am 25.05.22 um 11:25 schrieb Lang Yu: On 05/25/ , Christian König wrote: Am 25.05.22 um 10:43 schrieb Lang Yu: DOORBELL and MMIO BOs never move once created. No need to validate them after that. Yeah, but you still need to make sure their page tables are up to date. So this here might break

Re: [PATCH] drm/amdkfd: don't add DOORBELL and MMIO BOs to validate list

Am 25.05.22 um 10:43 schrieb Lang Yu: DOORBELL and MMIO BOs never move once created. No need to validate them after that. Yeah, but you still need to make sure their page tables are up to date. So this here might break horrible. Christian. Signed-off-by: Lang Yu ---

[PATCH] drm/amdkfd: don't add DOORBELL and MMIO BOs to validate list

DOORBELL and MMIO BOs never move once created. No need to validate them after that. Signed-off-by: Lang Yu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

Re: [PATCH] drm: Don't block HDR_OUTPUT_METADATA on unknown EOTF

On Tue, 24 May 2022 14:33:20 -0400 Harry Wentland wrote: > The supported EOTFs are defined in eotf_supported in drm_edid > but userspace has no way of knowing what is and isn't supported > when creating an HDR_OUTPUT_METADATA and will only know > something is wrong when the atomic commit fails.

答复: [PATCH Review v3 2/2] drm/amdgpu: print umc correctable error address

[AMD Official Use Only - General] [AMD Official Use Only - General] 发件人: Wang, Yang(Kevin) 日期: 星期三, 2022年5月25日 下午2:52 收件人: Yang, Stanley , amd-gfx@lists.freedesktop.org , Zhang, Hawking , Zhou1, Tao , Quan, Evan , Lazar, Lijo 主题: Re: [PATCH Review v3 2/2] drm/amdgpu: print umc correctable

Re: [PATCH Review v3 2/2] drm/amdgpu: print umc correctable error address

[AMD Official Use Only - General] From: amd-gfx on behalf of Stanley.Yang Sent: Wednesday, May 25, 2022 2:10 PM To: amd-gfx@lists.freedesktop.org ; Zhang, Hawking ; Zhou1, Tao ; Quan, Evan ; Lazar, Lijo Cc: Yang, Stanley Subject: [PATCH Review v3 2/2] drm/amdgpu: print umc correctable

[PATCH Review v3 2/2] drm/amdgpu: print umc correctable error address

Changed from V1: remove unnecessary same row physical address calculation Changed from V2: move record_ce_addr_supported to umc_ecc_info struct Signed-off-by: Stanley.Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 ++ drivers/gpu/drm/amd/amdgpu/umc_v6_7.c |

[PATCH Review v3 1/2] drm/amdgpu/pm: support mca_ceumc_addr in ecctable

SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Changed from V1: remove ecc_table_v2 and unnecessary table id, define union struct include EccInfo_t and EccInfo_V2_t. Changed