On 5/10/23 22:54, Aurabindo Pillai wrote:
> On 5/10/23 09:20, Michel Dänzer wrote:
>> On 5/9/23 23:07, Pillai, Aurabindo wrote:
>>>
>>> Sorry - the firmware in the previous message is for DCN32. For Navi2x,
>>> please use the firmware attached here.
>>
>> Same problem (contents of /sys/kernel/debu
[Why]
UMD is not aware of entity error, and will keep submitting jobs
into the error entity.
[How]
Add entity error check when getting entity from ctx.
Signed-off-by: ZhenGuo Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --
Hey,
On 2023-05-10 20:46, Tejun Heo wrote:
> Hello,
>
> On Wed, May 10, 2023 at 04:59:01PM +0200, Maarten Lankhorst wrote:
>> The misc controller is not granular enough. A single computer may have any
>> number of
>> graphics cards, some of them with multiple regions of vram inside a single
>> c
On 10/05/2023 19:46, Tejun Heo wrote:
Hello,
On Wed, May 10, 2023 at 04:59:01PM +0200, Maarten Lankhorst wrote:
The misc controller is not granular enough. A single computer may have any
number of
graphics cards, some of them with multiple regions of vram inside a single card.
Extending th
Pointer mqd_mem_obj can be deallocated in kfd_gtt_sa_allocate().
The function then returns non-zero value, which causes the second deallocation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: d1f8f0d17d40 ("drm/amdkfd: Move non-sdma mqd allocation out of init_mqd")
Signe
Hi,
I notice a regression report on bugzilla ([1]). As many developers
don't keep an eye on it, I decide to forward it by email.
Quoting from it:
> darkbasic 2023-05-10 13:36:37 UTC
>
> I'm using Gentoo Linux on a Raptor CS Talos 2 ppc64le, GPU is an AMD RX 570.
> So far the past dozen of ker
Don't assume that only the driver would be accessing LNKCTL/LNKCTL2.
ASPM policy changes can trigger write to LNKCTL outside of driver's
control. And in the case of upstream (parent), the driver does not even
own the device it's changing the registers for.
Use pcie_lnkctl_clear_and_set() and pcie_
Don't assume that only the driver would be accessing LNKCTL/LNKCTL2.
ASPM policy changes can trigger write to LNKCTL outside of driver's
control. And in the case of upstream (parent), the driver does not even
own the device it's changing the registers for.
Use pcie_lnkctl_clear_and_set() and pcie_
Hi Dave, Daniel,
Fixes for 6.4.
The following changes since commit ac9a78681b921877518763ba0e89202254349d1b:
Linux 6.4-rc1 (2023-05-07 13:34:35 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.4-2023-05-11
for you to fetch
Use the new added capable_any function in appropriate cases, where a
task is required to have any of two capabilities.
Reorder CAP_SYS_ADMIN last.
Signed-off-by: Christian Göttsche
---
v4:
Additional usage in kfd_ioctl()
v3:
rename to capable_any()
---
drivers/gpu/drm/amd/amdkfd/kfd_chard
Implement get_vbios_fb_size() so we can properly reserve
the vbios splash screen to avoid potential artifacts on the
screen during the transition from the pre-OS console to the
OS console.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 21 -
1 file c
Fix whitespace issues and other trivial formatting fixes
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 27 ---
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/d
[Why&How]
Add some missing register definitions and rearrange some others to
maintain consistency with related definitions.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 69 +++
.../include/asic_reg/dcn/dcn_3_0_0_offset.h | 5 ++
.../inclu
[Why]
When unused, all memory blocks should be put in a low power state
[How]
Check the value of enable_mem_low_power.bits.vga and set
corresponding bit in the hardware register
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 5 +
1 file changed, 5 i
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: aabe491169befbe5481144acf575a0260939764a Add linux-next specific
files for 20230511
Warning reports:
https://lore.kernel.org/oe-kbuild-all/202304140707.coh337ux-...@intel.com
Warning
On 5/11/23 09:38, Aurabindo Pillai wrote:
[Why&How]
Add some missing register definitions and rearrange some others to
maintain consistency with related definitions.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 69 +++
.../include/asi
On 5/11/23 09:38, Aurabindo Pillai wrote:
Fix whitespace issues and other trivial formatting fixes
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 27 ---
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/am
On 5/11/23 09:38, Aurabindo Pillai wrote:
[Why]
When unused, all memory blocks should be put in a low power state
[How]
Check the value of enable_mem_low_power.bits.vga and set
corresponding bit in the hardware register
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc
From: Chong Li
[ Upstream commit 38eecbe086a4e52f54b2bbda8feba65d44addbef ]
[WHY]
Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an
atomic context.
We shouldn't access registers through KIQ since "msleep()" may be called in
"amdgpu_kiq_rreg()".
[HOW]
Move functi
From: Wesley Chalmers
[ Upstream commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be ]
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This
From: Hersen Wu
[ Upstream commit 025ce392b5f213696ca0af3e07735d0fae020694 ]
[Why]
when amdgpu_dm_update_connector_after_detect is called
two times successively with valid sink, memory allocated of
aconnector->timing_requested for the first call is not free.
this causes memeleak.
[How]
allocate
From: lyndonli
[ Upstream commit 4eea7fb980dc44545a32eec92e2662053b34cd9d ]
Below call trace and errors are observed when reloading
amdgpu driver with the module parameter reset_method=3.
It should do a default reset when loading or reloading the
driver, regardless of the module parameter reset
From: Chong Li
[ Upstream commit 38eecbe086a4e52f54b2bbda8feba65d44addbef ]
[WHY]
Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an
atomic context.
We shouldn't access registers through KIQ since "msleep()" may be called in
"amdgpu_kiq_rreg()".
[HOW]
Move functi
From: Wesley Chalmers
[ Upstream commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be ]
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This
From: lyndonli
[ Upstream commit 4eea7fb980dc44545a32eec92e2662053b34cd9d ]
Below call trace and errors are observed when reloading
amdgpu driver with the module parameter reset_method=3.
It should do a default reset when loading or reloading the
driver, regardless of the module parameter reset
From: Chong Li
[ Upstream commit 38eecbe086a4e52f54b2bbda8feba65d44addbef ]
[WHY]
Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an
atomic context.
We shouldn't access registers through KIQ since "msleep()" may be called in
"amdgpu_kiq_rreg()".
[HOW]
Move functi
From: Wesley Chalmers
[ Upstream commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be ]
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This
From: lyndonli
[ Upstream commit 4eea7fb980dc44545a32eec92e2662053b34cd9d ]
Below call trace and errors are observed when reloading
amdgpu driver with the module parameter reset_method=3.
It should do a default reset when loading or reloading the
driver, regardless of the module parameter reset
From: Chong Li
[ Upstream commit 38eecbe086a4e52f54b2bbda8feba65d44addbef ]
[WHY]
Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an
atomic context.
We shouldn't access registers through KIQ since "msleep()" may be called in
"amdgpu_kiq_rreg()".
[HOW]
Move functi
From: lyndonli
[ Upstream commit 4eea7fb980dc44545a32eec92e2662053b34cd9d ]
Below call trace and errors are observed when reloading
amdgpu driver with the module parameter reset_method=3.
It should do a default reset when loading or reloading the
driver, regardless of the module parameter reset
Hey,
On 2023-05-11 12:14, Tvrtko Ursulin wrote:
>
> On 10/05/2023 19:46, Tejun Heo wrote:
>> Hello,
>>
>> On Wed, May 10, 2023 at 04:59:01PM +0200, Maarten Lankhorst wrote:
>>> The misc controller is not granular enough. A single computer may have any
>>> number of
>>> graphics cards, some of the
On 2023-05-11 07:23, Daniil Dulov wrote:
Pointer mqd_mem_obj can be deallocated in kfd_gtt_sa_allocate().
The function then returns non-zero value, which causes the second deallocation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: d1f8f0d17d40 ("drm/amdkfd: Move non-
On Tue, May 9, 2023 at 7:01 PM Guilherme G. Piccoli wrote:
>
> On 09/05/2023 13:49, Bas Nieuwenhuizen wrote:
> > From: "Guilherme G. Piccoli"
> >
> > (Bas: speculative change to mirror gfx10/gfx9)
> >
> > Signed-off-by: Guilherme G. Piccoli
> > Cc: Alex Deucher
> > ---
>
> Thanks a lot for both
[AMD Official Use Only - General]
drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to
revision id.
Due to the raven2 and raven/picasso maybe have the same GC_HWIP version.
So differentiate them by revision id.
Signed-off-by: shanshengwang
mailto:shansheng.
Hi,
Initially noticed this in some games, which seem to be a bit lazy
with their VRAM allocations + freeing, that performance would drop
dramatically / become unusable once the VRAM is full and GTT gets
used. For instance in No Man's Sky after jumping a solar system
or on DCS World on several maps
PMFW may boots the ASIC with a different power mode from the system's
real one. Notify PMFW explicitly the power mode the system in. This
is needed only when ACDC switch via gpio is not supported.
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18 +
[AMD Official Use Only - General]
Reviewed-by: Kenneth Feng
-Original Message-
From: Quan, Evan
Sent: Friday, May 12, 2023 11:18 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth
; Quan, Evan
Subject: [PATCH] drm/amd/pm: fix possible power mode mismatch betw
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