Currently, amdgpu will always set up the brightness at 100% when it
loads. However this is jarring when the BIOS has it previously
programmed to a much lower value.
The ACPI ATIF method includes two members for "ac_level" and "dc_level".
These represent the default values that should be used if t
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Tao Zhou
Sent: Thursday, June 6, 2024 18:06
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao
Subject: [PATCH 2/2] drm/amd/pm: up
From: Aric Cyr
* FW Release 0.0.221.0
* Fixed missing targets in FAMS2
* Populate hardware_release hook for dcn401
* Disable DMCUB timeout for DCN35
* Move PRIMARY plane zpos higher
* Introduce overlay cursor mode
* Change dram_clock_latency for dcn35 and dcn351
* DCN401 cursor code update
Acked
From: Alex Hung
[WHAT & HOW]
dmub_rb_cmd's ramping_boundary has size of uint8_t and it is assigned
0x. Fix it by changing it to uint8_t with value of 0xFF.
This fixes 2 INTEGER_OVERFLOW issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Zaeem Mohamed
Signed-off-by: Alex
From: Dillon Varone
[WHY&HOW]
Add additional delay factor when considering a safe time to flip for HWFQ
to be passed in by the driver.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c| 1 +
drivers/gpu/drm/amd/di
From: Anthony Koo
- Create a general command and fix Replay desync error with general cmd
Acked-by: Zaeem Mohamed
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
From: Dillon Varone
[WHY&HOW]
SubVP is not supported when hardware rotation is in use.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
.../display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
From: Daniel Miess
[Why]
PHYSYMCLK RCO has been found to lead to crashes in some
corner cases
[How]
Disable PHYSYMCLK RCO debug bit
Reviewed-by: Nicholas Kazlauskas
Acked-by: Zaeem Mohamed
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
From: Dillon Varone
[WHY&HOW]
Update the idle hardmin with SMU if either clock changed.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
From: Alvin Lee
[Description]
hardare_release() is called when driver is removed. Add the missing hook for
DCN401
Reviewed-by: Dillon Varone
Acked-by: Zaeem Mohamed
Signed-off-by: Alvin Lee
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 20 +++
.../amd/display/dc/hwss/d
From: Alex Hung
[WHY & HOW]
v_total is an uint32_t and subtracting an unsigned to a signed will
result in an unsigned which is always >= 0. As a result, the ternary
conditions are always true and thus has no effect.
This is fixed by casting v_total to signed explicitly. This also
avoids v_total
From: Dillon Varone
[WHY&HOW]
Reinit should return after completing version 2.1 reinit instead of calling
version 2 reinit after.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 3 ++-
1 file changed, 2 inse
From: Dillon Varone
[WHY&HOW]
Sometimes this function is called with a partially deconstructed phantom
stream toplolgy, and should ignore phantoms with no plane state.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/dml2/dml21/dml21_
From: Alex Hung
[WHAT & HOW]
The self-assignments have no effects and thus are removed.
Reviewed-by: Rodrigo Siqueira
Acked-by: Zaeem Mohamed
Signed-off-by: Alex Hung
---
.../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c| 4
.../display/dc/dml2/dml21/src/dml2_core/dml2_core
From: Ivan Lipski
[WHY]
Coverity analysis of the Upstream display driver code
(amd-staging-drm-next) flagged these three functions as
containing 'CONSTANT_EXPRESSION_RESULT' errors, i. e. the
conditionals are reduntant since their result is predetermined.
fixpt31_32.c:
The two flagged 'ASSERT' l
From: Sung-huai Wang
[How&Why]
This reverts commit a410234a0e13. Due to the it effects Replay resync.
Reviewed-by: Wenjing Liu
Acked-by: Zaeem Mohamed
Signed-off-by: Sung-huai Wang
---
.../dc/link/protocols/link_dp_irq_handler.c | 24 +++
1 file changed, 9 insertions(+), 15
From: Wenjing Liu
[why]
In YCbCr422 format hardware shares 1 set of chromas CbCr with 2 sets of
lumas Y. Therefore each ODM segment needs to be two pixel aligned. The
commit adds this missing hardwware requirement into ODM segment width
decision logic.
Reviewed-by: Dillon Varone
Acked-by: Zaeem
From: "JinZe.Xu"
[Why&How]
Add flag to disable IPS when it is not allowed.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Zaeem Mohamed
Signed-off-by: JinZe.Xu
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 ++
2 files changed, 3 insertio
From: Alex Hung
[WHY & HOW]
The comparisons of unsigned int with 0 can have no meanings, i.e.
unsigned int >= 0 (always true) or unsigned int < 0 (always false), and
therefore they are removed.
This fixes 12 NO_EFFECT issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Zaeem Moh
From: Alex Hung
This fixes an UNINIT issue reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Zaeem Mohamed
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/
From: Alex Hung
[WHY]
fe_clk_en and be_clk_sel have size of 4 but sizeof(fe_clk_en) has
byte size 16 which is lager than the array size.
[HOW]
Use ARRAY_SIZE for calculating size.
This fixes 2 OVERRUN issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Zaeem Mohamed
Signed-off
From: Sridevi Arvindekar
Move pipe_ctx variables to start of the function and add a helpful comment
Co-authored-by: Sridevi Arvindekar
Reviewed-by: Ilya Bakoulin
Acked-by: Zaeem Mohamed
Signed-off-by: Sridevi Arvindekar
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 5 +
From: Nicholas Kazlauskas
[Why]
DMCUB can intermittently take longer than expected to process commands.
Old ASIC policy was to continue while logging a diagnostic error - which
works fine for ASIC without IPS, but with IPS this could lead to a race
condition where we attempt to access DCN state
From: Rodrigo Siqueira
Coverity highlighted that the parameter otg_master is referenced before
the if condition that validates it, which means that the code might have
some attempt to access a null pointer. This commit addresses this issue
by moving the pointer verification to the beginning of th
From: Wenjing Liu
[why]
We set preferred link settings for virtual signal. However we don't support
virtual signal for UHBR link rate. If preferred is set to UHBR link rate, we
will allow virtual signal with UHBR link rate which causes system crashes.
Reviewed-by: Dillon Varone
Acked-by: Zaeem
From: Wenjing Liu
[why]
DML1 validation code doesn't have the ability to remove ODM combine.
It will directly translate currently used ODM combine config into ODM
override. If ODM combine is used in the initial state it will only
validate the timing if ODM is used. This is not correct for dynamic
From: Leo Li
[Why]
Compositors have different ways of assigning surfaces to DRM planes for
render offloading. It may decide between various strategies: overlay,
underlay, or a mix of both (see here for more info:
https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76)
One way for compos
From: Wayne Lin
[Why]
dm_dp_mst_is_port_support_mode() is a bit not following the original design
rule and cause
light up issue with multiple 4k monitors after mst dsc hub.
[How]
Refactor function dm_dp_mst_is_port_support_mode() a bit to solve the light up
issue.
Reviewed-by: Jerry Zuo
Acke
From: Wenjing Liu
[why]
There are cases where update pipe params could fail but dpp pipes are already
added to the state. In this case, we should remove dpp pipes so dc state is
restored back. If it is not restored, dc state is corrupted after calling this
function, so if we call the same interfa
From: Josip Pavic
[Why & How]
Define debug interface to dmub for reading back abm data.
Reviewed-by: Anthony Koo
Acked-by: Zaeem Mohamed
Signed-off-by: Josip Pavic
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 60 +++
1 file changed, 60 insertions(+)
diff --git a/drive
From: Chris Park
[Why]
Reference clock, either DPREFCLK or DTBCLK can be a value of 0
which then will encounter division by 0.
[How]
Avoid further calculation and programming if refclk is not
populated.
Reviewed-by: Dillon Varone
Acked-by: Zaeem Mohamed
Signed-off-by: Chris Park
---
drivers
From: Leo Li
[Why]
DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to the
other (output encoder).
Each DCN pipe has the ability to blend in a cursor early on in the
pipeline. In other words, there are no dedicate
From: Nicholas Kazlauskas
[Why]
These registers should not be read from driver and triggering the
security violation when DMCUB work times out and diagnostics are
collected blocks Z8 entry.
[How]
Remove the register read from DCN35.
Reviewed-by: Duncan Ma
Acked-by: Zaeem Mohamed
Signed-off-by
From: Paul Hsieh
[Why & How]
Current DRAM setting would cause underflow on customer platform.
Modify dram_clock_change_latency_us from 11.72 to 34.0 us as per recommendation
from HW team
Reviewed-by: Nicholas Kazlauskas
Acked-by: Zaeem Mohamed
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/a
From: Wayne Lin
[Why]
When unplug one of monitors connected after mst hub, encounter null pointer
dereference.
It's due to dc_sink get released immediately in early_unregister() or
detect_ctx(). When
commit new state which directly referring to info stored in dc_sink will cause
null pointer
d
From: Fangzhi Zuo
Fixing 4k240 underflow on dcn351
Reviewed-by: Harry Wentland
Acked-by: Zaeem Mohamed
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_tra
From: Daniel Miess
[Why]
Intermittent underflow observed when using 4k144 display on
dcn351
[How]
Update dram_clock_change_latency_us from 11.72us to 34us
Reviewed-by: Nicholas Kazlauskas
Acked-by: Zaeem Mohamed
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn35
From: Wayne Lin
[Why & How]
Debug msg for usb4/tbt now is a bit confusing. Adjust it for better reading.
Reviewed-by: Jerry Zuo
Acked-by: Zaeem Mohamed
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 57 +++
1 file changed, 34 insertions(+), 23 de
From: Wayne Lin
[Why & How]
It actually exposes '6' types in enum dmub_notification_type. Not 5. Using
smaller
number to create array dmub_callback & dmub_thread_offload has potential to
access
item out of array bound. Fix it.
Reviewed-by: Jerry Zuo
Acked-by: Zaeem Mohamed
Signed-off-by: Way
From: Joshua Aberback
[Why]
DCN401 currently has an issue re-enabling when pipe splitting is enabled,
while the root cause is being investigated we can make sure everything is
being reset as a workaround, by disabling boot optimization.
[How]
- use enable_accelerated_mode instead of init_pipes
From: Wayne Lin
[Why & How]
Link hpd status is set during link detection process via
dpia_query_hpd_status(),
doesn't need to explicitly set it during outbox irq. Remove it.
Reviewed-by: Jerry Zuo
Acked-by: Zaeem Mohamed
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amd
From: Chris Park
[Why]
uint32_t is implicitly converted to uint64_t while multiplication
still happens on uint32_t side. This creates digit overflow
for large pixel clock which is meant to be retained in uint64_t.
[How]
Calculate multiplication of units in uint64_t domain instead of
uint32_t in
From: Ivan Lipski
[WHY]
The coverity analysis flagged this if expression as it contains a
'CONSTANT_EXPRESSION_RESULT': 'update_idle_uclk' is 'ORd' with itself.
[HOW]
Remove the duplicate 'update_idle_uclk'.
Reviewed-by: Alex Hung
Acked-by: Zaeem Mohamed
Signed-off-by: Ivan Lipski
---
drive
From: Sridevi Arvindekar
Scaling androtation changes for cursor.
Reviewed-by: Ariel Bernstein
Reviewed-by: Nevenko Stupar
Acked-by: Zaeem Mohamed
Signed-off-by: Sridevi Arvindekar
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 22 +--
1 file changed, 5 insertions(+), 17
From: George Shen
[Why]
Passive DP40 cables were updated in the latest DP spec to support
UHBR13.5 link rate. Current max link rate logic checks against the
cable ID DPCD even for passive cables.
[How]
Ignore UHBR13.5 cable ID DPCD cap in get_max_link_rate logic.
Reviewed-by: Wenjing Liu
Acked
On 2024-06-05 05:14, Christian König wrote:
Am 04.06.24 um 20:08 schrieb Felix Kuehling:
On 2024-06-03 22:13, Al Viro wrote:
Using drm_gem_prime_handle_to_fd() to set dmabuf up and insert it into
descriptor table, only to have it looked up by file descriptor and
remove it from descriptor tab
From: Roman Li
[Why]
replay_capability debugfs tells whether sink and driver support
replay feature. However replay enablement also depends on
whether it is enabled/disabled via amdgpu module params.
[How]
Add 'Config support' entry to output current replay config.
Reviewed-by: ChiaHsuan Chung
From: Rodrigo Siqueira
Use the SPDX format for dmub_replay.c|.h files.
Reviewed-by: Aurabindo Pillai
Acked-by: Zaeem Mohamed
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dce/dmub_replay.c | 27 ++---
.../gpu/drm/amd/display/dc/dce/dmub_replay.h | 29 +++---
From: winstang
[Why]
prevent invalid memory access
[How]
check if dc and stream are NULL
Co-authored-by: winstang
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: winstang
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
1 file changed, 3 insertions(+)
diff --gi
From: Alvin Lee
[Description]
Phantom DTBCLK can be calculated different from main because phantom
has no DSC and thus will have a different output BPP. Ignore phantom
DTBCLK requirement and only consider non-phantom DTBCLK requirements.
Reviewed-by: Dillon Varone
Acked-by: Zaeem Mohamed
Signe
From: Nicholas Kazlauskas
[Why]
Adds support for performing the sequential ONO changes from DCN351
into DCN35 ASIC based on revision.
[How]
Check the revision and run the DCN351 sequences on applicable revisions.
Reviewed-by: Sung joon Kim
Acked-by: Zaeem Mohamed
Signed-off-by: Nicholas Kazla
From: Anthony Koo
- Change ordering of structs to put enums together
- Add new define DMUB_TRACE_ENTRY_DEFINED to guard
the trace code enum
Acked-by: Zaeem Mohamed
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 26 ++-
1 file changed, 14 in
From: Michael Strauss
[WHY]
Some sinks are observed to return invalid LTTPR revision and/or invalid
LTTPR link rate capabilities.
[HOW]
Assume any LTTPR which reports invalid max link rate supports HBR3.
Don't validate LTTPR DPCD revision in dp_is_lttpr_present check.
Reviewed-by: George Shen
From: Nevenko Stupar
[Why & How]
Remove some cursor offset calculations for rotated cursor for fixing a bug
where multiple cursors are seen.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Nevenko Stupar
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 25 --
From: Michael Strauss
[WHY]
Needed for PHY patterns as well to perform electrical compliance.
Also need to increase wait time from 30ms to 50ms to resolve very
intermittent UHBR20 link training failures.
Reviewed-by: Wenjing Liu
Acked-by: Zaeem Mohamed
Signed-off-by: Michael Strauss
---
.../
From: Wenjing Liu
[why]
We need to decrease ODM slice when adding or removing planes because MPO
support takes precedence over dynamic ODM combine. However there is a case where
we remove ODM combine even for ODM combine required timing in the initial new
dc state. This is normally okay because O
From: Chris Park
[Why]
Official Release CTA specification reverted the change and
no longer uses version 5 to indicate OVT timing.
[How]
Change the version used for AVI info Frame for OVT to 4.
Reviewed-by: Leo Ma
Acked-by: Zaeem Mohamed
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/dis
From: Daniel Sa
why:
DML21 being overwritten after init.
how:
After initializing, early return.
Reviewed-by: Dillon Varone
Acked-by: Zaeem Mohamed
Signed-off-by: Daniel Sa
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/
From: pochchan
For some specific panel, it need to use TPS3 rather than use TP2 in ALPM
when DSC is enabled.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: pochchan
---
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/dr
[WHY]
Duplicate headers requiring unecessary maintenance of both headers
[HOW]
Removal of smu13_driver_if header and all referneces to it changed to
dcn32_smu13_driver
Signed-off-by: Zaeem Mohamed
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn32/dcn32_clk_mgr_sm
From: Wenjing Liu
[why]
When optc uses two pixel per container, each ODM slice width must be an
even number.
[how]
If ODM slice width is odd number increase it by 1.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 3 +++
driver
From: Alvin Lee
[Description]
No need to assign stream_status NULL because it is always
re-assigned before usage. This change is to fix coverity
errors.
Reviewed-by: Nicholas Choi
Acked-by: Zaeem Mohamed
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 --
1 file
From: Ivan Lipski
[WHY]
Coverity analysis flagged the two if conditions in
dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they
are never true, since the variable
'program_prealpha_dealpha' is initialized at 0 and
never chagnes.
[HOW]
Removed the variable 'program_prealpha_dealpha' and
the if con
From: Ivan Lipski
[WHY]
Coverity analysis flagged this ternary operation as
DEADCODE.
Since 'total_y_free_entry' is initialized as 0x200 and
'total_c_free_entry' is initialized as 0x140, and they
never change values before the ternary operator, so
'total_y_free_entry' is always greater 'total_c_
From: Dennis Chan
When PHY power off, the DP_SEC_CNTL cannot be configured and cause
disable Adaptive sync SDP failed. Regarding the issue, the driver will
disabled AS-SDP in replay state machine.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dennis Chan
---
drivers/gpu/drm/amd/display/dc/dce/
From: Ivan Lipski
[WHY]
Coverity analysis flagged this code as DEADCODE
since the condition and return in the outer loop
are never reached.
All operations with the 'dwb_pipe' variable happen
in the inner loop, that already contains the same
check with the 'MAX_DWB_PIPES'. The later
check conditi
This DC patchset brings improvements in multiple areas. In summary, we have:
* FW Release 0.0.221.0
* Fixed missing targets in FAMS2
* Populate hardware_release hook for dcn401
* Disable DMCUB timeout for DCN35
* Move PRIMARY plane zpos higher
* Introduce overlay cursor mode
* Change dram_clock_la
From: Wenjing Liu
[why]
OPP input rect aka odm slice rect is a hardware dependent parameter that
can't be determined by SPL software logic. Therefore we need to
explicitly pass odm slice rect in. So ODM slice rect calculation is
moved out of SPL.
[how]
add odm_slice_rect parameter in spl_in
Rev
From: ChunTao Tso
[Why]
Because ABM will wait VStart to start getting histogram data, it will
cause we can't enter IPS while full screnn video playing.
[How]
Modify the panel refresh rate to the maximun multiple of current refresh
rate
Reviewed-by: Rodrigo Siqueira
Signed-off-by: ChunTao Tso
From: ChunTao Tso
[Why]
The original coasting vtotal is 2 bytes, and it need to be amended to 4
bytes because low hz case.
[How]
Amend coasting vtotal from 2 bytes to 4 bytes.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: ChunTao Tso
---
.../gpu/drm/amd/display/dc/dce/dmub_replay.c | 34
From: Leon Huang
[Why]
Dmub provides several Replay residency calculation methods, but current
interface only supports either ALPM or PHY mode
[How]
Modify the interface for supporting different types of Replay residency
calculation.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Leon Huang
---
[AMD Official Use Only - AMD Internal Distribution Only]
IGNORE
-Original Message-
From: Mohamed, Zaeem
Sent: Thursday, June 6, 2024 4:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Li, Sun peng (Leo)
; Siqueira, Rodrigo ; Pillai,
Aurabindo ; Li, Roman ; Lin, Wayne
; Gu
On 2024-06-06 04:47, Christian König wrote:
This was only used as workaround for recovering the page tables after
VRAM was lost and is no longer necessary after the function
amdgpu_vm_bo_reset_state_machine() started to do the same.
Compute never used shadows either, so the only proplematic case
From: winstang
[Why]
prevent invalid memory access
[How]
check if dc and stream are NULL
Co-authored-by: winstang
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: winstang
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
1 file changed, 3 insertions(+)
diff --gi
From: Nicholas Kazlauskas
[Why]
Adds support for performing the sequential ONO changes from DCN351
into DCN35 ASIC based on revision.
[How]
Check the revision and run the DCN351 sequences on applicable revisions.
Reviewed-by: Sung joon Kim
Acked-by: Zaeem Mohamed
Signed-off-by: Nicholas Kazla
From: Anthony Koo
- Change ordering of structs to put enums together
- Add new define DMUB_TRACE_ENTRY_DEFINED to guard
the trace code enum
Acked-by: Zaeem Mohamed
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 26 ++-
1 file changed, 14 in
From: Michael Strauss
[WHY]
Some sinks are observed to return invalid LTTPR revision and/or invalid
LTTPR link rate capabilities.
[HOW]
Assume any LTTPR which reports invalid max link rate supports HBR3.
Don't validate LTTPR DPCD revision in dp_is_lttpr_present check.
Reviewed-by: George Shen
From: Alvin Lee
[Description]
Phantom DTBCLK can be calculated different from main because phantom
has no DSC and thus will have a different output BPP. Ignore phantom
DTBCLK requirement and only consider non-phantom DTBCLK requirements.
Reviewed-by: Dillon Varone
Acked-by: Zaeem Mohamed
Signe
From: Michael Strauss
[WHY]
Needed for PHY patterns as well to perform electrical compliance.
Also need to increase wait time from 30ms to 50ms to resolve very
intermittent UHBR20 link training failures.
Reviewed-by: Wenjing Liu
Acked-by: Zaeem Mohamed
Signed-off-by: Michael Strauss
---
.../
From: Wenjing Liu
[why]
We need to decrease ODM slice when adding or removing planes because MPO
support takes precedence over dynamic ODM combine. However there is a case where
we remove ODM combine even for ODM combine required timing in the initial new
dc state. This is normally okay because O
From: Daniel Sa
why:
DML21 being overwritten after init.
how:
After initializing, early return.
Reviewed-by: Dillon Varone
Acked-by: Zaeem Mohamed
Signed-off-by: Daniel Sa
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/
From: Nevenko Stupar
[Why & How]
Remove some cursor offset calculations for rotated cursor for fixing a bug
where multiple cursors are seen.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Nevenko Stupar
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 25 --
[WHY]
Duplicate headers requiring unecessary maintenance of both headers
[HOW]
Removal of smu13_driver_if header and all referneces to it changed to
dcn32_smu13_driver
Signed-off-by: Zaeem Mohamed
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn32/dcn32_clk_mgr_sm
From: Chris Park
[Why]
Official Release CTA specification reverted the change and
no longer uses version 5 to indicate OVT timing.
[How]
Change the version used for AVI info Frame for OVT to 4.
Reviewed-by: Leo Ma
Acked-by: Zaeem Mohamed
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/dis
From: Ivan Lipski
[WHY]
Coverity analysis flagged this code as DEADCODE
since the condition and return in the outer loop
are never reached.
All operations with the 'dwb_pipe' variable happen
in the inner loop, that already contains the same
check with the 'MAX_DWB_PIPES'. The later
check conditi
From: Alvin Lee
[Description]
No need to assign stream_status NULL because it is always
re-assigned before usage. This change is to fix coverity
errors.
Reviewed-by: Nicholas Choi
Acked-by: Zaeem Mohamed
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 --
1 file
From: Wenjing Liu
[why]
OPP input rect aka odm slice rect is a hardware dependent parameter that
can't be determined by SPL software logic. Therefore we need to
explicitly pass odm slice rect in. So ODM slice rect calculation is
moved out of SPL.
[how]
add odm_slice_rect parameter in spl_in
Rev
From: Ivan Lipski
[WHY]
Coverity analysis flagged this ternary operation as
DEADCODE.
Since 'total_y_free_entry' is initialized as 0x200 and
'total_c_free_entry' is initialized as 0x140, and they
never change values before the ternary operator, so
'total_y_free_entry' is always greater 'total_c_
From: Dennis Chan
When PHY power off, the DP_SEC_CNTL cannot be configured and cause
disable Adaptive sync SDP failed. Regarding the issue, the driver will
disabled AS-SDP in replay state machine.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dennis Chan
---
drivers/gpu/drm/amd/display/dc/dce/
From: Ivan Lipski
[WHY]
Coverity analysis flagged the two if conditions in
dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they
are never true, since the variable
'program_prealpha_dealpha' is initialized at 0 and
never chagnes.
[HOW]
Removed the variable 'program_prealpha_dealpha' and
the if con
From: ChunTao Tso
[Why]
The original coasting vtotal is 2 bytes, and it need to be amended to 4
bytes because low hz case.
[How]
Amend coasting vtotal from 2 bytes to 4 bytes.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: ChunTao Tso
---
.../gpu/drm/amd/display/dc/dce/dmub_replay.c | 34
From: Wenjing Liu
[why]
When optc uses two pixel per container, each ODM slice width must be an
even number.
[how]
If ODM slice width is odd number increase it by 1.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 3 +++
driver
From: ChunTao Tso
[Why]
Because ABM will wait VStart to start getting histogram data, it will
cause we can't enter IPS while full screnn video playing.
[How]
Modify the panel refresh rate to the maximun multiple of current refresh
rate
Reviewed-by: Rodrigo Siqueira
Signed-off-by: ChunTao Tso
This DC ptchset brings improvements in multiple areas. In summary, we have:
* FW Release 0.0.221.0
* Fixed missing targets in FAMS2
* Populate hardware_release hook for dcn401
* Disable DMCUB timeout for DCN35
* Move PRIMARY plane zpos higher
* Introduce overlay cursor mode
* Change dram_clock_lat
From: Leon Huang
[Why]
Dmub provides several Replay residency calculation methods, but current
interface only supports either ALPM or PHY mode
[How]
Modify the interface for supporting different types of Replay residency
calculation.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Leon Huang
---
From: pochchan
For some specific panel, it need to use TPS3 rather than use TP2 in ALPM
when DSC is enabled.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: pochchan
---
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/dr
Tested-by: Richard Gong
On 6/6/2024 3:04 PM, Arunpravin Paneer Selvam wrote:
This happens when the amdgpu_bo_release_notify running
before amdgpu_ttm_set_buffer_funcs_status set the buffer
funcs to enabled.
check the buffer funcs enablement before calling the fill
buffer memory.
v2:(Christi
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Limonciello, Mario
> Sent: Thursday, June 6, 2024 10:56 AM
> To: Deucher, Alexander
> Cc: syzbot ;
> Huang, Tim ; Pan, Xinhui ;
> airl...@gmail.com; a...@linux-foundation.org; Deucher, Alexander
> ; amd
On 6/6/2024 15:04, Arunpravin Paneer Selvam wrote:
This happens when the amdgpu_bo_release_notify running
before amdgpu_ttm_set_buffer_funcs_status set the buffer
funcs to enabled.
check the buffer funcs enablement before calling the fill
buffer memory.
v2:(Christian)
- Apply it only for GEM
This happens when the amdgpu_bo_release_notify running
before amdgpu_ttm_set_buffer_funcs_status set the buffer
funcs to enabled.
check the buffer funcs enablement before calling the fill
buffer memory.
v2:(Christian)
- Apply it only for GEM buffers and since GEM buffers are only
allocated/
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