From: Jiadong Zhu
The job's embedded fence is dma_fence which shall not be conversed
to amdgpu_fence. The start timestamp shall be saved on job for
hw_fence.
v2: optimize get_fence_start_time.
v3: set start time only when mcbp enabled.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu
--
发件人：Felix Kuehling
发送时间：2024年7月11日(星期四) 07:47
收件人：周春明(日月) ; Tvrtko Ursulin ;
dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org ; Dave Airlie
; Daniel Vetter ; criu
抄 送："Errabolu, Ramesh" ; "Christian König"
; 张伦强
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, July 10, 2024 9:48 PM
> To: Ma, Li
> Cc: amd-gfx@lists.freedesktop.org; Huang, Tim ;
> Deucher, Alexander ; Zhang, Yifan
>
> Subject: Re: [PATCH] drm/amd/swsmu: enable Pstate
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Christian König
> Sent: Wednesday, July 10, 2024 8:46 PM
> To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org;
> Deucher, Alexander
> Subject: Re: [PATCH v2] drm/amdgpu: set start timestamp of fence in th
On 2024-07-09 22:38, 周春明(日月) wrote:
--
发件人：Felix Kuehling
发送时间：2024年7月10日(星期三) 01:07
收件人：周春明(日月) ; Tvrtko Ursulin
; dri-de...@lists.freedesktop.org
; amd-gfx@lists.freedesktop.org
; Dave Airlie ;
Daniel Vetter ; criu
抄 送：
On 7/10/24 04:43, Daniel Vetter wrote:
On Tue, Jul 09, 2024 at 10:02:08AM -0400, Hamza Mahfooz wrote:
On 7/9/24 06:09, Daniel Vetter wrote:
On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
Hook up drm_crtc_set_vblank
On 7/3/24 01:17, Mario Limonciello wrote:
During the Display Next hackfest 2024 one of the topics discussed
was the need for compositor to be able to relay intention to drivers
that color fidelity is preferred over power savings.
To accomplish this a new optional DRM property is being introduced
From: Boyuan Zhang
For unified queue, DPG pause for encoding is done inside VCN firmware,
so there is no need to pause dpg based on ring type in kernel.
For VCN3 and below, pausing DPG for encoding in kernel is still needed.
v2: add more comments
v3: update commit message
Signed-off-by: Boyuan
From: Boyuan Zhang
Determine whether VCN using unified queue in sw_init, instead of calling
functions later on.
v2: fix coding style
Signed-off-by: Boyuan Zhang
Acked-by: Alex Deucher
Reviewed-by: Ruijing Dong
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 39 ++---
drive
On 2024-07-03 01:17, Mario Limonciello wrote:
When the `power_saving_policy` property is set to bit mask
"Require color accuracy" ABM should be disabled immediately and
any requests by sysfs to update will return an -EBUSY error.
When the `power_saving_policy` property is set to bit mask
"Req
[AMD Official Use Only - AMD Internal Distribution Only]
Just change the commit messages from "For previous generations" to " For VCN3
and before" to be more specific.
With that all patches are
Reviewed-by: Ruijing Dong
Thanks,
Ruijing
-Original Message-
From: amd-gfx On Behalf Of
b
From: Boyuan Zhang
Determine whether VCN using unified queue in sw_init, instead of calling
functions later on.
v2: fix coding style
Signed-off-by: Boyuan Zhang
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 39 ++---
drivers/gpu/drm/amd/amdgpu/amdgp
From: Boyuan Zhang
For unified queue, DPG pause for encoding is done inside VCN firmware,
so there is no need to pause dpg based on ring type in kernel.
For previous generations, pausing DPG for encoding in kernel is still needed.
v2: add more comments
Signed-off-by: Boyuan Zhang
Acked-by: Al
On 02/07/2024 18:57, Jim Cromie wrote:
Several tests are dependent upon config choices. Lets avoid failing
where that is noise.
The KCONFIG_CONFIG var exists to convey the config-file around. If
the var names a file, read it and extract the relevant CONFIG items,
and use them to skip the dep
On 7/10/24 4:12 PM, Marek Olšák wrote:
Can you also increase KMS_DRIVER_MINOR with a proper comment in
amdgpu_drv.c, which will be used by Mesa to tell whether display DCC
is supported on gfx12?
Sure, will do.
--
Thanks & Regards,
Aurabindo Pillai
Can you also increase KMS_DRIVER_MINOR with a proper comment in
amdgpu_drv.c, which will be used by Mesa to tell whether display DCC
is supported on gfx12?
Thanks,
Marek
On Wed, Jul 10, 2024 at 4:05 PM Aurabindo Pillai
wrote:
>
>
>
> On 7/10/24 10:49 AM, Marek Olšák wrote:
> > This will enable d
On 7/10/24 10:49 AM, Marek Olšák wrote:
This will enable display DCC for Wayland because Mesa already exposes
modifiers with DCC. Has it been tested?
Yes, its working for most resolutions. Investigating issue with certain
modes.
Marek
--
Thanks & Regards,
Aurabindo Pillai
On 2024-07-10 15:36, Fangzhi Zuo wrote:
From: Tom Chung
[Why & How]
Fixed the replay issues and now re-enable the panel replay feature.
Reported-by: Arthur Borsboom
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3344
Reviewed-by: Mario Limonciello
Reviewed-by: Rodrigo Siqueira
From: Aric Cyr
* FW Release 0.0.225.0
* DML2 fixes
* Re-enable panel replay feature
* Allow display DCC for DCN401
* Refactor DWB, OPP, MPC, MMHUBBUB
* Fix dscclk Programming issue on DCN401
Acked-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/d
From: Aurabindo Pillai
Use an extra for loop to reduce duplicate code for adding modifiers
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 36 +--
1 file changed, 17 insertions(+), 19 d
From: Rodrigo Siqueira
Acked-by: Jerry Zuo
Signed-off-by: Rodrigo Siqueira
---
.../dml2/dml21/src/dml2_core/dml2_core_dcn4.c | 78 ---
1 file changed, 78 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
b/drivers/gpu/drm/amd/
From: Aurabindo Pillai
To enable mesa to use display dcc, DM should expose them in the
supported modifiers. Add the best (most efficient) modifiers first.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c
From: Joshua Aberback
[Why]
In some cases during topology changes, a pipe that was used to drive a
stream being removed can be re-assigned to drive a different stream. In
these cases, DSC power gating is not handled properly, leading to
situations where DSC is being setup while power gated.
[How
From: Aurabindo Pillai
fix a memleak introduced by not removing the buffer object for use with
early dmub bounding box value storage
Fixes: 25a40071e ("drm/amd/display: Enable copying of bounding box data from
VBIOS DMUB")
Reviewed-by: Rodrigo Siqueira
Reviewed-by: Alex Hung
Signed-off-by: J
From: Daniel Sa
why:
When the cursor disappears/reappears on fullscreen video, there is a
short transitional period where the cursor's color matrix is using the
same format as the video plane. This sets the cursor to the wrong color
momentarily before the UI plane appears, correcting the color.
From: Duncan Ma
[Why]
Visual Confirm would tell us if it ever
entered idle state.
[How]
Add debug option for IPS visual confirm
Reviewed-by: Ovidiu Bunea
Signed-off-by: Jerry Zuo
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display
From: Sung Joon Kim
[why & how]
We calculate static screen wait frames based
on the current timing info in the active stream.
If stream is not initialized, then we should skip
the calculation and go with the default values.
Reviewed-by: Gabe Teeger
Signed-off-by: Jerry Zuo
Signed-off-by: Sung
From: Fudongwang
[Why & How]
For DCN harvest case, if there is no dmcub support, we should return false
to avoid bugcheck later.
Reviewed-by: Aric Cyr
Signed-off-by: Jerry Zuo
Signed-off-by: Fudongwang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
1 file changed, 3 insertions(+)
dif
From: Dillon Varone
[WHY&HOW]
Some global configuration options were previously hardcoded in DC, now they are
exported by DML and sent to FW.
Reviewed-by: Martin Leung
Signed-off-by: Jerry Zuo
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/core/dc_state.c| 4 +-
drivers/gp
From: Mudimela
[Why]
To refactor DWB related files from dcn30 Files
[How]
Moved DWB related files from dcn30 to specific DWB folder and
updated Makefiles to fix Compilation.
Reviewed-by: Martin Leung
Signed-off-by: Jerry Zuo
Signed-off-by: Mudimela
---
drivers/gpu/drm/amd/display/dc/dcn30/M
From: Alex Hung
[WHY]
dml2_core_shared_mode_support and dml_core_mode_support access the third
element of dummy_boolean, i.e. hw_debug5 = &s->dummy_boolean[2], when
dummy_boolean has size of 2. Any assignment to hw_debug5 causes an
OVERRUN.
[HOW]
Increase dummy_boolean's array size to 3.
This f
From: Alex Hung
[WHAT & HOW]
Poniters, such as stream_enc and dc->bw_vbios, are null checked previously
in the same function, so Coverity warns "implies that stream_enc and
dc->bw_vbios might be null". They are used multiple times in the
subsequent code and need to be checked.
This fixes 10 FORW
From: Alex Hung
[WHAT & HOW]
Poniters, such as dc->clk_mgr, are null checked previously in the same
function, so Coverity warns "implies that "dc->clk_mgr" might be null".
As a result, these pointers need to be checked when used again.
This fixes 10 FORWARD_NULL issues reported by Coverity.
Rev
From: Alex Hung
[WHAT & HOW]
Functions dp_enable_link_phy and dp_disable_link_phy can pass link_res
without initializing hpo_dp_link_enc and it is necessary to check for
null before dereferencing.
This fixes 2 FORWARD_NULL issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-b
From: Samson Tam
[Why]
Make SPL library dc-independent so it can be reused by other
components
[How]
Create separate set of fixed31_32 calls in SPL
Make all inputs and outputs to SPL use primitive types
For ratios and inits, return as uint32 from SPL. So
add conversion from uint32 back to fix
From: Alvin Lee
[Description]
There are scenarios where ODM4:1 is used but the
surface is entirely outside of the first and last
ODM slice. In this case the recout.width for the
first and last slice is 0 because there's no overlap
with the surface and that ODM slice, but this causes
the x_pos for
From: Nevenko Stupar
[Why & How]
Current logic in mcache admissibility check has flaw if
calculated number of maches are 3 or more per surface,
so sometimes the check may pass when it should fail,
and sometimes may fail when it should pass, fix the
issue and also adding additional check to make s
From: Dillon Varone
[WHY&HOW]
OTG has new functionality to allow P-State relative to VStartup. Keepout region
for this should be configured based on DML outputs same as other global sync
params.
Reviewed-by: Alvin Lee
Signed-off-by: Jerry Zuo
Signed-off-by: Dillon Varone
---
.../dc/dce110/dc
From: Dillon Varone
[WHY]
DML2.1 currently has no concept of a "blanked" stream. For cases like DPMS off,
things like UCLK p-state is always allowed, so PMO is not required to optimize
for it.
[HOW]
Add flag to DML2.1 display configuration to indicate all streams are blanked,
so certain operatio
From: Tom Chung
[Why & How]
Fixed the replay issues and now re-enable the panel replay feature.
Reported-by: Arthur Borsboom
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3344
Reviewed-by: Mario Limonciello
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Tom
From: Tom Chung
[Why]
Sometimes the VRR cannot enable after login to the desktop.
User space may call the DRM_IOCTL_MODE_GETCONNECTOR right after
the DRM_IOCTL_MODE_RMFB.
After calling DRM_IOCTL_MODE_RMFB to remove all the frame buffer
and it will cause the driver to disable the crtc and disabl
From: Mounika Adhuri
[Why]
To refactor MPC files
[How]
Moved MPC files to respective folders and
updated makefiles appropriately.
Reviewed-by: Martin Leung
Signed-off-by: Jerry Zuo
Signed-off-by: Mounika Adhuri
---
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 1 -
drivers/gpu/drm/amd/di
From: Sung Joon Kim
[why]
To determine which block instance to power-gate,
we look at the available pipe resource for both plane
and stream. On MPO, DSC3 was falsely powered on even
though only 1 stream path was enabled because
the resource mapping was not done correctly.
[how]
Acquire the corre
From: Revalla Hari Krishna
[Why]
To refactor MMHUBBUB files
[How]
Moved mmhubbub files from dcn20 to /mmhubbub/ folder and
update makefile to fix compilation.
Reviewed-by: Martin Leung
Signed-off-by: Jerry Zuo
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/display/dc/dcn20/Make
From: Alex Hung
[WHAT & HOW]
amdgpu_dm can pass a null stream to dc_is_stream_unchanged. It is
necessary to check for null before dereferencing them.
This fixes 1 FORWARD_NULL issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Alex Hung
---
dri
From: Chris Park
[Why]
When DC state create DML memory allocation fails, memory is not
deallocated subsequently, resulting in uninitialized structure
that is not NULL.
[How]
Deallocate memory if DML memory allocation fails.
Reviewed-by: Joshua Aberback
Signed-off-by: Jerry Zuo
Signed-off-by:
From: Alex Hung
[WHAT & HOW]
These pointers are null checked previously in the same function,
indicating they might be null as reported by Coverity. As a result,
they need to be checked when used again.
This fixes 3 FORWARD_NULL issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-
From: Alex Hung
[WHAT & HOW]
"dcn20_validate_apply_pipe_split_flags" dereferences merge, and thus it
cannot be a null pointer. Let's pass a valid pointer to avoid null
dereference.
This fixes 2 FORWARD_NULL issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Si
From: Alex Hung
dcn32_enable_phantom_stream can return null, so returned value
must be checked before used.
This fixes 1 NULL_RETURNS issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/resource/dcn32
From: Alex Hung
[WHAT & HOW]
drr_timing and subvp_pipe are initialized to null and they are not
always assigned new values. It is necessary to check for null before
dereferencing.
This fixes 2 FORWARD_NULL issues reported by Coverity.
Reviewed-by: Nevenko Stupar
Reviewed-by: Rodrigo Siqueira
From: Revalla Hari Krishna
[Why]
To refactor OPP files
[How]
Moved opp related files to specific opp folder and
updated Makefiles.
Acked-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/display/dc/dcn10/Makefile| 1 -
drivers/gpu
From: Alex Hung
[WHAT & HOW]
Variables used as denominators and maybe not assigned to other values,
should not be 0. Change their default to 1 so they are never 0.
This fixes 10 DIVIDE_BY_ZERO issues reported by Coverity.
Reviewed-by: Harry Wentland
Signed-off-by: Jerry Zuo
Signed-off-by: Ale
From: Gabe Teeger
[why]
Hotplugging with a DVI-DP dongle on pre-rdna embedded platform
working about half the time. The regression was found to be the
setting of link->type here.
[what]
Reverts feb0593 besides the logging added.
Reviewed-by: Wenjing Liu
Signed-off-by: Jerry Zuo
Signed-off-by:
From: Jingwen Zhu
[Why]
This is a workaround for an dcn3.1 hang that happens if otg dispclk
is ramped while otg is on and stream enc is off.
But this w/a should not trigger when we have a dig active.
[How]
Avoid disable otg when dig FE/BE FIFO was not switched.
Acked-by: Rodrigo Siqueira
Signe
From: Alvin Lee
[Description]
- There are situations where HW cursor is required
- In these scenarios we should disable subvp based on the HW cursor
requirement
Reviewed-by: Dillon Varone
Signed-off-by: Jerry Zuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c
From: Alvin Lee
We resync the FIFO after each pipe update in apply_ctx_to_hw.
However, this means that some pipes (in hardware) are based on the
new context and some are based on the current_state (since the pipes
are updated on at a time). In this case we must ensure to use the
pipe_ctx that's c
From: Sridevi Arvindekar
Added option to allow transition for forced odm.
Add the variation to the nightly run.
Reviewed-by: Wenjing Liu
Signed-off-by: Jerry Zuo
Signed-off-by: Sridevi Arvindekar
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dc_stream
From: Relja Vojvodic
why:
New scaler needs the input to be full range color space. This will also fix
issues that come up due to not having a predefined limited color space matrix
for certain color spaces
how:
Use bias and scale HW to expand the range of limited color spaces to full
before the s
From: Wenjing Liu
[why]
The mux to switch between refclk and dto_dsc_clk is non double buffered.
However dto dsc clk's phase and modulo divider registers are currently
configured as double buffered update. This causes a problem when we switch to
use dto dsc clk and program phase and modulo in the
From: Wenjing Liu
[why]
Based on power measurement result, in most cases when display clock is higher
than Vmin display clock, lowering display clock using dynamic ODM will improve
overall power consumption by 0 to 4 watts even if we can't reach Vmin.
[how]
Allow vmin optimization applied even i
From: Alex Hung
This reverts commit d788be646098e6f4fc26763a213bd4fb94a04e13 due to a
power consumption regression.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jerry Zuo
Signed-off-by: Alex Hung
---
.../amd/display/modules/hdcp/hdcp1_execution.c | 18 +-
1 file changed, 9 in
From: Roman Li
[Why]
When assert in dp_retrieve_lttpr_cap() is hit, dmesg has traces like:
RIP: 0010:dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu]
Call Trace:
dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu]
report_bug+0x1e8/0x240
handle_bug+0x46/0x80
link_detect+0x35/0x580 [amdgpu]
It happens
From: Alvin Lee
[Description]
For no plane scenarios we should not consider cursor as there cannot
be any cursor if there's no planes. This fixes an issue where
dc_commit_streams fails due to prefetch bandwidth requirements
(the display config + dummy planes + cursor causes the prefetch
bandwidt
From: Alvin Lee
[Description]
Due to a HW bug, HBR audio is not supported for
DP2 encoders for certain ASICs.
Reviewed-by: Alvin Lee
Signed-off-by: Jerry Zuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce
From: Ryan Seto
[Why]
Added clock logs to automate DPM testing
[How]
Added logs and helper functions to output clocks
Co-authored-by: Ryan Seto
Reviewed-by: Alvin Lee
Signed-off-by: Jerry Zuo
Signed-off-by: Ryan Seto
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 250 ++---
This DC patchset brings improvements in multiple areas.
* FW Release 0.0.225.0
* DML2 fixes
* Re-enable panel replay feature
* Allow display DCC for DCN401
* Refactor DWB, OPP, MPC, MMHUBBUB
* Fix dscclk Programming issue on DCN401
Cc: Daniel Wheeler
Alex Hung (11):
drm/amd/display: Revert "C
From: Tom Chung
[Why]
The VRR need to be supported for panel replay feature.
If VRR capability is false, panel replay capability also
need to be disabled.
[How]
After update the vrr capability, the panel replay capability
also need to be check if need.
Reviewed-by: Wayne Lin
Signed-off-by: Jer
On Wed, Jul 10, 2024 at 2:10 PM wrote:
>
> From: Boyuan Zhang
>
> Determine whether VCN using unified queue in sw_init, instead of calling
> functions later on.
>
> Signed-off-by: Boyuan Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 39 ++---
> drivers/gpu/drm/amd/
From: Boyuan Zhang
For unified queue, DPG pause for encoding is done inside VCN firmware,
so there is no need to pause dpg based on ring type in kernel.
For previous generations, pausing DPG for encoding in kernel is still needed.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amd
From: Boyuan Zhang
Determine whether VCN using unified queue in sw_init, instead of calling
functions later on.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 39 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
2 files changed, 16 insertion
As part of the S3 suspend sequence dGPUs will evict VRAM. If there is
high memory pressure at this time, there is a chance this fails.
systemd has a policy to try to "fall back" from S3 to s2idle and see
if that works. When under high memory pressure this also fails, and
harder. Really we don't
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, July 9, 2024 05:51
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, July 10, 2024 22:15
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: rem
This will enable display DCC for Wayland because Mesa already exposes
modifiers with DCC. Has it been tested?
Marek
On Mon, Jul 8, 2024 at 12:06 PM Aurabindo Pillai
wrote:
>
> To enable mesa to use display dcc, DM should expose them in the
> supported modifiers. Add the best (most efficient) mod
Enable it by default.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index f927ccd7ec45..b241f61fe9c9 100644
--- a/dr
On Wed, Jul 10, 2024 at 5:50 AM Li Ma wrote:
>
> Enables following UMD stable Pstates profile levels
> of power_dpm_force_performance_level for SMU v14.0.4.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: Li Ma
Acked-by: Alex D
Ping on this series?
Alex
On Mon, Jul 8, 2024 at 6:30 PM Alex Deucher wrote:
>
> Fixes the indexing of the string array.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.
On 10/07/2024 07:03, Paneer Selvam, Arunpravin wrote:
Thanks Alex.
Hi Matthew,
Any comments?
Do we not pass the required address alignment when allocating the pages
in the first place?
Thanks,
Arun.
On 7/9/2024 1:42 AM, Alex Deucher wrote:
On Thu, Jul 4, 2024 at 4:40 AM Arunpravin Panee
Am 10.07.24 um 12:15 schrieb Zhu, Jiadong:
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Christian König
Sent: Wednesday, July 10, 2024 5:27 PM
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org;
Deucher, Alexander
Subject: Re: [PATCH v2] drm/amdgpu:
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Christian König
> Sent: Wednesday, July 10, 2024 5:27 PM
> To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org;
> Deucher, Alexander
> Subject: Re: [PATCH v2] drm/amdgpu: set start timestamp of fence in th
Enables following UMD stable Pstates profile levels
of power_dpm_force_performance_level for SMU v14.0.4.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Li Ma
---
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 18 +++---
1 fi
Am 10.07.24 um 09:54 schrieb Zhu, Jiadong:
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Christian König
Sent: Wednesday, July 10, 2024 3:17 PM
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/amdgpu: set start timestamp o
On Tue, Jul 09, 2024 at 10:02:08AM -0400, Hamza Mahfooz wrote:
> On 7/9/24 06:09, Daniel Vetter wrote:
> > On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
> > > On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
> > > > Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm,
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Christian König
> Sent: Wednesday, July 10, 2024 3:17 PM
> To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2] drm/amdgpu: set start timestamp of fence in the
> right place
>
> Am
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Christian König
> Sent: Wednesday, July 10, 2024 3:17 PM
> To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2] drm/amdgpu: set start timestamp of fence in the
> right place
>
> Am
Am 10.07.24 um 02:31 schrieb jiadong@amd.com:
From: Jiadong Zhu
The job's embedded fence is dma_fence which shall not be conversed
to amdgpu_fence.
Good catch.
The start timestamp shall be saved on job for
hw_fence.
But NAK to that approach. Why do we need the start time here in the
Hello,
I updated my system today to Debian trixie and noticed the following
error messages in my dmesg with 6.10.0-rc6 / 6.10.0-rc7.
...
[ 11.902016] amdgpu :0b:00.0: [drm] *ERROR*
dc_dmub_srv_log_diagnostic_data: DMCUB error - collecting diagnostic data
...
Full dmesg:
https://tg.st/u/a4
To avoid reports of NULL_RETURN warning, we should add
otg_master NULL check.
Cc: sta...@vger.kernel.org
Fixes: c51d87202d1f ("drm/amd/display: do not attempt ODM power optimization if
minimal transition doesn't exist")
Signed-off-by: Ma Ke
---
Changes in v2:
- added the recipient's email addres
On Wed, Jul 3, 2024 at 10:11 AM wrote:
>
> Got it.
> I had some mental block about passing designated intializers as macro args.
> it just worked, I needed to eyeball the .i file just to be sure.
> thanks.
> I have a fixup patch.
> whats the best thing to do with it, squash it in for later ? send
On 30.06.24 01:18, Mikhail Gavrilov wrote:
> On Sat, Jun 29, 2024 at 9:46 PM Rodrigo Siqueira Jordao
> wrote:
>>
>> I'm trying to reproduce this issue, but until now, I've been unable to
>> reproduce it. I tried some different scenarios with the following
>> components:
>>
>> 1. Displays: I tried
On Wed, Jul 10, 2024 at 12:01 PM Mikhail Gavrilov
wrote:
>
> On Tue, Jul 9, 2024 at 7:48 PM Rodrigo Siqueira Jordao
> wrote:
> > Hi,
> >
> > I also tried it with 6900XT. I got the same results on my side.
>
> This is weird.
>
> > Anyway, I could not reproduce the issue with the below components.
On Tue, Jul 9, 2024 at 7:48 PM Rodrigo Siqueira Jordao
wrote:
> Hi,
>
> I also tried it with 6900XT. I got the same results on my side.
This is weird.
> Anyway, I could not reproduce the issue with the below components. I may
> be missing something that will trigger this bug; in this sense, coul
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