if we simply replace
MAX_SURFACE_NUM with MAX_SURFACES = 3, will we still need these explicit fails?
FWICT, `dc_state_add_plane` should fail for us.
Thanks,
Leo
ret = drm_atomic_add_affected_planes(state, crtc);
if (ret)
goto fail;
@@ -11769,8 +11
[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Acked-by: Leo Liu
> -Original Message-
> From: Zhang, Boyuan
> Sent: October 24, 2024 10:35 PM
> To: amd-gfx@lists.freedesktop.org; Liu, Leo ; Koenig,
> Christian ; Deucher, Alexander
> ; Khatri,
On 2024-10-23 09:53, Melissa Wen wrote:
There are two events to trace the beginning and the end of
amdgpu_dm_atomic_commit_tail, but only the one ate the beginning was
placed. Place amdgpu_dm_atomic_commit_tail_finish tracepoint at the end
than.
Signed-off-by: Melissa Wen
Reviewed-by: Leo
/dmesg.log
[1]
Link:
https://gitlab.freedesktop.org/drm/amd/uploads/8f13ff3b00963c833e23e68aa8116959/output.log
[2]
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2645
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
Thanks
---
---
drivers/gpu/drm/amd/display/modules/power
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Leo Liu
> -Original Message-
> From: amd-gfx On Behalf Of Lijo
> Lazar
> Sent: October 18, 2024 2:41 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
>
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Lazar, Lijo
> Sent: October 17, 2024 9:17 AM
> To: Liu, Leo ; Koenig, Christian
> ; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Sundararaju, Sathishk
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Lazar, Lijo
> Sent: October 16, 2024 11:18 PM
> To: Liu, Leo ; Koenig, Christian
> ; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Sundararaju, S
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Koenig, Christian
> Sent: October 16, 2024 9:16 AM
> To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org; Liu, Leo
>
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Sundararaju, Sathishk
ted panel. Does setting
amdgpu.dcdebugmask=0x10 on your kernel cmdline help? This force disables PSR.
Another flag to try is amdgpu.dcdebugmask=0x800, which allows PSR but disables
idle power optimizations. I wonder if that may be causing extra latency.
- Leo
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Leo Liu
> -Original Message-
> From: Jamadar, Saleemkhan
> Sent: September 21, 2024 3:14 AM
> To: Jamadar, Saleemkhan ; Liu, Leo
> ; Rao, Srinath ; Gopalakrishnan,
> Veerabadhran (Veera) ;
> Sund
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Leo Liu
> -Original Message-
> From: Sundararaju, Sathishkumar
> Sent: September 10, 2024 10:32 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo ; Sundararaju, Sathishkumar
>
> Subject: [P
Hi Mikhail,
Can you give this patch a try to see if it helps?
https://gist.github.com/leeonadoh/3271e90ec95d768424c572c970ada743
Thanks,
Leo
On 2024-09-10 11:47, Leo Li wrote:
On 2024-09-08 19:30, Mikhail Gavrilov wrote:
I have done additional tests:
1. The computer does not hang with
update state. However, a KMS cursor
update will only include the cursor plane. It's likely that amdgpu_dm only adds
the dedicated cursor plane to DC's update state, leaving the game's plane out.
The fix isn't exactly trivial. If I don't get anywhere before the fixes window,
I'll send out a revert.
Cheers,
Leo
[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Leo Liu
> -Original Message-
> From: Lazar, Lijo
> Sent: September 6, 2024 4:46 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Liu, Leo ; Jian, Jane
> ; Lu, Vic
anes being used on my setup.
Third, in case these two issues are related, can you give the attached patch on
this issue thread a try as well?
https://gitlab.freedesktop.org/drm/amd/-/issues/3569#note_2558359
Thanks,
Leo
On 2024-09-05 02:06, Mikhail Gavrilov wrote:
On Thu, Sep 5, 2024 at 4:06
On 2024-09-04 18:21, Mikhail Gavrilov wrote:
On Wed, Sep 4, 2024 at 4:15 AM Leo Li wrote:
Hi Mike,
Super sorry for the ridiculous wait. Your first two emails slipped by my inbox,
which is really silly, given I'm first in the to field...
Thanks for bisecting and finding a free ga
le-0002-revert-drm-amd-display-introduce-overlay-cursor-mode-patch
Thanks,
Leo
On 2024-08-27 16:38, Harry Wentland wrote:
On 2024-08-27 15:53, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
DCN IPS interoperates with other system idle power features, such as
Zstates.
On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a
hard hang. We observe this on
improvements for text display and HDR DWM and MPO
- Fix Synaptics Cascaded Panamera DSC Determination
- Allocate DCN35 clock table transfer buffers in GART
- Add Replay Low Refresh Rate parameters in dc type
Signed-off-by: Aric Cyr
Signed-off-by: Zaeem Mohamed
Acked-by: Leo Li
---
drivers
On 2024-08-19 10:41, Harry Wentland wrote:
On 2024-08-16 18:57, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
Idle power states (IPS) describe levels of power-gating within DCN. DM
and DC is responsible for ensuring that we are out of IPS before any DCN
programming happens. Any DCN
[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Acked-by: Leo Liu
> -Original Message-
> From: Sunil Khatri
> Sent: Tuesday, August 13, 2024 7:30 AM
> To: Deucher, Alexander ; Lazar, Lijo
> ; Liu, Leo
> Cc: amd-gfx@lists.freedesktop.
, and I wonder
if it's really necessary. I'll go and find out.
Thanks,
Leo
Signed-off-by: Sebastian Wick
For anyone who hasn't seen it, there has been a bunch of discussions that have
transpired on this topic and what to do about it on [1] as well as some other
linked places o
[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Reviewed-by: Leo Liu
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, August 6, 2024 1:03 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ;
> s
o bit mask
"Require low latency" PSR should be disabled.
When the property is restored to an empty bit mask ABM and PSR
can be enabled again.
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
Thanks!
---
v3->v4:
* Fix enabling again after disable (Xaver)
---
dri
eira
Signed-off-by: Jerry Zuo
Signed-off-by: Tom Chung
Hi Jerry,
Please drop this patch as there's a known PSR SU regression caused by a patch
that originally fixed the aforementioned replay issue.
Thanks,
Leo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 --
o bit mask
"Require low latency" PSR should be disabled.
When the property is restored to an empty bit mask the previous
value of ABM and pSR will be restored.
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
Thanks!
---
v2->v3:
* Use `disallow_edp_enter_psr` i
psr_state = igt_amd_read_psr_state(data->fd, output->name);
igt_assert_f(psr_state == PSR_STATE3,
"Panel not in PSR after clearing power saving policy\n");
Thanks,
Leo
+
+ igt_remove_fb(data->fd, &ref_fb);
+ igt_remove_fb(data->fd, &
ose it should fail given that we've set REQUIRE_COLOR_ACCURACY. Though I'm
not sure why we can't keep target = 3.
Thanks,
Leo
+ r = set_abm_level(data, output, target);
+ igt_assert_eq(r, -1);
+
+ r = clear_power_saving_policy(dat
On 2024-06-10 11:32, Mario Limonciello wrote:
On 6/10/2024 09:55, sunpeng...@amd.com wrote:
From: Leo Li
To fix CONFIG_ACPI disabled build error.
Fixes: ec6f30c776ad ("drm/amd/display: Set default brightness according to
ACPI")
Signed-off-by: Leo Li
---
drivers/gpu/drm/a
lo
Acked-by: Alex Deucher
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 8
3 files changed, 23 insertions(+),
experience intended by the compositor.
Signed-off-by: Mario Limonciello
Acked-by: Leo Li
Thanks!
---
drivers/gpu/drm/drm_connector.c | 46 +
include/drm/drm_connector.h | 2 ++
include/drm/drm_mode_config.h | 5
include/uapi/drm/drm_mode.h
c_state->stream);
+ else if (!dm_old_conn_state->psr_forbidden &&
dm_new_conn_state->psr_forbidden)
+ amdgpu_dm_psr_enable(dm_new_crtc_state->stream);
+
dm_update_crtc_state() can be called as part of atomic check, so we should not
do any hw programmi
[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Leo Liu
> -Original Message-
> From: Wu, David
> Sent: Thursday, May 30, 2024 10:59 AM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
>
> Cc: Deucher, Alexander ; Liu, Leo
> ; Jiang,
On 2024-05-21 13:32, Mario Limonciello wrote:
On 5/21/2024 12:27, Leo Li wrote:
On 2024-05-21 12:21, Mario Limonciello wrote:
On 5/21/2024 11:14, Xaver Hugl wrote:
Am Di., 21. Mai 2024 um 16:00 Uhr schrieb Mario Limonciello
:
On 5/21/2024 08:43, Simon Ser wrote:
This makes sense to
ration in addition to accuracy is latency.
I suppose a compositor may want to disable features such as PSR for use-cases
requiring low latency. Touch and stylus input are some examples.
I wonder if flags would work better than enums? A compositor can set something
like `REQUIRE_ACCURACY & REQUIRE_LOW_LATENCY`, for example.
- Leo
Would be nice to add documentation for the property in the "standard
connector properties" section.
Ack.
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Leo Liu
> -Original Message-
> From: Wu, David
> Sent: Thursday, May 9, 2024 5:37 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
>
> Cc: Koenig, Christian ; Liu, Leo
> ; Jiang, Son
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
> -Original Message-
> From: Wu, David
> Sent: Thursday, May 9, 2024 3:59 PM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
>
> Cc: Deucher, Alexander ; Liu, Leo
> ; Jiang, Sonny
> Subject: [PA
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
> -Original Message-
> From: amd-gfx On Behalf Of Sonny
> Jiang
> Sent: Thursday, April 25, 2024 4:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Jiang, Sonny ; Jiang, Sonny
>
> Subject: [PATCH v3] drm/amd
On 2024-04-16 10:10, Harry Wentland wrote:
On 2024-04-16 04:01, Pekka Paalanen wrote:
On Mon, 15 Apr 2024 18:33:39 -0400
Leo Li wrote:
On 2024-04-15 04:19, Pekka Paalanen wrote:
On Fri, 12 Apr 2024 16:14:28 -0400
Leo Li wrote:
On 2024-04-12 11:31, Alex Deucher wrote:
On Fri
-509,7 +509,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device
> *adev,
> ++num_rings;
> }
> ib_start_alignment = 256;
> - ib_size_alignment = 4;
> + ib_size_alignment = 64;
We don't want these impact on previous HW if
On 2024-04-15 04:19, Pekka Paalanen wrote:
On Fri, 12 Apr 2024 16:14:28 -0400
Leo Li wrote:
On 2024-04-12 11:31, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 11:08 AM Pekka Paalanen
wrote:
On Fri, 12 Apr 2024 10:28:52 -0400
Leo Li wrote:
On 2024-04-12 04:03, Pekka Paalanen wrote
On 2024-04-12 11:31, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 11:08 AM Pekka Paalanen
wrote:
On Fri, 12 Apr 2024 10:28:52 -0400
Leo Li wrote:
On 2024-04-12 04:03, Pekka Paalanen wrote:
On Thu, 11 Apr 2024 16:33:57 -0400
Leo Li wrote:
...
That begs the question of what can be
On 2024-04-12 04:03, Pekka Paalanen wrote:
On Thu, 11 Apr 2024 16:33:57 -0400
Leo Li wrote:
On 2024-04-04 10:22, Marius Vlad wrote:
On Thu, Apr 04, 2024 at 09:59:03AM -0400, Harry Wentland wrote:
Hi all,
On 2024-04-04 06:24, Pekka Paalanen wrote:
On Wed, 3 Apr 2024 17:32:46 -0400
On 2024-04-04 10:22, Marius Vlad wrote:
On Thu, Apr 04, 2024 at 09:59:03AM -0400, Harry Wentland wrote:
Hi all,
On 2024-04-04 06:24, Pekka Paalanen wrote:
On Wed, 3 Apr 2024 17:32:46 -0400
Leo Li wrote:
On 2024-03-28 10:33, Pekka Paalanen wrote:
On Fri, 15 Mar 2024 13:09:56 -0400
On 2024-03-28 10:33, Pekka Paalanen wrote:
On Fri, 15 Mar 2024 13:09:56 -0400
wrote:
From: Leo Li
These patches aim to make the amdgpgu KMS driver play nicer with compositors
when building multi-plane scanout configurations. They do so by:
1. Making cursor behavior more sensible.
2
On 2024-03-28 11:52, Harry Wentland wrote:
On 2024-03-28 11:48, Robert Mader wrote:
Hi,
On 15.03.24 18:09, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
> -Original Message-
> From: Dhume, Samir
> Sent: Friday, March 15, 2024 3:51 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Dhume, Samir ; Lazar, Lijo
> ; Wan, Gavin ; Liu, Leo
> ; Deucher, Alexander
> Sub
[AMD Official Use Only - General]
> -Original Message-
> From: Dhume, Samir
> Sent: Monday, March 4, 2024 10:20 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Dhume, Samir ; Lazar, Lijo
> ; Wan, Gavin ; Liu, Leo
> ; Deucher, Alexander
> Subject: [PATCH 3/3] drm/
[AMD Official Use Only - General]
The series of 4 patches are:
Reviewed-by: Leo Liu
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Wednesday, February 21, 2024 12:00 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Yifan ; Deucher, Alex
licitly set the flag bit in hw_init
> every time and the data is repopulated after a WGR instead of
> assuming the data can survive the WGR.
>
I think this is part of sw_init, along with loading fw. Should not be in the
hw_init. I think you probably can try to save it to a saved_bo whe
The set looks good to me. The series is:
Reviewed-by: Leo Liu
On 2023-10-16 12:54, Bokun Zhang wrote:
- In VCN 4 SRIOV code path, add code to enable RB decouple feature
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 71 +--
1 file changed
t; + union {
> + // 12 DWords
This can be removed.
> + struct {
> + uint32_t rb_addr_lo;
> + uint32_t rb_addr_hi;
> + uint32_t rb_size;
> + uint32_t rb4_addr_lo;
> +
On 2023-10-03 11:23, Lakha, Bhawanpreet wrote:
[AMD Official Use Only - General]
Why not just set replay_feature_enabled = true; to false?
Would that be the right fix? If so, we can send out a patch
with that instead.
- Leo
there's a quick fix, we should
revert for now. It sounds like this can break existing support for
PSR/PSR SU.
Acked-by: Leo Li
- Leo
Bhawan
*From:* LIPSKI, IVAN
*Sent:* October 2, 2023 1:47 PM
*To:* amd-gfx@l
[AMD Official Use Only - General]
Acked-by: Leo Liu
-Original Message-
From: Wu, David
Sent: Thursday, September 21, 2023 3:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Deucher, Alexander
; Liu, Leo
Subject: [PATCH] drm/amdgpu: not to save bo in the case of RAS
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: Sundararaju, Sathishkumar
Sent: Thursday, September 14, 2023 12:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Liu, Leo ; Sundararaju,
Sathishkumar
Subject: [PATCH
ilures
are the only concerns, and I agree that it doesn't make sense to require
zpos to be normalized between 0 and number of planes.
Thanks,
Leo
-
if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
plane_cap &&
(plane_cap->pixel_format_support.nv12 ||
--
2.41.0
The series is:
Acked-by: Leo Liu .
On 2023-08-08 12:26, Samir Dhume wrote:
The structures are the same as v4_0 except for the
init header
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h | 37 +++
1 file changed, 37 insertions
return r;
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
@@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
drm_dev_exit(idx);
}
+ amdgpu_virt_free_mm_table(adev);
Same as
Reviewed-by: Leo Liu
On 2023-07-17 23:20, sguttula wrote:
This patch will enable VCN FW workaround using
DRM KEY INJECT WORKAROUND method,
which is helping in fixing the secure playback.
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message as per veera's feedback
Chang
Reviewed-by: Leo Liu
On 2023-07-17 13:27, sguttula wrote:
This patch will enable secure decode playback on VCN4_0_2
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message only enabling for VCN402
-updated the logic as per Leo's feedback
---
drivers/gpu/drm/amd/amdgpu/vcn
Since the changes will affect multiple ASICs, if you only tested with
VCN4_0_4, please just apply the set to that HW.
Regards,
Leo
On 2023-07-16 23:15, Guttula, Suresh wrote:
Hi Leo,
There are two issues here.
This change fixing the Crash while secure playback and we see below error
= {
.type = AMDGPU_RING_TYPE_VCN_ENC,
.align_mask = 0x3f,
+ .secure_submission_supported = true,
We should set it to true with VCN4_0_4 only for now, and check either
this boolean or VCN4_0_4 with your implementation from patch 2
Regards,
Leo
.nop = VCN_ENC_CMD_NO_OP
On 2023-07-10 16:19, Liu, Leo wrote:
[AMD Official Use Only - General]
[AMD Official Use Only - General]
-Original Message-
From: Jamadar, Saleemkhan
Sent: Monday, July 10, 2023 12:54 PM
To: Jamadar, Saleemkhan ; amd-gfx@lists.freedesktop.org; Liu, Leo
; Gopalakrishnan
[AMD Official Use Only - General]
-Original Message-
From: Jamadar, Saleemkhan
Sent: Monday, July 10, 2023 12:54 PM
To: Jamadar, Saleemkhan ;
amd-gfx@lists.freedesktop.org; Liu, Leo ; Gopalakrishnan,
Veerabadhran (Veera) ; Sundararaju,
Sathishkumar
Cc: Koenig, Christian ; Rao
[AMD Official Use Only - General]
-Original Message-
From: Jamadar, Saleemkhan
Sent: Monday, July 10, 2023 4:24 AM
To: Jamadar, Saleemkhan ;
amd-gfx@lists.freedesktop.org; Liu, Leo ; Gopalakrishnan,
Veerabadhran (Veera) ; Sundararaju,
Sathishkumar
Cc: Koenig, Christian ; Rao, Srinath
It looks good to me. The series is:
Reviewed-by: Leo Liu
On 2023-06-27 00:48, Lang Yu wrote:
Replace the old ones with psp_execute_load_ip_fw_cmd_buf.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 31 -
drivers/gpu/drm/amd/amdgpu
sure that also please specify the SRIOV from your patch
subject and commit message.
Regards,
Leo
On 2023-06-30 07:38, Christian König wrote:
Am 20.06.23 um 15:29 schrieb Horace Chen:
[Why]
VCN will use some framebuffer space as its cache. It needs to
be reset when reset happens, such as FLR
z
Cc: Tsung-hua (Ryan) Lin
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
---
v1->v2:
* Fix a s/dcn31/dcn314/ mixup
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c | 5 +
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h | 2 ++
drivers/gpu/drm/amd/display/
newer firmware.
Cc: Sean Wang
Cc: Marc Rossi
Cc: Hamza Mahfooz
Cc: Tsung-hua (Ryan) Lin
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
---
v1->v2:
* Fix a s/dcn314/dcn31/ mixup
---
drivers/gpu/drm/amd/display/a
On 6/22/23 14:25, Mario Limonciello wrote:
This reverts commit 33eec907ce0eb50a56dca621aa7310f7fa904b93.
This is no longer necessary when using newer DMUB F/W.
Cc: Sean Wang
Cc: Marc Rossi
Cc: Hamza Mahfooz
Cc: Tsung-hua (Ryan) Lin
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
: Mario Limonciello
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 7c9a2b34bd05..2a66a305679a 100644
_ASIC_DCN316) {
dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
- else
+ } else {
dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
+ }
Should these hunks be rolled into 3/4? dmub_dcn314_is_psrsu_supported i
Reviewed-by: Leo Liu
On 2023-06-20 21:29, Emily Deng wrote:
Need to unpause dpg first, or it will hit follow error during stop dpg:
"[drm] Register(1) [regUVD_POWER_STATUS] failed to reach value 0x0001 !=
0xn"
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/
ed in
fill_dc_dirty_rect().
Cc: sta...@vger.kernel.org # 6.1+
Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support")
Signed-off-by: Hamza Mahfooz
Reviewed-by: Leo Li
Thanks!
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 -
1 file changed, 4 i
?
Regards,
Leo
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Monday, June 19, 2023 6:24 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/vcn: Need to pause dpg before stop dpg
Need to pause dpg first, or it will hit follow error during stop
[Public]
Reviewed-by: Leo Liu
From: amd-gfx on behalf of Sonny Jiang
Sent: June 8, 2023 10:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Jiang, Sonny
Subject: [PATCH] drm/amdgpu: vcn_4_0 set instance 0 init sched score to 1
From: Sonny Jiang
Only vcn0 can
/7414
- Leo
On 2/9/23 04:27, Mikhail Gavrilov wrote:
Harry, please don't ignore me.
This issue still happens in 6.1 and 6.2
Leo you are the author of the problematic commit please don't stand aside.
Really nobody is interested in clean logs without warnings and errors?
I am 100% sure that
: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff
...@amd.com
Cc: Joshua Ashton
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Leo Li
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 -
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 54 +++
2 files changed, 56 insertions
[AMD Official Use Only - General]
The series are:
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: January 17, 2023 3:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/4] drm/amdgpu/nv: don't expose AV1 if VC
Secure part requires PSP load VCN boot sequence which is with indirect sram
mode.
Regards,
Leo
From: Alex Deucher
Sent: January 16, 2023 4:50 PM
To: Guilherme G. Piccoli
Cc: amd-gfx@lists.freedesktop.org ; Jiang, Sonny
; ker...@gpiccoli.net ; Pan, Xinhui
.. 129.421993: amdgpu_cs:
bo_list=92ffdb4c3400, ring=0, dw=48, fences=0
Fixes: 4624459c84d7 ("drm/amdgpu: add gang submit frontend v6")
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: January 10, 2023 5:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/vcn4: add missing encoder cap
VCN4.x supports AV1
of the condition?
if (!(link->connector_signal & SIGNAL_TYPE_EDP))
return true;
Thanks,
Leo
+ return true;
+
+ pic_height = stream->timing.v_addressable +
+ stream->timing.v_border_top + stream->timing.v_border_bottom;
+ slice_height = pic_height / st
Please try the latest AMDGPU driver:
https://gitlab.freedesktop.org/agd5f/linux/-/commits/amd-staging-drm-next/
On 2022-12-07 15:54, Alex Deucher wrote:
+ Leo, Thong
On Wed, Dec 7, 2022 at 3:43 PM Mikhail Gavrilov
wrote:
On Wed, Dec 7, 2022 at 7:58 PM Alex Deucher wrote:
What GPU do you
ts in fill_dc_dirty_rects().
Signed-off-by: Hamza Mahfooz
Thanks for the patch, it LGTM.
Reviewed-by: Leo Li
It would be good to add an IGT case to cover combinations of MPO &
damage clip commits. Perhaps something that covers the usecase of moving
a MPO video, while desktop UI updates. We'd
So that uses PSP to initialize HW.
Fixes: 0c2c02b6 (drm/amdgpu/vcn: add firmware support for dimgrey_cavefish)
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm
to
dc_dirty_rects. Otherwise, fallback to old FFU logic.
With MPO, the damage clips are more interesting, since the entire
plane's bounding box can be moved. I wonder if that is reflected in
DRM's damage clips. Do you know if a plane bb change will be reflected
in drm_pla
t are only useful for debugging PSR
(and confusing otherwise). So, we can instead limit the filling of dirty
rectangles to only when PSR is enabled.
Signed-off-by: Hamza Mahfooz
Reviewed-by: Leo Li
Thanks
---
v2: give a more concrete reason.
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.
On 2022-10-07 00:28, Shirish S wrote:
[Why]
If psr_feature_enable is set to true by default, it continues to be enabled
for non capable links.
[How]
explicitly disable the feature on links that are not capable of the same.
Signed-off-by: Shirish S
Reviewed-by: Leo Li
Thanks
On 2022-10-06 03:46, S, Shirish wrote:
On 10/6/2022 4:33 AM, Leo Li wrote:
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr feature continues to be enabled for non capable links.
Do you have more info on what
On 2022-09-28 10:53, Hamza Mahfooz wrote:
On 2022-09-28 10:49, sunpeng...@amd.com wrote:
From: Leo Li
On ChromeOS clang build, the following warning is seen:
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
error: variable 'mc_umc_status
On 2022-09-28 09:52, Harry Wentland wrote:
On 2022-09-27 19:13, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we
Hi August,
I've sent a fix here: https://patchwork.freedesktop.org/patch/504993/
It's not the most ideal fix, but it should address the regression. Let
me know it works for you.
Thanks!
Leo
On 2022-09-27 10:22, August Wikerfors wrote:
Hi Leo,
On 2022-09-27 00:29, Leo Li w
sink PSR ver 3 DPCD caps
0x70su_y_granularity 4 force_psrsu_cap **X**
Thanks,
Leo
On 2022-09-23 16:26, August Wikerfors wrote:
Hi Leo,
On 2022-09-23 20:41, Leo Li wrote:
Hi August,
Can you provide a dmesg log with drm.debug=0x16 enabled in kernel
cmdline?
Log is available here:
https://nam11.safelinks.pr
hat's hitting a
corner case. The dmesg will shed some light.
Thanks
Leo
On 2022-09-22 14:13, August Wikerfors wrote:
Hi Alex,
On 2022-09-22 15:59, Alex Deucher wrote:
On Thu, Sep 22, 2022 at 8:54 AM Thorsten Leemhuis
wrote:
Hi, this is your Linux kernel regression tracker. Top-postin
Reviewed-by: Leo Liu
On 2022-09-22 15:30, Ruijing Dong wrote:
update VF_RB_SETUP_FLAG, add SMU_DPM_INTERFACE_FLAG,
and corresponding change in VCN4.
Signed-off-by: Ruijing Dong
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 8 +++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4
2
st happen to use the same HW ring as legacy
encode ring, so reuse the value, and that is the whole idea.
Thanks,
Leo
Instead we should just add the comment to AMDGPU_HW_IP_VCN_ENC.
Regards,
Christian.
#define AMDGPU_HW_IP_VCN_JPEG 8
#define AMDGPU_HW_IP_NUM 9
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