Hi,
On Wednesday, October 05, 2016 12:17 PM, Cornelius Hempel wrote:
At this stage, we are just trying to get an understanding of the size and
functional requirements (FPGA space and features) at the verilog level - which
both Trung, our FPGA engineer, and Moglabs speak.
you can simply look
Hi,
At this stage, we are just trying to get an understanding of the size and
functional requirements (FPGA space and features) at the verilog level - which
both Trung, our FPGA engineer, and Moglabs speak.
So just the pre-bitstream verilog code would be sufficient to get a feel for
it.
If
Hi,
On Wednesday, October 05, 2016 09:49 AM, Trung Nguyen wrote:
My goal is to extract the Verilog comprising that gets compiled into the
FPGA bitstream in order to establish how and if we can deploy it on
another SPARTAN 6 board (= the pipistrello FPGA) made commercially by
moglabs here in
Dear ARTIQ users,
I'm still trying to set up the Artiq environment in order to be able to
compile the FPGA bitstream code, but I am getting stuck both with ARTIQ 3.0
and 2.0.
My goal is to extract the Verilog comprising that gets compiled into the
FPGA bitstream in order to establish how and if
