Hello Dr. Chris
Thank you so much, this is exactly what we were looking for.
Regards
Arpit Agrawal
On Thu, Sep 21, 2017 at 7:58 PM, Chris Ballance via ARTIQ <
artiq@lists.m-labs.hk> wrote:
> Joe,
>
> Attached is a patch I hacked up a while ago that adds differential IOs to
> the SPIMaster. It i
Joe,
Attached is a patch I hacked up a while ago that adds differential IOs
to the SPIMaster. It is ugly, but hopefully transparent. I don't think I
have tested this on hardware, and this will only work with a single
chip-select line.
Instantiate it like:
phy = spi.SPIMaster(self.platform.re
This was discussed on IRC too...
https://irclog.whitequark.org/m-labs/2017-09-13
https://irclog.whitequark.org/m-labs/2017-09-15
https://irclog.whitequark.org/m-labs/2017-09-16
https://irclog.whitequark.org/m-labs/2017-09-17
The Q&A is much appreciated but we still don't have a solution that
work
Thanks Arpit and Daniel for email responses. Catching up the mailing list...
The path Metlino/Sayma -> FMC -> VHDCI uses LVDS which are driven as
_p and _n pin pairs from the FPGA for each EEM IO line. Each EEM board
has an LVDS receiver that generates local single-ended IO.
> If that is the case
What's the right way to use ARTIQ to drive SPI devices across the VHDCI
bus? The SPIMaster interface appears to take only a single signal for each
of clk, cs_n, mosi and miso.
Has anybody yet interfaced with an SPI device using VHCDI? -Joe
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