Re: [ARTIQ] plans for clock chip, JESD and DAC initialization/configuration

2016-12-17 Thread Grzegorz Kasprowicz via ARTIQ
Just use Aurora IP core or something with similar functionality. You have 2 bidir links, one can be used for DRTIO, second for simple control protocol. >From one side you have some inputs that are repeated on the other side. You can run UART, SPI or whatever you want since it is transparent. I

Re: [ARTIQ] plans for clock chip, JESD and DAC initialization/configuration

2016-12-16 Thread Sébastien Bourdeauducq via ARTIQ
On Saturday, December 17, 2016 12:02 PM, Sébastien Bourdeauducq via ARTIQ wrote: Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on KC705) needs to be running. Strictly speaking: this is needed only for the two-KC705 system. But we might as well use the same scheme

[ARTIQ] plans for clock chip, JESD and DAC initialization/configuration

2016-12-16 Thread Sébastien Bourdeauducq via ARTIQ
Hi, Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on KC705) needs to be running. This setup should be done by the comms CPU on the DRTIO master, and the management CPU on a DRTIO satellite. For initialization, the comms or management CPU would configure the clock